Atmel AVR XMEGA AU series, Manual

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8331B–AVR–03/12
Atmel AVR XMEGA AU
5.14.10 SRCADDR2 – Channel Source Address 2
Reading and writing 24-bit values require special attention. For details, refer to ”Accessing 24-
and 32-bit Registers” on page 13 .
• Bit 7:0 – SRCADDR[23:16]: Channel Source Address 2
These bits hold byte 2 of the 24-bit source address.
5.14.11 DESTADDR0 – Channel Destination Address 0
DESTADDR0, DESTADDR1, and DESTADDR2 represent the 24-bit value DESTADDR, which
is the DMA channel destination address. DESTADDR2 holds the most significant byte in the reg-
ister. DESTADDR may be automatically incremented or decremented based on settings in the
DESTDIR bits in
”ADDRCTRL – Address Control register” on page 63 .
• Bit 7:0 – DESTADDR[7:0]: Channel Destination Address 0
These bits hold byte 0 of the 24-bit source address.
5.14.12 DESTADDR1 – Channel Destination Address 1
• Bit 7:0 – DESTADDR[15:8]: Channel Destination Address 1
These bits hold byte 1 of the 24-bit source address.
5.14.13 DESTADDR2 – Channel Destination Address 2
Reading and writing 24-bit values require special attention. For details, refer to ”Accessing 24-
and 32-bit Registers” on page 13 .
• Bit 7:0 – DESTADDR[23:16]: Channel Destination Address 2
These bits hold byte 2 of the 24-bit source address.
Bit 7 6 5 4 3 2 1 0
+0x0A SRCADDR[23:16] SRCADDR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x0C DESTADDR[7:0] DESTADDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x0D DESTADDR[15:8] DESTADDR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x0E DESTADDR[23:16] DESTADDR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0