231
8331B–AVR–03/12
Atmel AVR XMEGA AU
Synchronization of a new CNT value to the RTC32 domain is triggered by writing CNT3. The
synchronization time is up to 12 peripheral clock cycles from updating the register until this has
an effect in the RTC32 domain. Write operations to the CNT register will be blocked if the SYN-
CBUSY flag is set.
The synchronization of the CNT register value from the RTC32 domain to the system clock
domain can be done by writing one to the SYNCCNT bit in the SYNCCTRL register. The
updated and synchronized CNT register value is available after eight peripheral clock cycles.
After writing to the high byte of the CNT register, the condition for setting OVFIF and COMPIF,
as well as the overflow and compare match wake-up condition, will be disabled for the following
two RTC32 clock cycles.
19.3.6
CNT1 – Counter register 1
19.3.7
CNT2 – Counter register 2
19.3.8
CNT3 – Counter register 3
19.3.9
PER0 – Period register 0
The PER0, PER1, PER2, and PER3 registers represent the 32-bit value, PER. PER is con-
stantly compared with the counter value (CNT). A compare match will set OVFIF in the
INTFLAGS register, and CNT will be set to zero in the next RTC32 clock cycle. OVFIF will be set
on the next count after match.
The PER register can be written only if the RTC32 is disabled and not currently synchronizing;
i.e., when both ENABLE and SYNCBUSY are zero.
Bit
7
6
5
4
3
2
1
0
CNT[7:0]
CNT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CNT[15:8]
CNT1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CNT[23:16]
CNT2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CNT[31:24]
CNT3
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
