279
8331B–AVR–03/12
Atmel AVR XMEGA AU
The baud rate (BAUD) register defines the relation between the system clock and the TWI bus
clock (SCL) frequency. The frequency relation can be expressed by using the following
equation:
[1]
The BAUD register must be set to a value that results in a TWI bus clock frequency (f
TWI
) equal
or less than 100kHz or 400kHz, depending on which standard the application should comply
with. The following equation [2] expresses equation [1] solved for the BAUD value:
[2]
The BAUD register should be written only while the master is disabled.
21.9.6
ADDR
–
Address register
When the address (ADDR) register is written with a slave address and the R/W bit while the bus
is idle, a START condition is issued and the 7-bit slave address and the R/W bit are transmitted
on the bus. If the bus is already owned when ADDR is written, a repeated START is issued. If
the previous transaction was a master read and no acknowledge is sent yet, the acknowledge
action is sent before the repeated START condition.
After completing the operation and the acknowledge bit from the slave is received, the SCL line
is forced low if arbitration was not lost. WIF is set.
If the bus state is unknown when ADDR is written, WIF is set and BUSERR is set.
All TWI master flags are automatically cleared when ADDR is written. This includes BUSERR,
ARBLOST, RIF, and WIF. The master ADDR can be read at any time without interfering with
ongoing bus activity.
21.9.7
DATA
–
Data register
The data (DATA) register is used when transmitting and receiving data. During data transfer,
data are shifted from/to the DATA register and to/from the bus. This implies that the DATA regis-
ter cannot be accessed during byte transfers, and this is prevented by hardware. The DATA
f
TWI
f
sys
2(5
BAUD
(
)
)
+
----------------------------------------
[Hz]
=
BAUD
f
sys
2
f
TWI
--------------
5
–
=
Bit
7
6
5
4
3
2
1
0
ADDR[7:0]
ADDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DATA[7:0]
DATA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
