365
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 28-14.
ADC timing for one single conversion with gain.
28.9.3
Single Conversions on Two ADC Channels
shows the ADC timing for single conversions on two channels. The
pipelined design enables the second conversion to start on the next ADC clock cycle after the
first conversion has started. In this example, both conversions take place at the same time, but
the conversion on ADC channel 1(CH1) does not start until the ADC samples and performs con-
version on the msb on channel 0 (CH0).
Figure 28-15.
ADC timing for single conversions on two ADC channels.
28.9.4
Single Conversions on Two ADC Channels, CH0 with Gain
shows the conversion timing for single conversions on two ADC chan-
nels where ADC channel 0 uses the gain stage. As the gain stage introduces one addition cycle
for the gain sample and amplify, the sample for ADC channel 1 is also delayed one ADC clock
cycle, until the ADC sample and msb conversion is done for ADC channel 0.
ADC SAMPLE
CONVERTING BIT
START
IF
GAINSTAGE SAMPLE
GAINSTAGE AMPLIFY
MSB
10
9
8
7
6
5
4
3
2
1
LSB
CLK
ADC
1
2
3
4
5
6
7
8
9
CLK
ADC
START CH1
ADC SAMPLE
IF CH1
START CH0
IF CH0
CONVERTING BIT CH0
CONVERTING BIT CH1
MSB
10
9
8
7
6
5
4
3
2
1
LSB
1
2
3
4
5
6
7
8
9
MSB
10
9
8
7
6
5
4
3
2
1
LSB
