115
8331B–AVR–03/12
Atmel AVR XMEGA AU
Whenever a reset occurs, the clock system is reset and the internal 2MHz internal oscillator is
chosen as the source for Clk
SYS
.
9.3.2
Oscillator Startup
After the reset delay, the 2MHz internal oscillator clock is started, and its calibration values are
automatically loaded from the calibration row to the calibration registers.
9.4
Reset Sources
9.4.1
Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when
the V
CC
rises and reaches the POR threshold voltage (V
POT
), and this will start the reset
sequence.
The POR is also activated to power down the device properly when the V
CC
falls and drops
below the V
POT
level.
The V
POT
level is higher for falling V
CC
than for rising V
CC
. Consult the datasheet for POR charac-
teristics data.
Figure 9-2.
MCU startup, RESET tied to V
CC
.
Figure 9-3.
MCU startup, RESET extended externally,
9.4.2
Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the V
CC
level during operation by com-
paring it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled,
BOD is forced on at the lowest level during chip erase and when the PDI is enabled.
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC
