264
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 21-2.
Basic TWI transaction diagram topology for a 7-bit address bus .
The master provides the clock signal for the transaction, but a device connected to the bus is
allowed to stretch the low-level period of the clock to decrease the clock speed.
21.3.1
Electrical Characteristics
The TWI module in XMEGA devices follows the electrical specifications and timing of I
2
C bus
and SMBus. These specifications are not 100% compliant, and so to ensure correct behavior,
the inactive bus timeout period should be set in TWI master mode. Refer to
for more details.
21.3.2
START and STOP Conditions
Two unique bus conditions are used for marking the beginning (START) and end (STOP) of a
transaction. The master issues a START condition (S) by indicating a high-to-low transition on
the SDA line while the SCL line is kept high. The master completes the transaction by issuing a
STOP condition (P), indicated by a low-to-high transition on the SDA line while SCL line is kept
high.
Figure 21-3.
START and STOP conditions.
Multiple START conditions can be issued during a single transaction. A START condition that is
not directly following a STOP condition is called a repeated START condition (Sr).
P
S
ADDRESS
6 ... 0
R/W
ACK
ACK
7 ... 0
DATA
ACK/NACK
7 ... 0
DATA
SDA
SCL
S
A
A/A
R/W
ADDRESS
DATA
P
A
DATA
Address Packet
Data Packet #0
Transaction
Data Packet #1
Direction
The slave provides data on the bus
The master provides data on the bus
The master or slave can provide data on the bus
SDA
SCL
START
Condition
STOP
Condition
S
P
