282
8331B–AVR–03/12
Atmel AVR XMEGA AU
Writing the CMD bits will automatically clear the slave interrupt flags and CLKHOLD, and
release the SCL line. The ACKACT bit and CMD bits can be written at the same time, and then
the acknowledge action will be updated before the command is triggered.
21.10.3
STATUS – Status register
• Bit 7
–
DIF: Data Interrupt Flag
This fflag is set when a data byte is successfully received; i.e., no bus error or collision occurred
during the operation. Writing a one to this bit location will clear DIF. When this flag is set, the
slave forces the SCL line low, stretching the TWI clock period. Clearing the interrupt flags will
release the SCL line.
This flag is also cleared automatically when writing a valid command to the CMD bits in the
CTRLB register
• Bit 6
–
APIF: Address/Stop Interrupt Flag
This flag is set when the slave detects that a valid address has been received, or when a trans-
mit collision is detected. If the PIEN bit in the CTRLA register is set, a STOP condition on the
bus will also set APIF. Writing a one to this bit location will clear APIF. When set for an address
interrupt, the slave forces the SCL line low, stretching the TWI clock period. Clearing the inter-
rupt flags will release the SCL line.
The flag is also cleared automatically for the same condition as DIF.
• Bit 5
–
CLKHOLD: Clock Hold
This flag is set when the slave is holding the SCL line low.This is a status flag and a read-only bit
that is set when DIF or APIF is set. Clearing the interrupt flags and releasing the SCL line will
indirectly clear this flag.
11
RESPONSE
Used in response to an address byte
(APIF is set)
0
Execute acknowledge action succeeded by reception
of next byte
1
Execute acknowledge action succeeded by DIF
being set
Used in response to a data byte (DIF is set
)
0
Execute acknowledge action succeeded by waiting
for the next byte
1
No operation
Table 21-8.
TWI slave command. (Continued)
CMD[1:0]
Group
Configuration
DIR
Operation
Bit
7
6
5
4
3
2
1
0
DIF
APIF
CLKHOLD
RXACK
COLL
BUSERR
DIR
AP
STATUS
Read/Write
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
