339
8331B–AVR–03/12
Atmel AVR XMEGA AU
27.5.5
Address Latches
The Address Latch timing and parameter requirements are described in EBI Timing. See the
device datasheet characteristics for details. To reduce access time when using multiplexing of
address, the ALE signals are only issued when it is required to update the latched address. For
instance if address lines A[15:8] are multiplexed with A[7:0] the ALE1 and A[15:8] are only given
if any bit in A[15:8] are changed since the last time ALE was set.
27.5.6
Timing
SRAM or external memory devices may have different timing requirements. To meet these vary-
ing requirements, each Chip Select can be configured with different wait-states. Timing details
are described in the device datasheet.
27.6
SRAM LPC Configuration
The SRAM Low Pin Count (LPC) configuration enables EBI to be configured for multiplexing
modes where the data and address lines are multiplexed. Compared to SRAM configuration,
this can further reduce the number of pins required for the EBI. The available configurations is
shown in
”Multiplexing Data with Address Byte 0” on page 339
through
Address Byte 0 and 1” on page 339
.
Timing and Address Latch requirements is as for SRAM configuration.
27.6.1
Multiplexing Data with Address Byte 0
When the data byte and address byte 0 (AD[7:0]) are multiplexed, they are output from the same
port, and the ALE1 signal from the device controls the address latch.
Figure 27-7.
Multiplexed SRAM LPC connection using ALE1.
27.6.2
Multiplexing Data with Address Byte 0 and 1
When the data byte and address byte 0 (AD[7:0]), and address byte 1 (A[15:8]) are multiplexed,
they are output from the same port, and the ALE1 and ALE2 signal from the device control the
external address latches.
EBI
SRAM
AD[7:0]
ALE1
D
Q
G
D[7:0]
A[7:0]
A[15:8]
A[19:16]
A[19:16]
A[15:8]
