257
8331B–AVR–03/12
Atmel AVR XMEGA AU
interrupts or software intervention. See
”Multipacket Transfers” on page 243
packet transfers.
• Bit 4 – PINGPONG: Ping-pong Enable
Setting this bit enables ping-pong operation. Ping-pong operation enables both endpoints (IN
and OUT) with same address to be used in the same direction to allow double buffering and
maximize throughput. The endpoint in the opposite direction must be disabled when ping-pong
operation is enabled. Ping-pong operation is not possible for control endpoints. See
for details.
• Bit 3 – INTDSBL: Interrupt Disable
Setting this bit disables all enabled interrupts from the endpoint. Hence, only the interrupt flags
in the STATUS register are updated when interrupt conditions occur. The FIFO does not store
this endpoint configuration table address upon transaction complete for the endpoint when inter-
rupts are disabled for an endpoint. Clearing this bit enables all previously enables interrupts
again.
• Bit 2 – STALL: Endpoint STALL
This bit controls the STALL behavior if the endpoint.
• Bit 1:0 – BUFSIZE[1:0]: Data Size
These bits configure the maximum data payload size for the endpoint. Incoming data bytes
exceeding the maximum data payload size are discarded.
• Bit 2:0 – BUFSIZE[2:0]: Data Size
These bits configure the maximum data payload size for the endpoint when configured for iso-
chronous operation.
Note:
1. Setting only available for isochronous endpoints.
20.14.3
CNTL – Counter Low
The CNTL and CNTH registers represent the 10-bit value, CNT, that contains the number of
bytes received in the last OUT or SETUP transaction for an OUT endpoint, or the number of
bytes to be sent in the next IN transaction for an IN endpoint.
Table 20-5.
BUFSIZE configuration.
BUFSIZE[2:0]
Group Configuration
Description
000
8
8-byte buffer size
001
16
16-byte buffer size
010
32
32-byte buffer size
011
64
64-byte buffer size
100
128
128-byte buffer size
101
256
256-byte buffer size
110
512
512-byte buffer size
111
1023
1023-bytesbuffer size
