Anritsu BERTWave Series, Operation Manual, Page: 176 / 466

Chapter 5 How to Operate BERT
5-10
5.2.3 Setting Patterns
The following three test patterns can be selected.
 PRBS
 1/2 Clock Pattern
 1/16 Clock Pattern
PRBS
PRBS is the pattern generated at the hardware.
The generated pattern length, maximum length of contiguous 1s, and
maximum length of contiguous 0s differ depending on the hardware
configuration.
The following block diagram indicates the hardware generating PRBS
2^7–1.
Figure 5.2.3-1 Block Diagram for PRBS Generating Circuit
This block diagram is composed of a shift register composed of a
seven-stage flip-flop and an Exclusive OR circuit. A signal of the sixth and
seventh stages of the shift register are input to the Exclusive OR and the
output of the Exclusive OR is input to the shift register. This type of
configuration is described by the following pattern generation polynomial.
1 + X
6
+ X
7
When inputting the default value of 7 bits and impressing the clock, a
pattern with a bit length of 2
7
–1 = 127 is repeatedly generated. The
default value of seven bits includes 1 or more “1” bits.
The following shows the pattern length, maximum number of contiguous
1s, and maximum number of contiguous 0s using the PRBS generation
formula of the MP2110A.
D Q D Q D Q D Q D Q D Q D Q
Clock
Output
Flip-flop
×
7
Exclusive OR
1 2 3 4 5 6 7
Initial value