Section 8 Caches
Rev.1.00 Dec. 13, 2005 Page 216 of 1286
REJ09B0158-0100
8.6
Memory-Mapped Cache Configuration
To enable the IC and OC to be managed by software, the IC contents can be read from or written
to by a program in the P2 area by means of a MOV instruction in privileged mode. Operation is
not guaranteed if access is made from a program in another area. In this case, execute one of the
following three methods for executing a branch to the P0, U0, P1, or P3 area.
1. Execute a branch using the RTE instruction.
2. Execute a branch to the P0, U0, P1, or P3 area after executing the ICBI instruction for any
address (including non-cacheable area).
3. If the MC bit in IRMCR is 0 (initial value) before making an access to the memory-mapped
IC, the specific instruction does not need to be executed. However, note that the CPU
processing performance will be lowered because the instruction fetch is performed again for
the next instruction after making an access to the memory-mapped IC.
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
In privileged mode, the OC contents can be read from or written to by a program in the P1 or P2
area by means of a MOV instruction. Operation is not guaranteed if access is made from a
program in another area. The IC and OC are allocated to the P4 area in the virtual address space.
Only data accesses can be used on both the IC address array and data array and the OC address
array and data array, and accesses are always longword-size. Instruction fetches cannot be
performed in these areas. For reserved bits, a write value of 0 should be specified and the read
value is undefined.
Содержание SH7780 Series
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Страница 122: ...Section 3 Instruction Set Rev 1 00 Dec 13 2005 Page 72 of 1286 REJ09B0158 0100 ...
Страница 146: ...Section 4 Pipelining Rev 1 00 Dec 13 2005 Page 96 of 1286 REJ09B0158 0100 ...
Страница 196: ...Section 6 Floating Point Unit FPU Rev 1 00 Dec 13 2005 Page 146 of 1286 REJ09B0158 0100 ...
Страница 292: ...Section 9 L Memory Rev 1 00 Dec 13 2005 Page 242 of 1286 REJ09B0158 0100 ...
Страница 450: ...Section 11 Local Bus State Controller LBSC Rev 1 00 Dec 13 2005 Page 400 of 1286 REJ09B0158 0100 ...
Страница 492: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Dec 13 2005 Page 442 of 1286 REJ09B0158 0100 ...
Страница 674: ...Section 15 Clock Pulse Generator CPG Rev 1 00 Dec 13 2005 Page 624 of 1286 REJ09B0158 0100 ...
Страница 692: ...Section 16 Watchdog Timer and Reset Rev 1 00 Dec 13 2005 Page 642 of 1286 REJ09B0158 0100 ...
Страница 726: ...Section 18 Timer Unit TMU Rev 1 00 Dec 13 2005 Page 676 of 1286 REJ09B0158 0100 ...
Страница 1004: ...Section 24 Multimedia Card Interface MMCIF Rev 1 00 Dec 13 2005 Page 954 of 1286 REJ09B0158 0100 ...
Страница 1032: ...Section 25 Audio Codec Interface HAC Rev 1 00 Dec 13 2005 Page 982 of 1286 REJ09B0158 0100 ...
Страница 1070: ...Section 26 Serial Sound Interface SSI Module Rev 1 00 Dec 13 2005 Page 1020 of 1286 REJ09B0158 0100 ...
Страница 1104: ...Section 27 NAND Flash Memory Controller FLCTL Rev 1 00 Dec 13 2005 Page 1054 of 1286 REJ09B0158 0100 ...
Страница 1150: ...Section 28 General Purpose I O GPIO Rev 1 00 Dec 13 2005 Page 1100 of 1286 REJ09B0158 0100 ...
Страница 1184: ...Section 29 User Break Controller UBC Rev 1 00 Dec 13 2005 Page 1134 of 1286 REJ09B0158 0100 ...
Страница 1266: ...Section 31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1216 of 1286 REJ09B0158 0100 ...
Страница 1328: ...Appendix Rev 1 00 Dec 13 2005 Page 1278 of 1286 REJ09B0158 0100 ...
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