Section 10 Interrupt Controller (INTC)
Rev.1.00 Dec. 13, 2005 Page 297 of 1286
REJ09B0158-0100
upward compatibility with the “level-sense IRQ mode” of current SH-4 products (here, too, the
detection of high or low levels is selectable).
Note: When high-or low-level detection is selected, once the interrupt request has been detected,
the INTC holds the interrupt request as an interrupt source in INTREQ even if the level on
the IRQ interrupt pin has been changed and canceled. The interrupt source is held until the
CPU accepts any interrupt request (IRQ or not) or the corresponding interrupt mask bit is
set to 1. Moreover, when the holding function is selected by clearing the LSH bit in ICR0
to 0, the interrupt request is held in the detection circuit. In this case, clearing of the
interrupt request in the exception handling routine must be followed by clearing of the
interrupt source setting being held in INTREQ. For details, see section 10.7 Usage Notes.
When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is
automatically modified to the level of an accepted interrupt. When the INTMU bit is cleared to 0,
the IMASK value in SR is not affected by the acceptance of an interrupt.
10.4.3 IRL
Interrupts
IRL interrupts are input as combinations of levels on pins IRQ/
IRL7
to IRQ/
IRL4
or IRQ/
IRL3
to
IRQ/
IRL0
. The priority level is the value indicated by the levels (active low) on pins IRQ/
IRL7
to
IRQ/
IRL4
or IRQ/
IRL3
to IRQ/
IRL0
. The low level on all pins from IRQ/
IRL7
to IRQ/
IRL4
or
IRQ/
IRL3
to IRQ/
IRL0
corresponds to the highest-level interrupt request (interrupt priority level
15), and the high level on all pins corresponds to no interrupt request (interrupt priority level 0).
Figure 10.2 shows an example of IRL interrupt connection, and table 10.11 shows the
correspondence between the combinations of levels on the IRL pins and priority.
Priority
encoder
Interrupt
requests
SH7780
IRQ/
IRL3
to
IRQ/
IRL0
IRQ/
IRL7
to
IRQ/
IRL4
IRL7
to
IRL4
IRL3
to
IRL0
Interrupt
requests
Priority
encoder
..
.
..
.
Figure 10.2 Example of IRL Interrupt Connection
Содержание SH7780 Series
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