Rev.1.00 Dec. 13, 2005 Page xxxi of l
Figure 11.2 Correspondence between Virtual Address Space and External Memory
Space of LBSC........................................................................................................ 321
Figure 11.3 External Memory Space Allocation (29-bit address mode)..................................... 323
Figure 11.4 Basic Timing of SRAM Interface............................................................................ 362
Figure 11.5 Example of 32-Bit Data-Width SRAM Connection................................................ 363
Figure 11.6 Example of 16-Bit Data-Width SRAM Connection................................................ 364
Figure 11.7 Example of 8-Bit Data-Width SRAM Connection.................................................. 365
Figure 11.8 SRAM Interface Wait Timing (Software Wait Only) ............................................. 366
Figure 11.9 SRAM Interface Wait Timing
(Wait Cycle Insertion by
RDY
Signal,
RDY
Signal is synchronous input) ............ 367
Figure 11.10 SRAM Interface Wait Timing (Read-Strobe Negate Timing Setting) .................. 369
Figure 11.11 Burst ROM Basic Timing...................................................................................... 371
Figure 11.12 Burst ROM Wait Timing....................................................................................... 371
Figure 11.13 Burst ROM Wait Timing....................................................................................... 372
Figure 11.14
CExx
and
DACK
Output of ATA Complement Mode in DMA Transfer............. 374
Figure 11.15 Example of PCMCIA Interface ............................................................................. 377
Figure 11.16 Basic Timing for PCMCIA Memory Card Interface ............................................. 378
Figure 11.17 Wait Timing for PCMCIA Memory Card Interface .............................................. 379
Figure 11.18 Basic Timing for PCMCIA I/O Card Interface ..................................................... 380
Figure 11.19 Wait Timing for PCMCIA I/O Card Interface ...................................................... 381
Figure 11.20 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................. 382
Figure 11.21 Example of 32-Bit Data Width MPX Connection................................................. 384
Figure 11.22 MPX Interface Timing 1 (Single Read Cycle, IW
=
0, No External Wait) ........... 384
Figure 11.23 MPX Interface Timing 2 (Single Read, IW
=
0, One External Wait Inserted)...... 385
Figure 11.24 MPX Interface Timing 3 (Single Write Cycle, IW
=
0, No External Wait) .......... 385
Figure 11.25 MPX Interface Timing 4
(Single Write Cycle, IW
=
1, One External Wait Inserted).................................. 386
Figure 11.26 MPX Interface Timing 5
(Burst Read Cycle, IW
=
0, No External Wait, 32-Byte Data Transfer) ............... 386
Figure 11.27 MPX Interface Timing 6
(Burst Read Cycle, IW
=
0, External Wait Control, 32-Byte Data Transfer)........ 387
Figure 11.28 MPX Interface Timing 7
(Burst Write Cycle, IW
=
0, No External Wait, 32-Byte Data Transfer) .............. 387
Figure 11.29 MPX Interface Timing 8
(Burst Write Cycle, IW
=
1, External Wait Control, 32-Byte Data Transfer) ....... 388
Figure 11.30 Example of 32-Bit Data-Width Byte-Control SRAM ........................................... 389
Figure 11.31 Byte-Control SRAM Basic Read Cycle (No Wait) ............................................... 390
Figure 11.32 Byte-Control SRAM Basic Read Cycle (One Internal Wait Cycle)...................... 391
Figure 11.33 Byte-Control SRAM Basic Read Cycle
(One Internal Wait
+
One External Wait).............................................................. 392
Содержание SH7780 Series
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Страница 82: ...Section 1 Overview Rev 1 00 Dec 13 2005 Page 32 of 1286 REJ09B0158 0100 ...
Страница 122: ...Section 3 Instruction Set Rev 1 00 Dec 13 2005 Page 72 of 1286 REJ09B0158 0100 ...
Страница 146: ...Section 4 Pipelining Rev 1 00 Dec 13 2005 Page 96 of 1286 REJ09B0158 0100 ...
Страница 196: ...Section 6 Floating Point Unit FPU Rev 1 00 Dec 13 2005 Page 146 of 1286 REJ09B0158 0100 ...
Страница 292: ...Section 9 L Memory Rev 1 00 Dec 13 2005 Page 242 of 1286 REJ09B0158 0100 ...
Страница 450: ...Section 11 Local Bus State Controller LBSC Rev 1 00 Dec 13 2005 Page 400 of 1286 REJ09B0158 0100 ...
Страница 492: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Dec 13 2005 Page 442 of 1286 REJ09B0158 0100 ...
Страница 674: ...Section 15 Clock Pulse Generator CPG Rev 1 00 Dec 13 2005 Page 624 of 1286 REJ09B0158 0100 ...
Страница 692: ...Section 16 Watchdog Timer and Reset Rev 1 00 Dec 13 2005 Page 642 of 1286 REJ09B0158 0100 ...
Страница 726: ...Section 18 Timer Unit TMU Rev 1 00 Dec 13 2005 Page 676 of 1286 REJ09B0158 0100 ...
Страница 1004: ...Section 24 Multimedia Card Interface MMCIF Rev 1 00 Dec 13 2005 Page 954 of 1286 REJ09B0158 0100 ...
Страница 1032: ...Section 25 Audio Codec Interface HAC Rev 1 00 Dec 13 2005 Page 982 of 1286 REJ09B0158 0100 ...
Страница 1070: ...Section 26 Serial Sound Interface SSI Module Rev 1 00 Dec 13 2005 Page 1020 of 1286 REJ09B0158 0100 ...
Страница 1104: ...Section 27 NAND Flash Memory Controller FLCTL Rev 1 00 Dec 13 2005 Page 1054 of 1286 REJ09B0158 0100 ...
Страница 1150: ...Section 28 General Purpose I O GPIO Rev 1 00 Dec 13 2005 Page 1100 of 1286 REJ09B0158 0100 ...
Страница 1184: ...Section 29 User Break Controller UBC Rev 1 00 Dec 13 2005 Page 1134 of 1286 REJ09B0158 0100 ...
Страница 1266: ...Section 31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1216 of 1286 REJ09B0158 0100 ...
Страница 1328: ...Appendix Rev 1 00 Dec 13 2005 Page 1278 of 1286 REJ09B0158 0100 ...
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