Section 10 Interrupt Controller (INTC)
Rev.1.00 Dec. 13, 2005 Page 273 of 1286
REJ09B0158-0100
10.3.8 User
Interrupt
Mask
Level Register (USERIMASK)
USERIMASK is a 32-bit readable and conditionally writable register that sets the acceptable
interrupt level. When addresses in area 7 are accessed by using the MMU’s address translation
function, USERIMASK can be accessed in user mode. Since only USERIMASK is allocated to
the 64-Kbyte page (other INTC registers are allocated to a different area), it can be set to be
accessible in user mode.
Interrupts with priority levels lower than the level set in the UIMASK bits are masked. When the
value H'F is set in the UIMASK bit, all interrupts other than the NMI are masked.
Interrupts with priority levels higher than the level set in the UIMASK bits are accepted under the
following conditions.
•
The corresponding interrupt mask bit in the interrupt mask register is cleared to 0 (the interrupt
is enabled).
•
The priority level setting in the IMASK bits in also SR is lower than that of the interrupt.
Even if an interrupt is accepted, the UIMASK value does not change.
USERIMASK is initialized to H'0000 0000 (all interrupts are enabled) on return from a power-on
reset or manual reset.
To prevent incorrect writing, the value written to bits 31 to 24 must always be set to H'A5.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WKEY (H'A5)
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
UIMASK
R
R
R
R
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
Содержание SH7780 Series
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Страница 122: ...Section 3 Instruction Set Rev 1 00 Dec 13 2005 Page 72 of 1286 REJ09B0158 0100 ...
Страница 146: ...Section 4 Pipelining Rev 1 00 Dec 13 2005 Page 96 of 1286 REJ09B0158 0100 ...
Страница 196: ...Section 6 Floating Point Unit FPU Rev 1 00 Dec 13 2005 Page 146 of 1286 REJ09B0158 0100 ...
Страница 292: ...Section 9 L Memory Rev 1 00 Dec 13 2005 Page 242 of 1286 REJ09B0158 0100 ...
Страница 450: ...Section 11 Local Bus State Controller LBSC Rev 1 00 Dec 13 2005 Page 400 of 1286 REJ09B0158 0100 ...
Страница 492: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Dec 13 2005 Page 442 of 1286 REJ09B0158 0100 ...
Страница 674: ...Section 15 Clock Pulse Generator CPG Rev 1 00 Dec 13 2005 Page 624 of 1286 REJ09B0158 0100 ...
Страница 692: ...Section 16 Watchdog Timer and Reset Rev 1 00 Dec 13 2005 Page 642 of 1286 REJ09B0158 0100 ...
Страница 726: ...Section 18 Timer Unit TMU Rev 1 00 Dec 13 2005 Page 676 of 1286 REJ09B0158 0100 ...
Страница 1004: ...Section 24 Multimedia Card Interface MMCIF Rev 1 00 Dec 13 2005 Page 954 of 1286 REJ09B0158 0100 ...
Страница 1032: ...Section 25 Audio Codec Interface HAC Rev 1 00 Dec 13 2005 Page 982 of 1286 REJ09B0158 0100 ...
Страница 1070: ...Section 26 Serial Sound Interface SSI Module Rev 1 00 Dec 13 2005 Page 1020 of 1286 REJ09B0158 0100 ...
Страница 1104: ...Section 27 NAND Flash Memory Controller FLCTL Rev 1 00 Dec 13 2005 Page 1054 of 1286 REJ09B0158 0100 ...
Страница 1150: ...Section 28 General Purpose I O GPIO Rev 1 00 Dec 13 2005 Page 1100 of 1286 REJ09B0158 0100 ...
Страница 1184: ...Section 29 User Break Controller UBC Rev 1 00 Dec 13 2005 Page 1134 of 1286 REJ09B0158 0100 ...
Страница 1266: ...Section 31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1216 of 1286 REJ09B0158 0100 ...
Страница 1328: ...Appendix Rev 1 00 Dec 13 2005 Page 1278 of 1286 REJ09B0158 0100 ...
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