2-20 Setup and Operation
Advanced Chipset Control
Select the “Advanced Chipset Control” submenu on the Advanced menu to set PCI
parameters.
NOTE:
A Supervisor password might be
required to select parameters from the Advanced
Chipset Control submenu.
Use the legend keys to make your selections and exit to the Main menu. See Table Section
2-10 to configure your peripherals.
CAUTION:
Setting items in this menu to
incorrect values can cause your system to
malfunction.
Table Section 2-10 Advanced Chipset Control Parameters
Parameter
Options
Description
1 MB Memory Gap at
15 MB
Enable
Disable
If Enabled, turn system RAM off to free
address space for use with option
board. Memory from 15 MB to 16 MB
is disabled, creating 1 MB gap in
system RAM.
CPU to PCI Write
Buffer
Enable
Disable
Enables CPU to PCI Write Buffer,
allowing data to be temporarily stored in
buffer before writing data.
PCI to DRAM Write
Buffer
Enable
Disable
Enables PCI to DRAM Write Buffer,
allowing data to be temporarily stored in
buffer before writing data.
CPU to DRAM Write
Buffer
Enable
Disable
Enables CPU to DRAM Write Buffer,
allowing data to be temporarily stored in
buffer before writing data.
PCI Memory Burst
Cycles
Enable
Disable
Enables PCI memory burst write cycles.
Latency Timer Value
A0 through F0
20 through 90
Sets maximum number of PCI bus
clocks that PCMC may burst as a
master.
CAS# Before RAS#
Refresh
Enable
Disable
If Enabled, the PCMC uses CAS#
before RAS# timing to refresh DRAM
array. If Disabled, RAS# only refresh
is used.
Burst of 4 Refresh
Enable
Disable
If Enabled, refreshes are performed in
sets of four at a frequency of 1/4 of
normal refresh rate. If Disabled, single
refreshes occur at 15.6 ms refresh rate.