Technical Information 1-7
PCI-EISA Bridge Component (PCEB)
The PCEB is one of the two chips that connect the PCI bus to to the EISA bus. The PCEB
translates bus protocols from EISA to PCI and vice versa. Extensive buffering of both the
PCI and EISA interface allows for concurrent operations. Address decoding is provided for
both PCI and EISA. For further details, refer to the
Intel PCI–EISA Bridge (PCEB)
Component Specification
.
EISA System Component (ESC)
The ESC interfaces the PCI bus to the EISA bus. The ESC supplements the PCEB by
implementing such system functions as the Timer/ Counter, DMA and interrupt controllers,
and EISA subsystem control functions (such as the Bus Controller and Bus Arbiter).
Interrupt level assignments are provided later in this section (see “Interrupt Controller”).
For further details, refer to the
Intel EISA System Component (ESC) Specification
.
Bus Architecture
The interconnection of the major system components via the address and data buses is
shown in Figure Section 1-2
.
The number range next to each bus arrow indicates the bits
on the bus the arrow represents. Major buses include the host bus, system memory bus, the
PCI bus, the EISA bus, and the XD bus. The function of these buses is described in the
following subsections.