1-24 Technical Information
EISA expansion slot connector pin assignments are provided in Appendix B.
Figure Section 1-3 EISA Connector
Various DMA cycle types are needed to cover the speed and complex requirements of
different applications. In EISA systems, control signals, address lines, and the data bus use
a bus clock generated by the system board as the transfer reference. Since the bus clock is
not a fixed frequency, the protocol synchronizes the bus cycles to a common clock to
achieve maximum performance.
EISA DMA devices can be programmed for high-performance data transfers using one of
four DMA cycle types. Compatible cycles (the default) supply a higher data transfer than
ISA. The improvement is the result of EISA faster bus arbitration. Type A and type B
cycles permit some ISA-compatible DMA devices to achieve an even higher performance
level. The Burst DMA cycle (type C) provides the highest performance cycle and is only
available to DMA devices designed specifically for Burst. (Burst cycles require 1 clock per
transfer). Table Section 1-6 shows the data transfer rates for each cycle type and the
compatible DMA devices.
Tab Notch
Tab
ISA Expansion
Board
EISA Expansion
Board
EISA Connector