1-20 Technical Information
5, 6, and 7: Cache module present bits (Read only)
Bits 7, 6, 5:
0, 0, 0 equals 512 KB synchronous
1, 0, 0 equals 256 KB synchronous
1, 0, 1 equals 256 KB asynchronous
1, 1, 1 equals no cache
All other combinations have no meaning
Keyboard Controller Ports
The 87C42 has a command/status port at I/O address 64h and a read/write register at
address 60h. Commands written to the keyboard controller are written to I/O address 64h.
If the command contains two bytes, the second byte is written to I/O address 64h.
The keyboard status register is used to read the status of the keyboard controller. This port
is accessed via Phoenix Technologies, Limited (PTL) extended commands.
Bit 0
Output buffer full
A byte is present in the output buffer when this bit is set.
Bit 1
Input buffer full
A byte is present in the keyboard controller input buffer when this bit is set.
Bit 2
System flag
When this bit is set, the system is in a run time state. When clear (hardware reset), the
system is in a cold boot state. The BIOS uses this bit to sense a hot reset.
Bit 3
Command/data flag
When this bit is set, it indicates the byte in the input buffer is a keyboard controller
command. When clear, it indicates the byte in the input buffer is the data portion of a
keyboard controller command or a command for the keyboard.
1
2
3
4
5
6
7
Parity
Error
Timeout
Auxiliary
Buffer
Full
Command/
Data Flag
System
Flag
Input
Buffer Full
Keyboard/
Auxiliary
Inhibit Switch
0
Output
Buffer
Full