1-12 Technical Information
Flash ROM programming is supported only in the 0F0000h – 0FFFFh area. The system
and Video BIOS area of the Flash ROM (upper 64 KB) can be erased, programmed, and
verified normally with the RPG0 bit set low (to 0). To erase, program, and verify the SCSI
BIOS and ACU area (lower 64 bits) the RPG0 bit must be set high (to 1). This allows
access to the lower 64 KB of the Flash ROM via the 0F000h to 0FFFFFh area.
To upgrade the BIOS, see Section 4, Maintenance and Troubleshooting, for BIOS upgrade
information.
On-Board Peripherals
The following subsections describe the computer’s on-board peripheral control circuitry.
The peripherals interface with the computer through either the PCI or EISA buses.
SCSI Circuitry
The SCSI circuitry is controlled by the Adaptec AIC-7850 PCI bus to SCSI bus controller.
SCSI bus connectivity allows connection to SCSI-compatible peripherals, such as high-
capacity floppy drives, tape drives, and CD-ROMs. The AIC-7850 can support data
transfer rates of up to 10 MBs per second. For further information, refer to the
Adaptec
AIC-7850
data manual.
IDE Controller
The CMD PCIO640B IDE controller supports up to four IDE hard disks. The PCIO640B
supports both primary and secondary IDE devices. Automatic sensing of EISA hard disk
controllers is provided. If the BIOS senses an EISA hard disk controller, the on-board IDE
interface is disabled. For further information, refer to the
CMD PCIO640B
data manual.
Video Circuitry
The Tseng W32P PCI graphics accelerator features a graphical user interface (GUI)
accelerator and advanced features for the developing imaging and multimedia markets. For
further information, refer to the
Tseng W32P
data manual.
EISA SRAM
A 6264LP 8Kx8 static RAM is used to configure the EISA bus. This SRAM receives its
power from the bq4287 real-time clock (RTC), which uses a lithium battery. The 6264LP
is located on the EISA bus.