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KATANA S610M Inverter Specialized for Elevator Manual
disconnected, the terminal is inactive.
Negative logic: when output terminal is connected with corresponding common port, the terminal is inactive; when they are
disconnected, the terminal is active.
When BIT digit is set to 0, it refers to positive logic, when it is set to 1, it is negative logic.
Figure 6-6 Output terminal activeness setting
F07.19
Frequency arrival (FAR) detected
width
0.00
～
100.0Hz
2.50
This parameter is a complementary definition to function 2 in Table 6-5, as shown in Figure 6-7. When the inverter output
frequency falls within the detected positive & negative width of the set frequency, the terminal outputs pulse signal.
Figure 6-7 Frequency arrival signal output sketch
F07.21
FDT1 level
0.00
～
100.0Hz
50.00
F07.22
FDT1 delay
0.00
～
100.0Hz
1.00
F07.23
FDT2 level
0.00
～
100.0Hz
25.00
F07.24
FDT2 delay
0.00
～
100.0Hz
1.00
F07.21
～
F07.22 are complementary definitions to function 3 in Table 6-5. F07.23
～
F07.24 are complementary definitions to
function 4 in Table 6-5. F07.21
～
F07.22 are for same use as F07.21
～
F07.22. Take F07.21
～
F07.22 use as an example:
When output frequency exceeds the set frequency (FDT1 level), the terminal outputs indicating signal until output frequency
drops lower than FDT1 level (within FDT1 level ~ FDT1 delay), as shown in Figure 6-8.
Tens digit
Units digit
BIT0: positive & negative logic definition of Y1
BIT1: positive & negative logic definition of Y2
BIT2: positive & negative logic definition of relay 1
BIT3: positive & negative logic definition of relay 2
BIT0: positive & negative logic definition of relay 3
Detected
width
Time
Y
Set
freque
ncy
Output
Time
