Systemsoftware
System- and communication configuring D7-SYS - SIMADYN D
2-29
Edition 03.2001
If the CPU should generate a basic clock cycle itself, the following
settings must be made in the dialog field „Basic clock cycle“ (refer to Fig.
Dialog field, basic clock cycle in HWConfig):
•
Activate the „Generate“ button with a mouse click.
•
Enter the required basic sampling time from 0.1 to 16 ms.
In the lower section of the window it can be defined as to whether the
selected CPU should be used as the source for the basic clock cycle. The
appropriate bus must be set for this purpose. „No“ is pre-assigned
(default).
If the basic clock cycle is to be synchronized to another source,
HWConfig requires the following settings:
•
Activate the „Synchronizing“ button with a mouse click.
•
Select the required source from a list, e. g.
L- or C-bus basic clock cycle
L- or C-bus interrupt (SIMADYN D)
bus interrupt (SIMATIC TDC)
•
Enter an equivalent sampling time of 0.1 to 16 ms.
Pre-assignment = 1.0 ms (default)
•
If required, enter a synchronization delay time of 0.1 ms up to the
equivalent sampling time.
No sampling time is pre-assigned (default value)
Basic clock cycle
generated by the
CPU itself
Synchronizing the
basic clock cycle
to a source.
