Systemsoftware
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System- and communication configuring D7-SYS - SIMADYN D
Edition 03.2001
2.1.8.3 Synchronizing its own basic clock cycle to an interrupt task of a
master CPU
At the start or at the end of an interrupt task of a transmitting CPU, it is
possible to initiate an L- or C-bus interrupt. This can be received from one
or several other receiver CPUs where it is then used to generate the
basic clock cycle.
2.1.8.4 Synchronizing its own interrupt tasks to interrupt tasks of a master
CPU
To synchronize an interrupt task it is possible to use an L- or C-bus
interrupt, initiated at the start or the end of an interrupt task from a
transmitter CPU. This interrupt can be received at one or several other
receiver CPUs in order to initiate an interrupt-controlled task there.
2.1.8.5 Synchronizing several SIMATIC TDC/SIMADYN D stations
CS12, CS13 and CS14 modules (master rack coupling) and CS22 (slave
rack coupling) (SIMADYN D) or CP52M0, CP52IO and CP52A0
(SIMATIC TDC) are available to synchronize the basic sampling time
over several stations. In this case, the bus systems of the two stations
are connected via coupling modules.
Further information
on synchronization please refer to the "System and communication
configuring D7-SYS" Manual.
2.1.8.6 Response when the synchronization fails
The basic clock cycle is monitored on the synchronized receiver CPUs
using a hardware timer. If the transmitted clock is no longer available for
4 cycles, the basic clock timer on the CPU module, generates the basic
clock cycle. The basic sampling time configured in HWConfig is used as
basis, which in this case serves as the equivalent sampling time. The
changeover to the basic clock cycle of the CPU is signaled by a flashing
"E" on the 7-segment display of the CPU module, and is flagged in the
error field. When the external clock source kicks in again, this can be
again used on the basic sampling time clock receiver using the “DTS"
function block type.
2.1.8.7 Configuring the CPU basic clock cycle synchronization
The configuring is set in the dialog window "Basic clock cycle" of
HWConfig (refer to the Chapter "Significance and use of CPU
synchronization). The synchronization is disabled as default.
