Renesas M32R/ECU Series, User Manual

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13
32180 Group User’s Manual (Rev.1.0)
13.2 CAN Module Related Registers
CAN MODULE
CAN0 Error Interrupt Request Status Register (CAN0ERIST) <Address: H’0080 1014>
CAN1 Error Interrupt Request Status Register (CAN1ERIST) <Address: H’0080 1414>
1 2 3 4 5 6 b7 b0
BEIS EPIS EOIS
0 0 0 0 0 0 0 0
<After reset: H’00>
b Bit Name Function R W
0–4 No function assigned. Fix to "0". 0 0
5 BEIS 0: Interrupt not requested R(Note 1)
CAN bus error interrupt request status bit 1: Interrupt requested
6 EPIS
Error passive interrupt request status bit
7 EOIS
Bus off interrupt request status bit
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write.
When using CAN interrupts, if the interrupt request sources are associated with errors, this register helps to
know which source generated the interrupt.
(1) BEIS (CAN Bus Error Interrupt Request Status) bit (Bit 5)
The BEIS bit is set to "1" when a communication error is detected. This bit is cleared by writing "0" in soft-
ware.
(2) EPIS (Error Passive Interrupt Request Status) bit (Bit 6)
The EPIS bit is set to "1" when the CAN module goes to an error passive state. This bit is cleared by writing
"0" in software.
(3) EOIS (Bus Off Interrupt Request Status) bit (Bit 7)
The EOIS bit is set to "1" when the CAN module goes to a bus off passive state. This bit is cleared by writing
"0" in software.
When writing to the CAN error interrupt request status, make sure only the bits to be cleared are set to "0" and
all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain
the value they had before the write.