Renesas M32R/ECU Series, User Manual

Page: 810 / 839

Appendix 4
Appendix
4-5
32180 Group User's Manual (Rev. 1.0)
SUMMARY OF PRECAUTIONS
Appendix 4.7 Precautions about the DMAC
Appendix 4.7.1 About Writing to the DMAC Related Registers
Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can
only be accessed for write immediately after reset or when transfer is disabled (transfer enable bit = "0"). When
transfer is enabled, do not write to the DMAC related registers, except the DMA transfer enable bit, the transfer
request flag, and the DMA Transfer Count Register that is protected in hardware. This is a precaution necessary
to ensure stable DMA operation.
The table below lists the registers that can or cannot be accessed for write.
Table 4.7.1 DMAC Related Registers That Can or Cannot Be Accessed for Write
Status Transfer enable bit Transfer request flag Other DMAC related registers
Transfer enabled Can be accessed Can be accessed Cannot be accessed
Transfer disabled Can be accessed Can be accessed Can be accessed
Even for registers that can exceptionally be written to while transfer is enabled, the following conditions must be
observed:
(1) DMA Channel Control Register 0 transfer enable bit and transfer request flag
For all other bits in this register, be sure to write the same data that those bits had before the write. Note,
however, that only writing "0" is effective for the transfer request flag.
(2) DMA Transfer Count Register
When transfer is enabled, this register is protected in hardware, so that any data rewritten to it is ignored.
(3) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer
Although this operation means accessing the DMAC related registers while DMA is enabled, there is no
problem. Note, however, that no data can be transferred by DMA to the DMAC related registers on the
currently active channel itself.
Appendix 4.7.2 Manipulating the DMAC Related Registers by DMA Transfer
When manipulating the DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related
registers with the initial values by DMA transfer), do not write to the DMAC related registers on the currently
active channel through that channel. (If this precaution is neglected, device operation cannot be guaranteed.)
It is only the DMAC related registers on other channels that can be rewritten by means of DMA transfer. (For
example, the DMAn Source Address and DMAn Destination Address Registers on channel 1 can be rewritten by
DMA transfer through channel 0.)
Appendix 4.7.3 About the DMA Interrupt Request Status Register
When clearing the DMA Interrupt Request Status Register, be sure to write "1" to all bits, except those to be
cleared. Writing "1" to any bits in this register has no effect, so that they retain the data they had before the write.
Appendix 4.7.4 About the Stable Operation of DMA Transfer
To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the channel
control register’s transfer enable bit, unless transfer is disabled. One exception is that even when transfer is
enabled, the DMA Source Address and DMA Destination Address Registers can be rewritten by DMA transfer
from one channel to another.
Appendix 4.7 Precautions about the DMAC