Renesas M32R/ECU Series, User Manual

Page: 522 / 839

12
12-31
Serial I/O
12.3 Transmit Operation in CSIO Mode
32180 Group User's Manual (Rev.1.0)
Figure 12.3.4 Example of CSIO Transmission (Transmitted Successively)
Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit
Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: When transmission finished interrupt is enable
Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared
Note 5: A transmit interrupt request is generated when transmission is enabled.
Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the
data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.
Note 7: A transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which
transmission of the transmit shift register data has finished or when the transmit enable bit is cleared.
Note 8: It is inhibited to select the transmission finished interrupt when an external clock is selected.
: Interrupt request generated : Processing by software
Transmit enable bit
Transmit buffer empty bit
Transmit status bit
TXD
SIO transmit interrupt request
(Note 1)
Transmit clock
(SCLKO)
<CSIO on transmit side>
<CSIO on transmit side>
<CSIO on receive side>
SCLKO
TXD
SCLKI
RXD
b7 b6 b5 b0 b7 b6 b5 b0
(Note 2)
(Note 5)
(Note 2)
(Note 2)(Note 6)
Next data is written at a transmit
buffer empty interrupt
First data Next data
Write to the
transmit buffer
register
(First data) (Next data)
Write to the
transmit buffer
register
Cleared
Internal clock selected External clock selected
Set
(Internal transfer clock)
(When transmit buffer empty
interrupt is selected)
(When transmission finished
interrupt is selected) (Note 8)
(Note 3)
Transmit interrupt request
(Note 3)(Note 7)
Interrupt request accepted (Note 4)
Interrupt request accepted (Note 4)