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32180 Group User’s Manual (Rev.1.0)
CAN MODULE
13.2 CAN Module Related Registers
(1) RBO (Return Bus Off) bit (Bit 4)
Setting this bit to "1" clears the CAN Receive Error Count Register (CANnREC) and CAN Transmit Error
Count Register (CANnTEC) to H'00 and forcibly places the CAN module into an error active state. This bit is
cleared when the CAN module goes to an error active state.
Note: • Communication becomes possible when 11 consecutive recessive bits are detected on the
CAN bus after clearing the error counters.
(2) TSR (Timestamp Counter Reset) bit (Bit 5)
Setting this bit to "1" clears the value of the CAN Timestamp Count Register (CANnTSTMP) to H’0000. This
bit is cleared after the value of the CAN Timestamp Count Register (CANnTSTMP) is cleared to H’0000.
(3) TSP (Timestamp Prescaler) bits (Bits 6–7)
These bits select the count clock source for the timestamp counter.
Note: • Do not change settings of the TSP bits while CAN is operating (CAN Status Register CRS bit = "0").
(4) FRST (Forcible Reset) bit (Bit 11)
When the FRST bit is set to "1", the CAN module is separated from the CAN bus and the protocol control unit
is reset regardless of whether the CAN module currently is communicating. Up to 5 BCLK periods are re-
quired before the protocol control unit is reset after setting the FRST bit.
Notes: • In order for CAN communication to start, the FRST and RST bits must be cleared to "0".
• If the FRST bit is set to "1" during communication, the CTX pin output goes high immediately
after that. Therefore, setting the FRST bit to "1" while sending CAN frame may cause a CAN
error.
• The CAN Message Slot Control Register’s transmit/receive requests are not cleared for rea-
sons that the FRST or RST bits are set.
• When the protocol control unit is reset by setting the FRST bit to "1", the CAN Timestamp
Count and CAN Transmit/Receive Error Count Registers are initialized to "0".
(5) BCM (BasicCAN Mode) bit (Bit 12)
By setting this bit to "1", the CAN module can be operated in BasicCAN mode.
• Operation during BasicCAN mode
During BasicCAN mode, two local slots—slots 14 and 15—are used as dual buffers, and the received
frames with matching ID are stored alternately in slots 14 and 15 by acceptance filtering. Used for this
acceptance filtering when slot 14 is active (next received frame to be stored in slot 14) are the ID set in
slot 14 and local mask A, and those when slot 15 is active are the ID set in slot 15 and local mask B. Two
types of frames—data frame and remote frame—can be received in this mode. By setting the same ID
and the same mask register value for the two slots, the possibility of loosing messages when, for
example, receiving frames which have many IDs may be reduced.
Summary of Contents for M32R/ECU Series
Page 17: ...12 This page is blank for reasons of layout...
Page 712: ...CHAPTER 18 OSCILLATOR CIRCUIT 18 1 Oscillator Circuit 18 2 Clock Generator Circuit...
Page 794: ...CHAPTER 22 TYPICAL CHARACTERISTICS...
Page 796: ...APPENDIX 1 MECHANICAL SPECIFICAITONS Appendix 1 1 Dimensional Outline Drawing...
Page 798: ...APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2 1 32180 Instruction Processing Time...
Page 802: ...APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3 1 Example Processing of Unused Pins...