Renesas M32R/ECU Series, User Manual, Page: 630 / 839

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32180 Group User’s Manual (Rev.1.0)
CAN MODULE
B'0100 0011
B'0000 0001
B'0100 0001
B'0000 0000
B'0100 0000
Clear the receive request
Set a receive
request
Store the received data
Clear the receive
request
Store the receiv
ed data
Clear the receiv
e request
Finished storing the received data
Finishe
d stor
ing the
receiv
ed data
Clear the receiv
e request
B'0000 0011
B'0100 0111
Store the received data
B'0100 0101
Finished storing
the received
data
B'0000 0111
B'0000 0101
Store the received data
Wait for the
received data
Wait for the received data
Finished storing
the received data
CPU
read
CPU
read
Clear the receive
request
Clear the receive
request
Clear the receive
request
Finished storing
the received data
Store the receiv
ed
data
Clear the receiv
e request
Finished stor
ing
the
receiv
ed data
Clear the receiv
e request
Figure 13.6.2 Operation of the CAN Message Slot Control Register during Data Frame Reception
13.6 Receiving Data Frames
(2) When the receive conditions are met
When the receive conditions in (1) above are met, the CAN module sets the CAN Message Slot Control
Register’s TRSTAT (Transmit/Receive Status) bit and TRFIN (Transmit/Receive Finished) bit to "1" while at
the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is
already set to "1" at this time, the CAN module also sets the ML (Message Lost) bit to "1", indicating that the
message slot has been overwritten. The message slot has both of its ID and DLC fields entirely overwritten
and has an undefined value written in its unused area (e.g., extended ID field during standard frame recep-
tion and an unused data field).
Furthermore, a timestamp count value at which the message was received is written to the CAN Message
Slot Timestamp (C0MSLnTSP, C1MSLnTSP) along with the received data. When the CAN module finished
writing to the message slot, it sets the CAN Slot Interrupt Request Status bit to "1". If the interrupt request for
the slot has been enabled, the CAN module generates an interrupt request and enters a wait state for the
next reception.
(3) When the receive conditions are not met
The received frame is discarded, and the CAN module goes to the next transmit/receive operation without
writing to the message slot.
1 2 3 4 5 6 b7(b15) (b8) b0
RM RR TR RL RA ML TRSTAT TRFIN
0 0 0 0 0 0 0 0
Bit arrangement in the CAN Message Slot Control Register