Renesas M32R/ECU Series User Manual Download

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DMAC

9-27

32180 Group User’s Manual (Rev.1.0)

9.3 Functional Description of the DMAC

9.3.1 DMA Transfer Request Sources

For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are

various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some

internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all

transfers on another DMA channel (cascade mode).

The causes or sources of DMA transfer requests are selected using the transfer request source select bits

REQSLn on each channel (DMAn Channel Control Register 0 bits 2–3) or the extended transfer request source

select bits REQESELn (DMAn Channel Control Register 1 bits 12–15). The tables below list the causes or

sources of DMA transfer requests on each channel.

Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0

REQSL0

DMA Transfer Request Source

DMA Transfer Request Generation Timing

0 0

Software start or one DMA2

When any data is written to the DMA0 Software Request Generation Register

transfer completed

(software start) or when one DMA2 transfer is completed (cascade mode)

0 1

A-D0 conversion completed

When A-D0 conversion is completed

1 0

MJT (TIO8_udf)

When MJT TIO8 underflows

1 1

Extended DMA0 transfer request

The source selected by the DMA0 Channel Control Register 1 (DM0CNT1)

source selected

REQESEL0 bits (see below)

REQESEL0 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

MJT (input event bus 2)

When MJT input event bus 2 signal is generated

0001

MJT (TID0_udf/ovf)

When MJT TID0 underflow/overflow occurs

0010

CAN (CAN0_S0/S15)

When CAN0 slot 0 transmission failed or slot 15 transmission reception finished

0011

MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

A-D0 conversion completed

When A-D0 conversion is completed

1000

MJT (TIN0 input signal)

When MJT TIN0 input signal is generated

1001

MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Settings inhibited

–

1111

9.3 Functional Description of the DMAC

Summary of Contents for M32R/ECU Series

Page 1: ...ubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for...

Page 2: ...2R ECU Series User s Manual 32180 32180 G r o u p Rev 1 0 Jan 24 2003 The latest version of this manual is published at the Mitsubishi microcomputer home page shown above Please make sure you are usin...

Page 3: ...accuracies or typographical errors Mitsubishi Electric Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention t...

Page 4: ...32180 Group User s Manual Rev Date of Issue Contents of Revision Page Changes Made 1 1 Revision History 1 0 Jan 24 2003 First edition issued...

Page 5: ...is bit is always 1 7 Write conditions W This bit can be accessed for write N This bit is write protected 0 To write to this bit always write 0 1 To write to this bit always write 1 Writing to this bit...

Page 6: ...Bit Register CBR CR1 2 4 2 3 3 Interrupt Stack Pointer SPI CR2 and User Stack Pointer SPU CR3 2 4 2 3 4 Backup PC BPC CR6 2 4 2 3 5 Floating point Status Register FPSR CR7 2 5 2 4 Accumulator 2 7 2 5...

Page 7: ...s on EIT 4 22 CHAPTER 5 INTERRUPT CONTROLLER ICU 5 1 Outline of the Interrupt Controller 5 2 5 2 ICU Related Registers 5 4 5 2 1 Interrupt Vector Register 5 5 5 2 2 Interrupt Request Mask Register 5 6...

Page 8: ...CHAPTER 7 RESET 7 1 Outline of Reset 7 2 7 2 Reset Operation 7 2 7 2 1 Reset at Power on 7 3 7 2 2 Reset during Operation 7 3 7 2 3 Reset at Entering RAM Backup Mode 7 3 7 2 4 Reset Vector Relocation...

Page 9: ...ip flop Control Unit 10 26 10 2 6 Interrupt Control Unit 10 35 10 3 TOP Output Related 16 Bit Timer 10 64 10 3 1 Outline of TOP 10 64 10 3 2 Outline of Each Mode of TOP 10 66 10 3 3 TOP Related Regist...

Page 10: ...7 3 TID Control Prescaler Enable Registers 10 141 10 7 4 TID Counters TID0CT TID1CT and TID2CT 10 144 10 7 5 TID Reload Registers TID0RL TID0RL and TID2RL 10 144 10 7 6 Outline of Each Mode of TID 10...

Page 11: ...How to Find Analog Input Voltages 11 33 11 3 2 A D Conversion by Successive Approximation Method 11 34 11 3 3 Comparator Operation 11 35 11 3 4 Calculating the A D Conversion Time 11 36 11 3 5 Accurac...

Page 12: ...tarting UART Reception 12 50 12 7 3 Processing at End of UART Reception 12 50 12 7 4 Example of UART Receive Operation 12 52 12 7 5 Start Bit Detection during UART Reception 12 54 12 8 Fixed Period Cl...

Page 13: ...Real Time Debugger RTD 14 2 14 2 Pin Functions of the RTD 14 3 14 3 Functional Description of the RTD 14 4 14 3 1 Outline of the RTD Operation 14 4 14 3 2 Operation of RDR Real time RAM Content Output...

Page 14: ...18 1 4 System Clock Output Function 18 7 18 1 5 Oscillation Stabilization Time at Power On 18 7 18 2 Clock Generator Circuit 18 8 CHAPTER 19 JTAG 19 1 Outline of JTAG 19 2 19 2 Configuration of the JT...

Page 15: ...CE 3 3 V 0 3 V f XIN 10 MHz 21 14 21 5 Electrical Characteristics when VCCE 3 3 V f XIN 8 MHz 21 15 21 5 1 Recommended Operating Conditions when VCCE 3 3 V 0 3 V f XIN 8 MHz 21 15 21 5 2 D C Character...

Page 16: ...recautions on Using TIO Single Shot Output Mode Appendix 4 9 Appendix 4 8 7 Precautions on Using TIO Delayed Single Shot Output Mode Appendix 4 10 Appendix 4 8 8 Precautions on Using TIO Continuous Ou...

Page 17: ...12 This page is blank for reasons of layout...

Page 18: ...CHAPTER 1 OVERVIEW 1 1 Outline of the 32180 Group 1 2 Block Diagram 1 3 Pin Functions 1 4 Pin Assignments...

Page 19: ...ition to the ordinary load store instructions the M32R FPU supports compound instructions such as Load Address Update and Store Address Update These instructions help to speed up data transfers 2 Five...

Page 20: ...with IEEE 754 stan dards Specifically five exceptions specified in IEEE 754 standards Inexact Underflow Division by Zero Overflow and Invalid Operation and four rounding modes round to nearest round t...

Page 21: ...operating clock frequency for the M32R FPU core internal flash memory and internal RAM BCLK Peripheral clock Defined as f BCLK when it indicates the operating clock frequency for the internal periphe...

Page 22: ...ytes 1 024 Kbytes M32R FPU Core 80 MHz Multiplier Accumulator 32 bits 16 bits 56 bits DMAC 10 channels Multijunction Timer 64 channels Serial I O 6 channels A D Converter 2 A D0 10 bit converter 16 ch...

Page 23: ...rocessor mode Extended external area Maximum 8 Mbytes 1 Mbytes 2 Mbytes 3 blocks during external extension mode External data address 20 bit address External data bus 16 bit data bus Shortest external...

Page 24: ...uest Failed to send transmission completed or reception completed Real Time Debugger Internal RAM can be rewritten or monitored independently of the CPU by entering a command RTD from the outside Come...

Page 25: ...HW BHE P41 BLW BLE P71 WAIT P72 HREQ P73 HACK P20 A23 P27 A30 P30 A15 P37 A22 P46 A13 P47 A14 P00 DB0 P07 DB7 P10 DB8 P17 DB15 P82 TXD0 P83 RXD0 P84 SCLKI0 SCLKO0 P85 TXD1 P86 RXD1 P87 SCLKI1 SCLKO1 P...

Page 26: ...MHz BCLK System clock Output This pin outputs a clock whose frequency is twice that of the external input clock XIN BCLK output is 20 MHz when f CPUCLK 80 MHz Use this clock to synchronize the operat...

Page 27: ...d byte position to which data is transferred BHW and BLW correspond to the upper address side bits 0 7 are valid and the lower address side bits 8 15 are valid respectively BHE Byte high enable Output...

Page 28: ...ive clock dividing it by 2 input output When channel 0 is in CSIO mode This pin accepts as input a transmit receive clock when external clock is selected or outputs a transmit receive clock when inter...

Page 29: ...input pin for serial I O channel 5 Real time RTDTXD RTD transmit data Output Serial data output pin for the real time debugger debugger RTDRXD RTD received data Input Serial data input pin for the re...

Page 30: ...t port 6 P65 P67 P70 P77 Input output port 7 P82 P87 Input output port 8 P93 P97 Input output port 9 P100 P107 Input output port 10 P110 P117 Input output port 11 P124 P127 Input output port 12 P130 P...

Page 31: ...111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 32: ...P132 TIN18 P132 TIN18 Input output P132 Input Hi z Hi z 19 P133 TIN19 P133 TIN19 Input output P133 Input Hi z Hi z 20 P134 TIN20 P134 TIN20 Input output P134 Input Hi z Hi z 21 P135 TIN21 P135 TIN21...

Page 33: ...VSS0 AVSS0 74 AD0IN8 AD0IN8 Input AD0IN8 Input Hi z Hi z 75 AD0IN9 AD0IN9 Input AD0IN9 Input Hi z Hi z 76 AD0IN10 AD0IN10 Input AD0IN10 Input Hi z Hi z 77 AD0IN11 AD0IN11 Input AD0IN11 Input Hi z Hi z...

Page 34: ...TO16 Input output P93 Input Hi z Hi z 125 VCCE VCCE VCCE 126 VSS VSS VSS 127 VCC BUS VCC BUS VCC BUS During single chip and external extension modes P27 Input Hi z Hi z During processor mode A30 Outp...

Page 35: ...chip and external extension modes P226 Input Hi z Hi z During processor mode CS2 Output Hi z High level 153 VCC BUS VCC BUS VCC BUS 154 VCCE VCCE VCCE 155 VSS VSS VSS 156 P167 TO28 P167 TO28 Input ou...

Page 36: ...14 Input Hi z Hi z During processor mode DB12 Input output Hi z Hi z During single chip and external extension modes P13 Input Hi z Hi z During processor mode DB11 Input output Hi z Hi z During single...

Page 37: ...e P41 Input Hi z Hi z During external extension and processor modes BLW BLE Output Hi z High level 221 VCC BUS VCC BUS VCC BUS 222 VSS VSS 223 AD1IN15 AD1IN15 Input AD1IN15 Input Hi z Hi z 224 AD1IN14...

Page 38: ...Registers 2 2 General purpose Registers 2 3 Control Registers 2 4 Accumulator 2 5 Program Counter 2 6 Data Formats 2 7 Supplementary Explanation for BSET BCLR LOCK and UNLOCK Instruction Execution 2...

Page 39: ...g point operations etc R14 is used as the link register and R15 as the stack pointer The link register is used to store the return address when executing a subroutine call instruction The Interrupt St...

Page 40: ...kup C Bit 24 SM 0 Uses R15 as the interrupt stack pointer R W Stack Mode Bit 1 Uses R15 as the user stack pointer 25 IE 0 Does not accept interrupt R W Interrupt Enable Bit 1 Accepts interrupt 26 30 N...

Page 41: ...ss of the current stack pointer These registers can be accessed as the general purpose register R15 R15 switches between repre senting the SPI and SPU depending on the value of the Stack Mode SM bit i...

Page 42: ...to 0 in software 6 16 No function assigned Fix to 0 0 0 17 EX 0 Mask EIT processing to be executed when an inexact exception occurs R W Inexact Exception Enable Bit 1 Execute EIT processing when an i...

Page 43: ...Bit 1 An invalid operation exception occurred When the bit is set to 1 the execution of an FPU operation instruction will clear it to 0 30 31 RM 00 Round to nearest R W Rounding Mode Selection Bit 01...

Page 44: ...ively Use the MVFACHI MVFACLO and MVFACMI instructions for reading data from the accumulator The MVFACHI MVFACLO and MVFACMI instructions read data from the high order 32 bits bits 0 31 the low order...

Page 45: ...n floating point numbers The signed integers are represented by 2 s complements Figure 2 6 1 Data Types Signed byte 8 bit integer Unsigned byte 8 bit integer Signed halfword 16 bit integer Unsigned ha...

Page 46: ...a memory the 32 bit data the 16 bit data on the LSB side and the 8 bit data on the LSB side of the register are stored into memory by the ST STH and STB instructions respectively Figure 2 6 2 Data For...

Page 47: ...a can be located at any address halfword and word data must be located at the addresses aligned with a halfword boundary least significant address bit 0 or a word boundary two low order address bits 0...

Page 48: ...Rsrc Note The condition bit C changes state when data is written to CR0 PSW using the MVTC instruction Figure 2 6 6 Transfer Instructions Little little LL LH HL HH Big big HH HL LH LL Little big HH H...

Page 49: ...00 FF FF FF b31 b0 0 1 2 3 Determined by MSB Memory Register 0 Positive number 1 Negative number 0 Positive number 1 Negative number Unsigned 32 bits LD24 Rsrc label LD Rdest Rsrc Unsigned 16 bits LD2...

Page 50: ...Word data 32 bits 0 1 2 3 b0 b31 HH HL LH LL b0 b31 HH HL LH LL Halfword data 16 bits 0 1 2 3 b0 b31 H L b0 b15 H L Byte data 8 bits 0 1 2 3 b0 b31 b0 b7 R0 R15 R0 R15 R0 R15 0 1 2 3 b0 b31 b8 b15 R0...

Page 51: ...lowing two cases When DMA transfer is requested by the internal DMAC When HREQ input is pulled low to request that the CPU be placed in a hold state 2 8 Precautions on CPU Usage Notes for 0 Division I...

Page 52: ...DDRESS SPACE 3 1 Outline of the Address Space 3 2 Operation Modes 3 3 Internal ROM and Extended External Areas 3 4 Internal RAM and SFR Areas 3 5 EIT Vector Entry 3 6 ICU Vector Table 3 7 Notes on Add...

Page 53: ...Gbytes from the address H 0000 0000 to the address H 7FFF FFFF comprise the user space Located in this space are the internal ROM area an extended external area the internal RAM area and the SFR Speci...

Page 54: ...a CS1 area CS2 area CS3 area SFR area 16 Kbytes RAM area 48 Kbytes Reserved area 64 Kbytes H 0000 0000 H 000F FFFF H 0010 0000 H 001F FFFF H 0020 0000 H 003F FFFF H 0040 0000 H 005F FFFF H 0060 0000 H...

Page 55: ...able see Section 6 5 Programming the Internal Flash Memory The internal ROM and extended external areas are located differently depending on how operation mode is set All other areas in the address sp...

Page 56: ...tings When accessing the extended external area the control signals necessary to access exter nal devices are output The CS0 through CS3 signals are output corresponding to the address mapping of the...

Page 57: ...ernal RAM Area The internal RAM area is allocated to the addresses shown below Table 3 4 1 Internal RAM Allocation Address Type Name Size Allocation Address M32180F8 48 Kbytes H 0080 4000 to H 0080 FF...

Page 58: ...1F8 H 0080 0200 H 0080 023E H 0080 0240 H 0080 02FE H 0080 0300 H 0080 03BE H 0080 03C0 H 0080 03D8 H 0080 03E0 H 0080 03FE H 0080 0400 H 0080 0478 H 0080 0700 H 0080 077F H 0080 0080 Multijunction ti...

Page 59: ...ster TOP6 7 Output Interrupt Control Register 5 8 ITIO03CR ITOP67CR H 0080 0074 TOP0 5 Output Interrupt Control Register TIO8 9 Output Interrupt Control Register 5 8 ITOP05CR ITIO89CR H 0080 0076 TIO4...

Page 60: ...2 AD08DT4 H 0080 00DA Use inhibited area 8 bit A D0 Data Register 5 11 32 AD08DT5 H 0080 00DC Use inhibited area 8 bit A D0 Data Register 6 11 32 AD08DT6 H 0080 00DE Use inhibited area 8 bit A D0 Data...

Page 61: ...0080 0144 SSIO3 Receive Buffer Register 12 19 S3RXB H 0080 0146 SIO3 Receive Control Register SIO3 Baud Rate Register 12 20 S3RCNT S3BAUR 12 23 Use inhibited area H 0080 0180 CS0 Area Wait Control Reg...

Page 62: ...r TOP0 5 Interrupt Request Mask Register 10 39 TOP05IST TOP05IMA H 0080 0232 TOP6 7 Interrupt Request Mask Status Register TOP8 9 Interrupt Request Mask Status Register 10 41 TOP67IMS TOP89IMS 10 42 H...

Page 63: ...0 0286 TOP4 Correction Register 10 77 TOP4CC Use inhibited area H 0080 0290 TOP5 Counter 10 75 TOP5CT H 0080 0292 TOP5 Reload Register 10 76 TOP5RL H 0080 0294 Use inhibited area H 0080 0296 TOP5 Corr...

Page 64: ...OP10CC H 0080 02E8 Use inhibited area H 0080 02EA TOP8 10 Control Register 10 74 TOP810CR Use inhibited area H 0080 02FA TOP External Enable Permit Register 10 78 TOPEEN H 0080 02FC TOP Enable Protect...

Page 65: ...Control Register TIO5 Control Register 10 104 TIO4CR TIO5CR 10 106 Use inhibited area H 0080 0350 TIO5 Counter 10 109 TIO5CT H 0080 0352 Use inhibited area H 0080 0354 TIO5 Reload 1 Register 10 111 T...

Page 66: ...egister 10 130 TMS0MR3 H 0080 03C4 TMS0 Measure 2 Register 10 130 TMS0MR2 H 0080 03C6 TMS0 Measure 1 Register 10 130 TMS0MR1 H 0080 03C8 TMS0 Measure 0 Register 10 130 TMS0MR0 H 0080 03CA TMS0 Control...

Page 67: ...7 DM1CNT0 DM1CNT1 H 0080 0422 DMA1 Source Address Register 9 19 DM1SA H 0080 0424 DMA1 Destination Address Register 9 20 DM1DA H 0080 0426 DMA1 Transfer Count Register 9 21 DM1TCT H 0080 0428 DMA6 Ch...

Page 68: ...tware Request Generation Register 9 18 DM3SRI H 0080 0468 DMA4 Software Request Generation Register 9 18 DM4SRI Use inhibited area H 0080 0470 DMA5 Software Request Generation Register 9 18 DM5SRI H 0...

Page 69: ...nction Control Register 8 11 P4MOD PICNT 8 21 H 0080 0746 P6 Operation Mode Register P7 Operation Mode Register 8 11 P6MOD P7MOD 8 12 H 0080 0748 P8 Operation Mode Register P9 Operation Mode Register...

Page 70: ...80 079A Lower 10 163 TOU01CT H 0080 079C TOU0_1 Reload Register TOU0_1 Reload 1 Register 10 164 TOU01RLW TOU01RL1 10 167 H 0080 079E TOU0_1 Reload 0 Register 10 166 TOU01RL0 H 0080 07A0 TOU0_2 Counter...

Page 71: ...FF0CR TIN2425CR 10 25 H 0080 07E2 TIN24 25 Interrupt Request Mask Register TIN24 25 Interrupt Request Status Register 10 53 TIN2425IMA TIN2425IST Use inhibited area H 0080 0A00 SIO45 Interrupt Request...

Page 72: ...D1 Data Register 13 11 31 AD1DT13 H 0080 0AAC 10 bit A D1 Data Register 14 11 31 AD1DT14 H 0080 0AAE 10 bit A D1 Data Register 15 11 31 AD1DT15 Use inhibited area H 0080 0AD0 Use inhibited area 8 bit...

Page 73: ...OU1_2 Reload 1 Register 10 164 TOU12RLW TOU12RL1 10 167 H 0080 0BA6 TOU1_2 Reload 0 Register 10 166 TOU12RL0 H 0080 0BA8 TOU1_3 Counter Upper 10 161 TOU13CTW TOU13CTH H 0080 0BAA Lower 10 163 TOU13CT...

Page 74: ...tus Register 10 54 TIN2627IMA TIN2627IST Use inhibited area H 0080 0C8C TID2 Counter 10 144 TID2CT H 0080 0C8E TID2 Reload Register 10 144 TID2RL H 0080 0C90 TOU2_0 Counter Upper 10 161 TOU20CTW TOU20...

Page 75: ...0 143 H 0080 0CD2 TOU2 Interrupt Request Mask Register TOU2 Interrupt Request Status Register 10 61 TOU2IMA TOU2IST H 0080 0CD4 Use inhibited area F F37 44 Protect Register 10 31 FF3744P H 0080 0CD6 U...

Page 76: ...andard ID 0 CAN0 Global Mask Register Standard ID 1 13 48 C0GMSKS0 C0GMSKS1 H 0080 102A CAN0 Global Mask Register Extended ID 0 CAN0 Global Mask Register Extended ID 1 13 49 C0GMSKE0 C0GMSKE1 H 0080 1...

Page 77: ...13 71 C0MSL0TSP H 0080 1110 CAN0 Message Slot 1 Standard ID 0 CAN0 Message Slot 1 Standard ID 1 13 57 C0MSL1SID0 C0MSL1SID1 13 58 H 0080 1112 CAN0 Message Slot 1 Extended ID 0 CAN0 Message Slot 1 Ext...

Page 78: ...er 13 61 C0MSL5EID2 C0MSL5DLC 13 62 H 0080 1156 CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 13 63 C0MSL5DT0 C0MSL5DT1 13 64 H 0080 1158 CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3...

Page 79: ...C0MSL9DT5 13 68 H 0080 119C CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 13 69 C0MSL9DT6 C0MSL9DT7 13 70 H 0080 119E CAN0 Message Slot 9 Timestamp 13 71 C0MSL9TSP H 0080 11A0 CAN0 Message Slo...

Page 80: ...Slot 13 Timestamp 13 71 C0MSL13TSP H 0080 11E0 CAN0 Message Slot 14 Standard ID 0 CAN0 Message Slot 14 Standard ID 1 13 57 C0MSL14SID0 C0MSL14SID1 13 58 H 0080 11E2 CAN0 Message Slot 14 Extended ID 0...

Page 81: ...1432 CAN1 Local Mask Register A Extended ID 0 CAN1 Local Mask Register A Extended ID 1 13 49 C1LMSKAE0 C1LMSKAE1 H 0080 1434 CAN1 Local Mask Register A Extended ID 2 Use inhibited area 13 50 C1LMSKAE2...

Page 82: ...Message Slot 1 Data 3 13 65 C1MSL1DT2 C1MSL1DT3 13 66 H 0080 151A CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 13 67 C1MSL1DT4 C1MSL1DT5 13 68 H 0080 151C CAN1 Message Slot 1 Data 6 CAN1 Mess...

Page 83: ...1MSL5TSP H 0080 1560 CAN1 Message Slot 6 Standard ID 0 CAN1 Message Slot 6 Standard ID 1 13 57 C1MSL6SID0 C1MSL6SID1 13 58 H 0080 1562 CAN1 Message Slot 6 Extended ID 0 CAN1 Message Slot 6 Extended ID...

Page 84: ...13 62 H 0080 15A6 CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 13 63 C1MSL10DT0 C1MSL10DT1 13 64 H 0080 15A8 CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 13 65 C1MSL10DT2 C1MSL10...

Page 85: ...Extended ID 0 CAN1 Message Slot 14 Extended ID 1 13 59 C1MSL14EID0 C1MSL14EID1 13 60 H 0080 15E4 CAN1 Message Slot 14 Extended ID 2 CAN1 Message Slot 14 Data Length Register 13 61 C1MSL14EID2 C1MSL14...

Page 86: ...005C H 0000 0060 H 0000 0064 H 0000 0068 H 0000 006C H 0000 0070 H 0000 0074 H 0000 0078 H 0000 007C H 0000 0080 H 0000 0090 H 0000 0030 H 0000 0020 H 0000 0010 H 0000 0000 H 0000 0034 H 0000 0038 H...

Page 87: ...0000 00AC TOP8 9 Output Interrupt Handler Start Address A0 A15 H 0000 00AE TOP8 9 Output Interrupt Handler Start Address A16 A31 H 0000 00B0 TOP10 Output Interrupt Handler Start Address A0 A15 H 0000...

Page 88: ...A15 H 0000 00F2 RTD Interrupt Handler Start Address A16 A31 H 0000 00F4 TID1 Input Interrupt Handler Start Address A0 A15 H 0000 00F6 TID1 Input Interrupt Handler Start Address A16 A31 H 0000 00F8 TO...

Page 89: ...dress H 0080 8000 into areas S banks of the internal flash memory that are divided in 4 Kbyte units This functions is referred to as the virtual flash emulation function This function allows the data...

Page 90: ...ure 4 4 EIT Processing Mechanism 4 5 Acceptance of EIT Events 4 6 Saving and Restoring the PC and PSW 4 7 EIT Vector Entry 4 8 Exception Processing 4 9 Interrupt Processing 4 10 Trap Processing 4 11 E...

Page 91: ...n FPE 2 Interrupt This is an event generated irrespective of the context being executed It is generated by a hardware derived signal from an external source as well as by the internal peripheral I O T...

Page 92: ...Destination Register When the OVF EIT processing is masked Note 1 When the OVF EIT processing is executed Note 2 MAX Infinity Infinity MAX MAX MAX Infinity Infinity No change Sign of the Result Infin...

Page 93: ...tion IXCT The exception occurs when the operation result differs from a result led out with an infinite range of precision The following table shows the operation results and the respective conditions...

Page 94: ...A UDF occurs when the intermediate result of an operation is a denormalized number in which case if the DN bit FPSR register bit 23 0 an UIPL occurs 4 2 2 Interrupt 1 Reset Interrupt RI Reset Interru...

Page 95: ...egister must be saved to the stack as necessary Remember that all these registers must be saved to the stack in a program by the user When processing by the EIT handler is completed restore the saved...

Page 96: ...the backup registers for the PC and PSW the BPC register and the BPSW field of the PSW register The EIT processing mechanism is shown below 4 4 EIT Processing Mechanism Figure 4 4 1 EIT Processing Mec...

Page 97: ...ndary only External Interrupt EI Instruction processing Break in instructions PC value of the next instruction completed type word boundary only Trap TRAP Instruction processing Break in instructions...

Page 98: ...the PC PC Vector address B Restoring the PC from the BPC register The value stored in the BPC register after executing the RTE instruction is undefined A Restoring the SM IE and C bits from the backup...

Page 99: ...RAP instruction 4 TRAP6 H 0000 0058 Unchanged 0 PC of TRAP instruction 4 TRAP7 H 0000 005C Unchanged 0 PC of TRAP instruction 4 TRAP8 H 0000 0060 Unchanged 0 PC of TRAP instruction 4 TRAP9 H 0000 0064...

Page 100: ...he PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC register For example if the instruction that generated the reserved instruction exception is a...

Page 101: ...isaligned address in Load or Store instructions The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur Two low order address bits accesse...

Page 102: ...nstruction including the instruction that generated an AE see Figure 4 8 2 Except when using address exceptions intentionally occurrence of an address exception suggests that the system has some fatal...

Page 103: ...ion performed in hardware preprocessing 5 Jumping from the EIT vector entry to the user created handler The CPU executes the BRA instruction written by the user at the address H 0000 0090 of the EIT v...

Page 104: ...e jumping to the start address of the user program 4 9 2 System Break Interrupt SBI System Break Interrupt SBI is an emergency interrupt which is used when power outage is detected or a fault conditio...

Page 105: ...ndary following one in which the interrupt was detected is stored in the BPC register If the interrupt was detected in a branch instruction then the next instruction is one that exists at the jump add...

Page 106: ...mulator and FPSR register as necessary 4 9 3 External Interrupt EI An external interrupt is generated upon an interrupt request which is output by the microcomputer s internal interrupt controller The...

Page 107: ...C bits are updated as shown below SM Unchanged IE 0 C 0 3 Saving the PC When the trap instruction is executed the PC value of TRAP instruction 4 is set in the BPC register For example if the TRAP inst...

Page 108: ...nerates a trap see Figure 4 10 1 4 11 EIT Priority Levels The table below lists the priority levels of EIT events When two or more EITs occur simultaneously the event with the highest priority is acce...

Page 109: ...Processing of Events When RIE AE FPE or TRAP and EI Occur Simultaneously RTE instruction IE 0 RIE AE FPE or TRAP is accepted first BPC register Return address A IE 1 RIE AE FPE or TRAP and EI occur si...

Page 110: ...ose registers to the stack Processing by EIT handler Restore general purpose registers from the stack Restore PSW from the stack Restore BPC from the stack EIT event occurs SBI System Break Interrupt...

Page 111: ...2 become undefined these instructions behave the same way as when used in other addressing modes Applicable instructions LD Rdest Rsrc ST Rsrc1 Rsrc2 ST Rsrc1 Rsrc2 If the above case applies consider...

Page 112: ...1 Outline of the Interrupt Controller 5 2 ICU Related Registers 5 3 Interrupt Request Sources in Internal Peripheral I O 5 4 ICU Vector Table 5 5 Description of Interrupt Operation 5 6 Description of...

Page 113: ...nsition occurs on the SBI signal input pin This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer so that it...

Page 114: ...ller Interrupt Control Register SBI Control Register SBICR SBIREQ IREQ IREQ IREQ IREQ IREQ IREQ Peripheral circuits Edge Interrupt control circuit Edge Edge Level Interrupt request Interrupt request I...

Page 115: ...IDMA59CR H 0080 006A TOU0 Output Interrupt Control Register TID0 Output Interrupt Control Register 5 8 ITOU0CR ITID0CR H 0080 006C A D0 Conversion Interrupt Control Register SIO0 Transmit Interrupt C...

Page 116: ...IVECT register using the LDH instruction to get the ICU vector table address When the IVECT register is read operations 1 to 4 below are automatically performed in hardware 1 The interrupt priority l...

Page 117: ...ther or not to accept an interrupt request after comparing its priority with the priority levels Interrupt Control Register ILEVEL bits that have been set for each interrupt request source When the In...

Page 118: ...1 SBI requested Note 1 This bit can only be cleared see below The System Break Interrupt SBI is an interrupt request generated by a falling edge on the SBI signal input pin When a falling edge on the...

Page 119: ...Address H 0080 006D SIO0 Receive Interrupt Control Register ISIO0RXCR Address H 0080 006E SIO1 Transmit Interrupt Control Register ISIO1TXCR Address H 0080 006F SIO1 Receive Interrupt Control Registe...

Page 120: ...equest bit Bit 3 or 11 When an interrupt request from some internal peripheral I O occurs the corresponding IREQ Interrupt Re quest bit is set to 1 This bit can be set and cleared in software for only...

Page 121: ...ship between ILEVEL settings and the IMASK values at which interrupts are accepted Table 5 2 1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted...

Page 122: ...uest SIO0 transmission completed or transmit buffer empty 1 Edge recognized interrupt A D0 conversion interrupt request A D0 converter s scan mode one shot operation 1 Edge recognized single mode or c...

Page 123: ...0 00BF TOP6 7 output interrupt request H 0000 00C0 H 0000 00C3 TIO0 3 output interrupt request H 0000 00C4 H 0000 00C7 DMA0 4 interrupt request H 0000 00C8 H 0000 00CB SIO1 receive interrupt request H...

Page 124: ...priority levels set in each Interrupt Control Register s ILEVEL bit to select an interrupt request that has the highest priority If the interrupt requests have the same ILEVEL value their priorities...

Page 125: ...pt request H 0000 00D4 H 0000 00D7 Edge recognized SIO0 transmit interrupt request H 0000 00D8 H 0000 00D8 Edge recognized A D0 conversion interrupt request H 0000 00DC H 0000 00DF Edge recognized TID...

Page 126: ...ority levels than that of the accepted interrupt request source are masked The accepted interrupt request source is cleared not cleared for level recognized interrupt request sources The interrupt req...

Page 127: ...ng the source of the interrupt request generated If any internal peripheral I O has two or more interrupt request sources check the Interrupt Request Status Register provided for each internal periphe...

Page 128: ...errupts by setting the IE bit to 1 after writing to the Interrupt Request Mask Register IMASK perform a dummy access to the internal memory etc before reenabling interrupts H 0000 0080 BRA instruction...

Page 129: ...gister IE bit is set and cannot be masked 5 6 2 SBI Processing by Handler When the system break interrupt generated has been serviced shut down or reset the system without returning to the program tha...

Page 130: ...sh Memory 6 4 Registers Associated with the Internal Flash Memory 6 5 Programming the Internal Flash Memory 6 6 Virtual Flash Emulation Function 6 7 Connecting to A Serial Programmer 6 8 Internal Flas...

Page 131: ...Debugger Notes Immediately after power on reset for the power on case in which VDDE also goes up from GND the value of the RAM is undefined If the RAM is reset during RAM backup power for only VDDE is...

Page 132: ...0000 H 000F 0000 H 000F FFFF 16KB 8KB 8KB 32KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Block...

Page 133: ...er 1 6 11 FESBANK1 H 0080 01EC Virtual Flash S Bank Register 2 6 11 FESBANK2 H 0080 01EE Virtual Flash S Bank Register 3 6 11 FESBANK3 H 0080 01F0 Virtual Flash S Bank Register 4 6 11 FESBANK4 H 0080...

Page 134: ...peration performed on the internal flash memory When FSTAT 0 busy the internal flash memory is being programmed or erased during which time do not start a new programming or erase operation on it When...

Page 135: ...in an error When ERASE 0 it means that the erase operation termi nated normally when ERASE 1 the erase operation terminated in an error 3 WRERR1 Write status 1 bit Bit 11 The WRERR1 bit is used to det...

Page 136: ...the FENTRY bit Note that the following operations cannot be performed while programming or erasing the internal flash memory FSTAT1 register FSTAT bit 0 busy If one of these operations is attempted th...

Page 137: ...rotection by lock bit invalidated Flash Control Register 2 FCNT2 controls invalidation of the internal flash memory protection by a lock bit protection against programming erase operation Protection o...

Page 138: ...12 13 14 b15 b8 FRESET 0 0 0 0 0 0 0 0 After reset H 00 b Bit Name Function R W 8 14 No function assigned Fix to 0 0 0 15 FRESET 0 No operation R W Flash reset bit 1 Reset Flash Control Register 4 FCN...

Page 139: ...T 0 Program erase the flash memory FENTRY 0 At this point in time the FSTAT1 register FSTAT bit 1 ready Programming erase operation terminated normally 6 4 Registers Associated with the Internal Flash...

Page 140: ...irtual flash emulation function R W Virtual flash emulation enable bit 1 Enable virtual flash emulation function 1 7 No function assigned Fix to 0 0 0 8 SBANKAD Start address A12 A19 of the relevant S...

Page 141: ...t program to set the Flash Control Register 1 FCNT1 FENTRY bit to 1 to make the internal flash memory ready for programming erase operation i e placed in boot mode flash E W enable mode When the above...

Page 142: ...n high MOD0 pin high and MOD1 pin low to place the flash memory in boot mode flash E W enable mode Dessert reset signal and start up with the boot program Transfer the flash write erase program into t...

Page 143: ...selected Reset signal deasserted Boot program starts Mode selected Reset signal deasserted Flash programming erasing by the boot program Settings by the boot program Figure 6 5 3 Internal Flash Memory...

Page 144: ...PU RAM Flash write erase program FP L or H Write data RAM RAM Step 1 Initial state Flash write erase program existing in the internal flash memory An ordinary program in the internal flash memory is b...

Page 145: ...MOD1 pin Low High or low Flash programming erasing by the flash write erase program Flash rewrite starts Flash mode turned on Flash mode turned off Flash write erase program transferred into the RAM...

Page 146: ...H 0080 4000 1 0 1 1 External extension Start address of internal Beginning of internal RAM mode flash E W flash memory H 0080 4000 enable H 0000 0000 1 1 Use inhibited Note 1 Indicates the Flash Cont...

Page 147: ...n high 2 P82DT At read R W Port P82 data bit Depends on how the Port Direction Register is set 3 P83DT If direction bit 0 input mode Port P83 data bit 0 Port input pin low 4 P84DT 1 Port input pin hig...

Page 148: ...l Register in SFR area FCNT1 H 0080 01E2 FENTRY bit to 1 Execute flash write erase command and various read commands Note 1 Switched to the flash write erase program Wait for 1 s using a hardware or s...

Page 149: ...ommand H 7777 Block Erase command H 2020 Erase All Unlocked Blocks command H A7A7 Read Status Register command H 7070 Clear Status Register command H 5050 Read Lock Bit Status command H 7171 Verify co...

Page 150: ...tomatically readied to run the Read Status command so that there is no need to enter the Read Status command until another command is entered Note 3 Inspect the Flash Status Register 2 ERASE erase sta...

Page 151: ...6 4 3 Flash Control Registers and erase the flash memory block whose protection is to be removed The content of that memory block is also erased Executing a programming erase operation on flash memor...

Page 152: ...it Program Note 1 Wait for 1 s using a hardware or software timer FSTAT bit 1 TIME OUT 0 5s YES NO Forcibly terminated see Figure 6 4 3 YES NO Note 1 When a programming operation started the internal...

Page 153: ...ter 2 ERASE erase status WRERR1 write status 1 and WRERR2 write status 2 bits to check for programming error Figure 6 5 10 Block Erase Command 6 5 Programming the Internal Flash Memory 4 Block Erase c...

Page 154: ...e the Verify command H D0D0 to any address of the internal flash memory Write the Erase All Unlocked Blocks command H A7A7 to any address of the internal flash memory Flash memory contents are erased...

Page 155: ...programming or erasing the internal flash memory and the Flash Status Register 2 ERASE erase status WRERR1 write status 1 or WRERR2 write status 2 bit is set to 1 the next programming or erase operat...

Page 156: ...ther a flash memory block is protected against programming erase operation Write the Read Lock Bit Status command H 7171 to any address of the internal flash memory Next read the last even address of...

Page 157: ...of one another The following shows how the lock bits in this register are set a Setting the lock bit to 0 protected Issue the Lock Bit Program command H 7777 to the memory block to be protected b Sett...

Page 158: ...s 3 Time required for erasing the entire area 50 ms 19 blocks approx 950 ms 4 Total flash programming time entire 1 024 KB area When communicating at 57 600 bps via UART the flash programming time ca...

Page 159: ...RAM blocks allocated for virtual flash emulation can be accessed for read and write the same way as in usual RAM This function when used in combination with the microcomputer s internal Real Time Deb...

Page 160: ...SBANK7 and each register s flash emulation enable bit MODENS is set to 1 enabled the bank is assigned the corresponding internal RAM area 4 Kbyte according to the priority of Virtual Flash S Bank Regi...

Page 161: ...SBANK5 FESBANK6 FESBANK7 If any 4 Kbyte area S bank specified by the Virtual Flash S Bank Register is accessed its corresponding internal RAM area is accessed During virtual flash emulation mode RAM c...

Page 162: ...nable the Virtual Flash Emulation Function Even during virtual flash emulation mode the internal RAM area H 0080 8000 through H 0080 FFFF can be accessed the same way as in usual internal RAM Set RAM...

Page 163: ...tion Mode 1 2 Replace area Flash memory RAM block 0 Data write to RAM0 RAM block 1 1 Operation when reset Replaced Data write to RAM1 2 Programming operation using RAM block 0 Flash memory Initial val...

Page 164: ...ced 5 Programming operation switched from RAM block 1 to RAM block 0 RAM block 0 Flash memory Initial value RAM block 0 RAM block 1 RAM block 1 Bank xx Bank xx specified Bank xx specified settings inv...

Page 165: ...eration mode 0 Connect to the main power supply MOD1 189 Operation mode 1 Connect to ground RESET 35 Reset After setting MOD0 MOD1 ground and back to main power supply JTRST 50 JTAG reset Pull low via...

Page 166: ...D1 P85 TXD1 VCC BUS EXCVDD EXCVCC VREF0 VREF1 AVCC0 AVCC1 OSC VCC VDDE VCCE Connect to the user system power supply rail Connect to the VCCE 5 or 3 3 V power supply rail Main power supply Connect to t...

Page 167: ...is protected in hardware against programming erase operation by pulling the FP Flash Protect pin low Furthermore because the FP pin level can be known by reading the Flash Mode Regis ter FMOD s FPMOD...

Page 168: ...mory needs to be protected while using a general purpose programming erase tool set any ID in the flash memory protect ID verification area H 0000 0084 to H 0000 008F If the internal flash memory does...

Page 169: ...6 6 40 INTERNAL MEMORY 32180 Group User s Manual Rev 1 0 6 9 Precautions To Be Taken when Rewriting the Internal Flash Memory This page is blank for reasons of layout...

Page 170: ...CHAPTER 7 RESET 7 1 Outline of Reset 7 2 Reset Operation 7 3 Internal State Immediately after Reset 7 4 Things to Be Considered after Reset...

Page 171: ...cuits including the CPU are reset 9 10 BCLK periods later When the RESET input is returned high the microcomputer pins get out of a reset state and the internal bus hold request is deasserted 17 18 BC...

Page 172: ...nal bus hold request is output internally after accepting the reset input Then the internal circuits are reset after the internal bus is placed in a hold state Note Reset input at entering RAM backup...

Page 173: ...R2 Undefined SPU CR3 Undefined BPC CR6 Undefined FPSR CR7 H 0000 0100 Only DN bit 1 PC H 0000 0000 Executed beginning with the address H 0000 0000 Note 1 R0 R15 Undefined ACC accumulator Undefined RAM...

Page 174: ...AND PIN FUNCTIONS 8 1 Outline of Input Output Ports 8 2 Selecting Pin Functions 8 3 Input Output Port Related Registers 8 4 Port Input Level Switching Function 8 5 Port Peripheral Circuits 8 6 Precau...

Page 175: ...8 ports P1 P10 P17 8 ports P2 P20 P27 8 ports P3 P30 P37 8 ports P4 P41 P47 7 ports P6 P61 P63 P65 P67 6 ports P7 P70 P77 8 ports P8 P82 P87 6 ports P9 P93 P97 5 ports P10 P100 P107 8 ports P11 P110...

Page 176: ...1 CPU Operation Modes and P0 P4 and P224 P227 Pin Functions MOD0 MOD1 Operation Mode P0 P4 and P224 P227 Pin Function VSS VSS Single chip mode Input output port pin VSS VCCE External extension mode In...

Page 177: ...39 TO40 TO41 TO42 TO43 TO44 TIN8 TIN9 TIN10 TIN11 TIN12 TIN13 TIN14 TIN15 TIN24 TIN25 TXD2 RXD2 TXD3 RXD3 MOD0 MOD1 SCLKI0 SCLKI1 TXD0 RXD0 TXD1 RXD1 Note 3 Note 3 SCLKO0 SCLKO1 BLW BHW RD CS0 CS1 A13...

Page 178: ...H 0080 0710 P16 Data Register P17 Data Register 8 7 P16DATA P17DATA H 0080 0712 P18 Data Register P19 Data Register 8 7 P18DATA P19DATA H 0080 0714 P20 Data Register P21 Data Register 8 7 P20DATA P21...

Page 179: ...P14 Operation Mode Register P15 Operation Mode Register 8 15 P14MOD P15MOD 8 16 H 0080 0750 P16 Operation Mode Register P17 Operation Mode Register 8 16 P16MOD P17MOD 8 17 H 0080 0752 P18 Operation Mo...

Page 180: ...3 4 5 6 b7 b0 Pn0DT Pn1DT Pn2DT Pn3DT Pn4DT Pn5DT Pn6DT Pn7DT n 0 22 not including P5 After reset Undefined b Bit Name Function R W 0 b8 Pn0DT At read R W Port Pn0 data bit Depends on how the Port Di...

Page 181: ...dress H 0080 0730 P17 Direction Register P17DIR Address H 0080 0731 P18 Direction Register P18DIR Address H 0080 0732 P19 Direction Register P19DIR Address H 0080 0733 P20 Direction Register P20DIR Ad...

Page 182: ...rt P07 operation mode bit 1 DB7 Note P0 Operation Mode Register is useful only when the CPU operates in external extension mode P1 Operation Mode Register P1MOD Address H 0080 0741 9 10 11 12 13 14 b1...

Page 183: ...n mode bit 1 A30 Note P2 Operation Mode Register is useful only when the CPU operates in external extension mode P3 Operation Mode Register P3MOD Address H 0080 0743 9 10 11 12 13 14 b15 b8 P30MD P31M...

Page 184: ...14 Note P4 Operation Mode Register is useful only when the CPU operates in external extension mode P6 Operation Mode Register P6MOD Address H 0080 0746 1 2 3 4 5 6 b7 b0 P65MD P66MD 0 0 0 0 0 0 0 0 Af...

Page 185: ...5 operation mode bit 1 RTDRXD 14 P76MD 0 P76 R W Port P76 operation mode bit 1 RTDACK 15 P77MD 0 P77 R W Port P77 operation mode bit 1 RTDCLK P8 Operation Mode Register P8MOD Address H 0080 0748 1 2 3...

Page 186: ...nt P10 Operation Mode Register P10MOD Address H 0080 074A 1 2 3 4 5 6 b7 b0 P103MD P102MD P101MD P100MD P104MD P105MD P106MD P107MD 0 0 0 0 0 0 0 0 After reset H 00 b Bit Name Function R W 0 P100MD 0...

Page 187: ...R W Port P114 operation mode bit 1 TO4 13 P115MD 0 P115 R W Port P115 operation mode bit 1 TO5 14 P116MD 0 P116 R W Port P116 operation mode bit 1 TO6 15 P117MD 0 P117 R W Port P117 operation mode bi...

Page 188: ...1 14 P136MD 0 P136 R W Port P136 operation mode bit 1 TIN22 15 P137MD 0 P137 R W Port P137 operation mode bit 1 TIN23 Note 1 TIN and PWMOFF inputs both are enabled P14 Operation Mode Register P14MOD A...

Page 189: ...bit 1 TIN5 14 P156MD 0 P156 R W Port P156 operation mode bit 1 TIN6 15 P157MD 0 P157 R W Port P157 operation mode bit 1 TIN7 P16 Operation Mode Register P16MOD Address H 0080 0750 1 2 3 4 5 6 b7 b0 P1...

Page 190: ...TXD3 15 P177MD 0 P177 R W Port P177 operation mode bit 1 RXD3 Note Ports P170 and P171 are nonexistent P18 Operation Mode Register P18MOD Address H 0080 0752 1 2 3 4 5 6 b7 b0 P184MD P185MD P186MD P18...

Page 191: ...bit 1 TIN30 13 P195MD 0 P195 R W Port P195 operation mode bit 1 TIN31 14 P196MD 0 P196 R W Port P196 operation mode bit 1 TIN32 15 P197MD 0 P197 R W Port P197 operation mode bit 1 TIN33 PWMOFF2 Note...

Page 192: ...4 P22 Operation Mode Register P22MOD Address H 0080 0756 1 2 3 4 5 6 b7 b0 P220MD P222MD P223MD P224MD P225MD P226MD P227MD 0 0 0 0 0 0 0 0 After reset H 00 b Bit Name Function R W 0 P220MD 0 P220 R W...

Page 193: ...0 1 P101SMD 0 TO9 R W Port P101 peripheral output select mode bit 1 TXD3 2 P102SMD 0 TO10 R W Port P102 peripheral output select mode bit 1 CTX1 3 7 No function assigned Fix to 0 0 0 P22 Peripheral Ou...

Page 194: ...scillation has stopped When XIN remains at the same level for a predetermined time 3 BCLK periods up to 4 BCLK periods XIN oscillation is assumed to have stopped When operating normally XIN changes st...

Page 195: ...it before inspecting XSTAT Figure 8 3 1 Procedure for Setting XSTAT 2 PISEL Port input data select bit Bit 14 When the Port Direction Register is set for output this bit selects the target data to be...

Page 196: ...ons are enabled for input and can therefore be protected against current flowing in from the pins other than serial I O functions during flash programming by clearing PIEN0 The table below lists the p...

Page 197: ...202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 120 119 118 117 116 115 114 113 112 111 110...

Page 198: ...Input Level Setting Register PG8LEV Address H 0080 0764 1 2 3 4 5 6 b7 b0 WF8SEL PT8SEL VT8SEL0 VT8SEL1 0 0 0 1 0 0 0 0 Note The PG8LEV register bits 4 7 have no functions assigned After reset B 0001...

Page 199: ...re 8 4 2 Port Level Switching Function 8 4 Port Input Level Switching Function VT VT Schmitt Peripheral function input Port input Pin 0 7VCCE 0 5VCCE 0 35VCCE CMOS S S S S S WFnSEL PTnSEL VTnSELL Thre...

Page 200: ...P20 P27 A23 A30 P30 P37 A15 A22 P46 P47 A13 A14 P71 WAIT P73 HACK P74 RTDTXD P76 RTDACK P224 A11 CS2 P225 A12 CS3 Note 1 Data bus Operation mode register Input function enable Peripheral function inpu...

Page 201: ...2 TO10 CTX1 Data bus Peripheral function input 1 Port level switching function Standard peripheral Schmitt P130 TIN16 PWMOFF0 P131 TIN17 PWMOFF1 P197 TIN33 PWMOFF2 Note 1 Peripheral function input 2 N...

Page 202: ...t output latch Direction register Input data select bit Port level switching function No peripheral input Note 1 PWM output disable Note 1 For details about the port level switching function see Secti...

Page 203: ...0 MOD1 FP JTDI JTCK JTMS JTDO RESET XIN JTRST Output control SBI P221 CRX0 Data bus DB0 DB15 SBI CRX0 Notes The circle denotes a pin The symbol denotes a parasitic diode Make sure the voltage applied...

Page 204: ...ts an undefined value until any data is written into it About the port input disable function Because the input output ports are disabled against input after reset they must be enabled for input by se...

Page 205: ...8 8 32 INPUT OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User s Manual Rev 1 0 This page is blank for reasons of layout 8 6 Precautions on Input Output Ports...

Page 206: ...CHAPTER 9 DMAC 9 1 Outline of the DMAC 9 2 DMAC Related Registers 9 3 Functional Description of the DMAC 9 4 Precautions about the DMAC...

Page 207: ...n be selected for the source and destination Address fixed Address incremental Ring buffered Channel priority DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 Priority is fixed Maximum transfer rate...

Page 208: ...ion completed TIO8_udf Software start TIN13S Software start TIN18S Software start SIO0_TXD SIO1_RXD Software start SIO0_RXD Software start Software start DMA0 4 interrupt DMA5 9 interrupt SIO2_RXD SIO...

Page 209: ...ess Register 9 20 DM5DA H 0080 041E DMA5 Transfer Count Register 9 21 DM5TCT H 0080 0420 DMA1 Channel Control Register 0 DMA1 Channel Control Register 1 9 7 DM1CNT0 DM1CNT1 H 0080 0422 DMA1 Source Add...

Page 210: ...A4 Destination Address Register 9 20 DM4DA H 0080 0456 DMA4 Transfer Count Register 9 21 DM4TCT H 0080 0458 DMA9 Channel Control Register 0 DMA9 Channel Control Register 1 9 15 DM9CNT0 DM9CNT1 H 0080...

Page 211: ...6 bits R W DMA0 transfer size select bit 1 8 bits 6 SADSL0 0 Fixed R W DMA0 source address direction select bit 1 Increment 7 DADSL0 0 Fixed R W DMA0 destination address direction select bit 1 Increme...

Page 212: ...W DMA1 transfer size select bit 1 8 bits 6 SADSL1 0 Fixed R W DMA1 source address direction select bit 1 Increment 7 DADSL1 0 Fixed R W DMA1 destination address direction select bit 1 Increment Note 1...

Page 213: ...t 1 8 bits 6 SADSL2 0 Fixed R W DMA2 source address direction select bit 1 Increment 7 DADSL2 0 Fixed R W DMA2 destination address direction select bit 1 Increment Note 1 Only writing 0 is effective W...

Page 214: ...bit 1 8 bits 6 SADSL3 0 Fixed R W DMA3 source address direction select bit 1 Increment 7 DADSL3 0 Fixed R W DMA3 destination address direction select bit 1 Increment Note 1 Only writing 0 is effectiv...

Page 215: ...ct bit 1 8 bits 6 SADSL4 0 Fixed R W DMA4 source address direction select bit 1 Increment 7 DADSL4 0 Fixed R W DMA4 destination address direction select bit 1 Increment Note 1 Only writing 0 is effect...

Page 216: ...DMA5 transfer size select bit 1 8 bits 6 SADSL5 0 Fixed R W DMA5 source address direction select bit 1 Increment 7 DADSL5 0 Fixed R W DMA5 destination address direction select bit 1 Increment Note 1...

Page 217: ...select bit 1 8 bits 6 SADSL6 0 Fixed R W DMA6 source address direction select bit 1 Increment 7 DADSL6 0 Fixed R W DMA6 destination address direction select bit 1 Increment Note 1 Only writing 0 is ef...

Page 218: ...1 8 bits 6 SADSL7 0 Fixed R W DMA7 source address direction select bit 1 Increment 7 DADSL7 0 Fixed R W DMA7 destination address direction select bit 1 Increment Note 1 Only writing 0 is effective Wri...

Page 219: ...t bit 1 8 bits 6 SADSL8 0 Fixed R W DMA8 source address direction select bit 1 Increment 7 DADSL8 0 Fixed R W DMA8 destination address direction select bit 1 Increment Note 1 Only writing 0 is effecti...

Page 220: ...it 1 8 bits 6 SADSL9 0 Fixed R W DMA9 source address direction select bit 1 Increment 7 DADSL9 0 Fixed R W DMA9 destination address direction select bit 1 Increment Note 1 Only writing 0 is effective...

Page 221: ...next DMA transfer request is not accepted until the transfer being performed on that channel is completed 3 REQSLn DMAn Transfer Request Source Select bits Bits 2 3 These bits select the cause or sou...

Page 222: ...Group User s Manual Rev 1 0 9 2 DMAC Related Registers Extended DMA transfer request source selected DMAn transfer request source S S DMAn Figure 9 2 1 Block Diagram of Extended DMAn Transfer Request...

Page 223: ...oftware Request Generation Register DM9SRI Address H 0080 0478 b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 DM0SRI DM9SRI After reset Undefined b Bit Name Function R W 0 15 DM0SRI DM9SRI DMA transfer reque...

Page 224: ...t 0 and bit 5 correspond to A16 and A31 respectively Because this register is comprised of a current register the values read from this register are always the current value When DMA transfer finishes...

Page 225: ...ch a way that bit 0 and bit 15 correspond to A16 and A31 respectively Because this register is comprised of a current register the values read from this register are always the current value When DMA...

Page 226: ...in this register has no effect during ring buffer mode The transfer count is the value set in the transfer count register 1 Because the DMA Transfer Count Register is comprised of a current register...

Page 227: ...an be used to inspect the operating status of peripheral functions In interrupt handling make sure that within the grouped interrupt request status only the status bit for the interrupt request that h...

Page 228: ...r the Interrupt Request Status Register 0 ISTREG interrupt request status 1 ISTAT1 0x02 bit To clear an interrupt request status always be sure to write 1 to all other interrupt request status bits At...

Page 229: ...request status bit 1 Interrupt requested 5 DMITST7 DMA7 interrupt request status bit 6 DMITST6 DMA6 interrupt request status bit 7 DMITST5 DMA5 interrupt request status bit Note 1 Only writing 0 is e...

Page 230: ...H 0080 0409 9 10 11 12 13 14 b15 b8 DMITMK9 DMITMK8 DMITMK6 DMITMK5 DMITMK7 0 0 0 0 0 0 0 0 After reset H 00 b Bit Name Function R W 8 10 No function assigned Fix to 0 0 0 11 DMITMK9 DMA9 interrupt r...

Page 231: ...puts DM59ITST H 0080 0408 DM59ITMK H 0080 0409 Figure 9 2 5 Block Diagram of DMA Transfer Interrupt Request 1 F F F F DMITMK0 DMITST0 F F F F DMITMK1 DMITST1 F F F F DMITMK2 DMITST2 F F F F DMITMK3 DM...

Page 232: ...n to the DMA0 Software Request Generation Register transfer completed software start or when one DMA2 transfer is completed cascade mode 0 1 A D0 conversion completed When A D0 conversion is completed...

Page 233: ...enerated 1001 MJT TIO8_udf When MJT TIO8 underflow occurs 1010 Settings inhibited 1111 Table 9 3 3 DMA Transfer Request Sources and Generation Timings on DMA2 REQSL2 DMA Transfer Request Source DMA Tr...

Page 234: ...JT TIN0 input signal is generated 1001 MJT TIO8_udf When MJT TIO8 underflow occurs 1010 Settings inhibited 1111 Table 9 3 5 DMA Transfer Request Sources and Generation Timings on DMA4 REQSL4 DMA Trans...

Page 235: ...T TIN0 input signal When MJT TIN0 input signal is generated 1001 MJT TIO8_udf When MJT TIO8 underflow occurs 1010 Settings inhibited 1111 Table 9 3 7 DMA Transfer Request Sources and Generation Timing...

Page 236: ...1000 MJT TIN0 input signal When MJT TIN0 input signal is generated 1001 MJT TIO8_udf When MJT TIO8 underflow occurs 1010 Settings inhibited 1111 Table 9 3 9 DMA Transfer Request Sources and Generatio...

Page 237: ...Request Source DMA Transfer Request Generation Timing 0000 One DMA8 transfer completed When one DMA8 transfer is completed cascade mode 0001 MJT TOU0_7irq MJT TOU0_7 interrupt source 0010 A D0 convers...

Page 238: ...ers disabled Interrupt request status bits cleared Set DMA0 4 Interrupt Request Mask Register Source address of transfer Destination address of transfer Number of times DMA transfer is performed Trans...

Page 239: ...the internal peripheral clock 20 MHz at the shortest Or depending on the preceding or following bus usage condition up to five cycles 250 ns when the internal peripheral clock 20 MHz may be required...

Page 240: ...data is taken into the DMAC s internal temporary register before being transferred 2 Bus protocol and bus timing Because the bus interface is shared with the CPU DMA transfer is performed with the sam...

Page 241: ...ycles to the start address if the destination address has been set to be incremented it is the destination address that recycles to the start address If both source and destination addresses have been...

Page 242: ...d even when transfer in ring buffer mode is terminated by clearing the transfer enable bit 9 3 11 Each Register Status after Completion of DMA Transfer When DMA transfer is completed the status of the...

Page 243: ...tten to it is ignored 3 Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer Although this operation means accessing the DMAC related registers while DMA is ena...

Page 244: ...10 2 Common Units of Multijunction Timers 10 3 TOP Output Related 16 Bit Timer 10 4 TIO Input Output Related 16 Bit Timer 10 5 TMS Input Related 16 Bit Timer 10 6 TML Input Related 32 Bit Timer 10 7...

Page 245: ...e shot output mode Without correction function Continuous output mode TIO Input output related 10 One of three input modes or four output modes can be selected Timer 16 bit timer by software Input dow...

Page 246: ...IN6 input TIN3 6 input interrupt 4 IRQ13 TOU0_0 TOU0_7 output TOU0 output interrupt 8 IRQ14 TID0 output TID0 output interrupt 1 IRQ15 TID1 output TID1 output interrupt 1 IRQ16 TOU1_0 TOU1_7 output TOU...

Page 247: ...on transfer request source see Table 10 1 4 Table 10 1 4 DMA Transfer Request Generation by MJT Common Corresponding DMAC Channel No DMA Transfer Request Source DMAn Input event bus 1 Input event bus...

Page 248: ...P 2 clk en udf TOP 3 clk en udf TOP 4 clk en udf TOP 5 clk en udf TOP 6 clk en udf TOP 7 clk en udf TOP 8 clk en udf TOP 9 clk en udf TOP 10 clk en udf TIO 0 clk en cap udf TIO 1 clk en cap udf TIO 2...

Page 249: ...verter AD0TRG To A D1 converter AD1TRG IRQ18 IRQ18 IRQ18 IRQ18 AD0TRG to A D0 converter AD1TRG to A D1 converter AD0TRG to A D0 converter AD1TRG to A D1 converter AD0TRG to A D0 converter IRQ7 IRQ7 TM...

Page 250: ...f TOU0_1 24 bit clk en udf TOU0_2 24 bit clk en udf TOU0_3 24 bit clk en udf TOU0_4 24 bit clk en udf TOU0_5 24 bit clk en udf TOU0_6 24 bit clk en udf TOU0_7 24 bit clk en udf TID 0 clk CLK1 CLK2 ovf...

Page 251: ...ID1_udf ovf AD0 conversion completed TIO8_udf Software start TIN13S Software start TIN18S Software start SIO0_TXD SIO1_RXD Software start SIO0_RXD Software start Software start DMA0 4 interrupt DMA5 9...

Page 252: ...32180 Group User s Manual Rev 1 0 10 2 Common Units of Multijunction Timers The common units of MJT include the following Prescaler Unit Clock Bus and Input Output Event Bus Control Unit Input Proces...

Page 253: ...FF1620P H 0080 022A Use inhibited area F F16 20 Data Register 10 32 FF1620D Use inhibited area H 0080 0230 TOP0 5 Interrupt Request Status Register TOP0 5 Interrupt Request Mask Register 10 39 TOP05IS...

Page 254: ...H 0080 0BD6 Use inhibited area F F29 36 Data Register 10 33 FF2936D H 0080 0BE0 PWMOFF1 Input Processing Control Register TIN26 27 Input Processing Control Register 10 171 PWMOFF1CR TIN2627CR 10 25 H...

Page 255: ...escaler Register 1 PRS1 Address H 0080 0203 Prescaler Register 2 PRS2 Address H 0080 0204 Prescaler Register 3 PRS3 Address H 0080 07D0 Prescaler Register 4 PRS4 Address H 0080 0BD0 Prescaler Register...

Page 256: ...Signal Note 1 3 TIN3 input output event bus 2 or TIO7 underflow signal 2 TIN0 input TIN2 input or TIN4 input 1 TIO6 underflow signal 0 TIO5 underflow signal Note 1 For the destination output to which...

Page 257: ...he counter underflows PWM output mode When the counter underflows Single shot output mode When the counter underflows Delayed single shot output mode When the counter underflows Continuous output mode...

Page 258: ...TCLK0S 3 2 1 0 TCLK0 P124 TIN0 P150 TIN2 P152 TIN3 P153 TIN4 P154 TIN5 P155 TIN6 P156 PRS1 PRS0 PRS0 2 Prescaler 3 2 1 0 3 2 1 0 3 2 1 0 PRS2 TCLK3 P127 udf TIO 5 udf TIO 6 S Output event bus 0 1 2 3...

Page 259: ...10 Select output event bus 2 11 Select TIO7 output 10 11 IEB2S 00 Select external input 0 TIN0 R W Input event bus 2 input select bit 01 Select external input 2 TIN2 10 Select external input 4 TIN4 11...

Page 260: ...2 4 Input Processing Control Unit The Input Processing Control Unit processes TCLK and TIN input signals to the MJT In TCLK input processing it selects the source of TCLK signal and for external input...

Page 261: ...Group User s Manual Rev 1 0 Count clock Count clock Count clock BCLK 2 Count clock BCLK 2 TCLK TCLK Count clock TCLK TCLK TCLK Count clock BCLK 2 Item Function BCLK 2 Rising edge Falling edge Both edg...

Page 262: ...N Input Processing Control Registers Internal edge signal Internal edge signal Internal edge signal Prescaler output period or TCLK input period TIN TIN Internal edge signal TIN TIN TIN Internal edge...

Page 263: ...ge 11 Both edges 4 No function assigned Fix to 0 0 0 5 7 TCLK2S 000 Disable input R W TCLK2 input processing select bit 001 Rising edge 010 Falling edge 011 Both edges 100 Low level 101 Low level 110...

Page 264: ...el 101 Low level 110 High level 111 High level 4 No function assigned Fix to 0 0 0 5 7 TIN3S 000 Disable input R W TIN3 input processing select bit 001 Rising edge 010 Falling edge 011 Both edges 100...

Page 265: ...evel 111 High level 4 No function assigned Fix to 0 0 0 5 7 TIN7S 000 Disable input R W TIN7 input processing select bit 001 Rising edge 010 Falling edge 011 Both edges 100 Low level 101 Low level 110...

Page 266: ...essing select bit 001 Rising edge 010 Falling edge 011 Both edges 100 Low level 101 Low level 110 High level 111 High level 8 No function assigned Fix to 0 0 0 9 11 TIN10S 000 Disable input R W TIN10...

Page 267: ...3 TIN13S TIN13 input processing select bit 14 15 TIN12S TIN12 input processing select bit Note This register must always be accessed in halfwords TIN20 23 TIN30 33 Input Processing Control Register TI...

Page 268: ...rol Register TIN2627CR Address H 0080 0BE1 9 10 11 12 13 14 b15 b8 TIN26S TIN27S 0 0 0 0 0 0 0 0 After reset H 00 b Bit Name Function R W 8 11 No function assigned Fix to 0 0 0 12 13 TIN27S TIN27 inpu...

Page 269: ...r FF1619S F F0 15 Protect Register FF015P F F16 20 Protect Register FF1620P F F21 28 Protect Register FF2128P F F29 36 Protect Register FF2936P F F37 44 Protect Register FF3744P F F0 15 Data Register...

Page 270: ...r underflows TIO Measure clear input mode When counter underflows Measure free run input mode When counter underflows Noise processing input mode When counter underflows PWM output mode When count is...

Page 271: ...R W F F13 source select bit 1 Output event bus 3 6 FS12 0 TIO1 output R W F F12 source select bit 1 Output event bus 2 7 FS11 0 TIO0 output R W F F11 source select bit 1 Output event bus 1 8 9 FS10 00...

Page 272: ...0 11 Output event bus 1 10 11 FS18 00 TIO7 output R W F F18 source select bit 01 TIO7 output 10 Output event bus 0 11 Output event bus 1 12 13 FS17 00 TIO6 output R W F F17 source select bit 01 TIO6 o...

Page 273: ...rotect bit 5 FP10 F F10 protect bit 6 FP9 F F9 protect bit 7 FP8 F F8 protect bit 8 FP7 F F7 protect bit 9 FP6 F F6 protect bit 10 FP5 F F5 protect bit 11 FP4 F F4 protect bit 12 FP3 F F3 protect bit...

Page 274: ...ame Function R W 8 FP29 F F29 protect bit 0 Enable write to F F output bit R W 9 FP30 F F30 protect bit 1 Disable write to F F output bit 10 FP31 F F31 protect bit 11 FP32 F F32 protect bit 12 FP33 F...

Page 275: ...0 output data bit 6 FD9 F F9 output data bit 7 FD8 F F8 output data bit 8 FD7 F F7 output data bit 9 FD6 F F6 output data bit 10 FD5 F F5 output data bit 11 FD4 F F4 output data bit 12 FD3 F F3 output...

Page 276: ...it 11 FD24 F F24 output data bit 12 FD25 F F25 output data bit 13 FD26 F F26 output data bit 14 FD27 F F27 output data bit 15 FD28 F F28 output data bit F F29 36 Data Register FF2936D Address H 0080 0...

Page 277: ...F38 output data bit 1 F F output data 1 10 FD39 F F39 output data bit 11 FD40 F F40 output data bit 12 FD41 F F41 output data bit 13 FD42 F F42 output data bit 14 FD43 F F43 output data bit 15 FD44 F...

Page 278: ...IN12 19 Interrupt Request Mask Register TIN1219IMA TIN20 23 Interrupt Request Mask Status Register TIN2023IMS TIN24 25 Interrupt Request Mask Register TIN2425IMA TIN24 25 Interrupt Request Status Regi...

Page 279: ...s status bit is used to determine whether there is an interrupt request When an interrupt request occurs this bit is set in hardware cannot be set in software The status bit is cleared by writing 0 Wr...

Page 280: ...STREG interrupt request status 1 ISTAT1 0x02 bit To clear an interrupt request status always be sure to write 1 to all other interrupt request status bits At this time avoid using a logic operation li...

Page 281: ...MS0 1 output interrupt 2 IRQ8 TIN7 TIN8 TIN9 TIN10 TIN11 TIN7 11 input interrupt 5 IRQ9 TIN0 TIN1 TIN2 TIN0 2 input interrupt 3 IRQ10 TIN12 TIN13 TIN14 TIN15 TIN16 TIN17 TIN12 19 input interrupt 8 TIN...

Page 282: ...t status bit 6 TOPIS1 interrupt request status bit 7 TOPIS0 interrupt request status bit Note 1 Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before the write TO...

Page 283: ...s b2 TOPIS5 F F TOPIM5 F F b10 b3 TOPIS4 F F TOPIM4 F F b11 b4 TOPIS3 F F TOPIM3 F F b12 b5 TOPIS2 F F TOPIM2 F F b13 b6 TOPIS1 F F TOPIM1 F F b14 b7 TOPIS0 F F TOPIM0 F F b15 Level 6 source inputs TO...

Page 284: ...R Note 1 3 TOPIS6 TOP6 interrupt request status bit 1 Interrupt requested 4 5 No function assigned Fix to 0 0 0 6 TOPIM7 TOP7 interrupt request mask bit 0 Enable interrupt request R W 7 TOPIM6 TOP6 in...

Page 285: ...0 0 0 6 TOPIM9 TOP9 interrupt request mask bit 0 Enable interrupt request R W 7 TOPIM8 TOP8 interrupt request mask bit 1 Mask disable interrupt request Note 1 Only writing 0 is effective Writing 1 has...

Page 286: ...status bit 3 TIOIS0 TIO0 interrupt request status bit 4 TIOIM3 TIO3 interrupt request mask bit 0 Enable interrupt request R W 5 TIOIM2 TIO2 interrupt request mask bit 1 Mask disable interrupt request...

Page 287: ...atus bit 11 TIOIS4 TIO4 interrupt request status bit 12 TIOIM7 TIO7 interrupt request mask bit 0 Enable interrupt request R W 13 TIOIM6 TIO6 interrupt request mask bit 1 Mask disable interrupt request...

Page 288: ...R Note 1 3 TIOIS8 TIO8 interrupt request status bit 1 Interrupt requested 4 5 No function assigned Fix to 0 0 0 6 TIOIM9 TIO9 interrupt request mask bit 0 Enable interrupt request R W 7 TIOIM8 TIO8 in...

Page 289: ...Note 1 11 TMSIS0 TMS0 interrupt request status bit 1 Interrupt requested 12 13 No function assigned Fix to 0 0 0 14 TMSIM1 TMS1 interrupt request mask bit 0 Enable interrupt request R W 15 TMSIM0 TMS...

Page 290: ...Interrupt requested 3 TINIS0 TIN0 interrupt request status bit 4 No function assigned Fix to 0 0 0 5 TINIM2 TIN2 interrupt request mask bit 0 Enable interrupt request R W 6 TINIM1 TIN1 interrupt reque...

Page 291: ...us bit 11 TINIS3 TIN3 interrupt request status bit 12 TINIM6 TIN6 interrupt request mask bit 0 Enable interrupt request R W 13 TINIM5 TIN5 interrupt request mask bit 1 Mask disable interrupt request 1...

Page 292: ...atus bit 6 TINIS8 TIN8 interrupt request status bit 7 TINIS7 TIN7 interrupt request status bit Note 1 Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before the wr...

Page 293: ...IRQ8 Data bus b3 TINIS11 F F TINIM11 F F b11 b4 TINIS10 F F TINIM4 F F b12 b5 TINIS9 F F TINIM9 F F b13 b6 TINIS8 F F TINIM8 F F b14 b7 TINIS7 F F TINIM7 F F b15 Level 5 source inputs TIN711IST H 0080...

Page 294: ...tus bit 6 TINIS13 TIN13 interrupt request status bit 7 TINIS12 TIN12 interrupt request status bit Note 1 Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before the...

Page 295: ...F F b9 b2 TINIS17 F F TINIM17 F F b10 b3 TINIS16 F F TINIM16 F F b11 b4 TINIS15 F F TINIM15 F F b12 Level 8 source inputs TIN1219IST H 0080 023C TIN1219IMA H 0080 023D TIN19edge TIN18edge TIN17edge T...

Page 296: ...st 6 TINIM21 TIN21 interrupt request mask bit 7 TINIM20 TIN20 interrupt request mask bit Note 1 Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before the write TI...

Page 297: ...0 0 14 TINIS26 TIN26 interrupt request status bit 0 Interrupt not requested R Note 1 15 TINIS27 TIN27 interrupt request status bit 1 Interrupt requested TIN28 29 Interrupt Request Mask Register TIN282...

Page 298: ...F F b7 b15 TINIS26 F F TINIM26 F F b6 b15 TINIS25 F F TINIM25 F F b7 Level 10 source inputs TIN2425IST H 0080 07E3 TIN2425IMA H 0080 07E2 TIN2627IST H 0080 0BE3 TIN2627IMA H 0080 0BE2 TIN2829IST H 008...

Page 299: ...1 0 To the preceding page Data bus b0 TINIS23 F F TINIM23 F F b4 b1 TINIS22 F F TINIM22 F F b5 b2 TINIS21 F F TINIM21 F F b6 b3 TINIS20 F F TINIM20 F F b7 4 source inputs TIN2023IMS H 0080 023E TIN23e...

Page 300: ...INIM33 TIN33 interrupt request mask bit 0 Enable interrupt request R W 13 TINIM32 TIN32 interrupt request mask bit 1 Mask disable interrupt request 14 TINIM31 TIN31 interrupt request mask bit 15 TINIM...

Page 301: ...TOU0IM1 TOU0_1 interrupt request mask bit 7 TOU0IM0 TOU0_0 interrupt request mask bit TOU0 Interrupt Request Status Register TOU0IST Address H 0080 07D3 9 10 11 12 13 14 b15 b8 TOU0IS7 TOU0IS6 TOU0IS...

Page 302: ...TOU0IM6 F F b1 b10 TOU0IS5 F F TOU0IM5 F F b2 b11 TOU0IS4 F F TOU0IM4 F F b3 b12 TOU0IS3 F F TOU0IM3 F F b4 Level 8 source inputs TOU0IMA H 0080 07D2 TOU0IST H 0080 07D3 TOU07udf TOU06udf TOU05udf TO...

Page 303: ...TOU1IM1 TOU1_1 interrupt request mask bit 7 TOU1IM0 TOU1_0 interrupt request mask bit TOU1 Interrupt Request Status Register TOU1IST Address H 0080 0BD3 9 10 11 12 13 14 b15 b8 TOU1IS7 TOU1IS6 TOU1IS...

Page 304: ...TOU2IM1 TOU2_1 interrupt request mask bit 7 TOU2IM0 TOU2_0 interrupt request mask bit TOU2 Interrupt Request Status Register TOU2IST Address H 0080 0CD3 9 10 11 12 13 14 b15 b8 TOU2IS7 TOU2IS6 TOU2IS...

Page 305: ...F TOU1IM5 F F b2 b11 TOU1IS4 F F TOU1IM4 F F b3 b12 TOU1IS3 F F TOU1IM3 F F b4 Level 16 source inputs TOU1IMA H 0080 0BD2 TOU1IST H 0080 0BD3 TOU17udf TOU16udf TOU15udf TOU14udf TOU13udf b13 TOU1IS2...

Page 306: ...IS5 F F TOU2IM5 F F b2 b11 TOU2IS4 F F TOU2IM4 F F b3 b12 TOU2IS3 F F TOU2IM3 F F b4 TOU2IMA H 0080 0CD2 TOU2IST H 0080 0CD3 TOU27udf TOU26udf TOU25udf TOU24udf TOU23udf b13 TOU2IS2 F F TOU2IM2 F F b5...

Page 307: ...e diagram in the next page shows a block diagram of TOP Table 10 3 1 Specifications of TOP Output Related 16 Bit Timer Item Specification Number of channels 11 channels Counter 16 bit down counter Rel...

Page 308: ...f TOP 5 TCLK0 P124 TIN0 P150 S S TIN0S clk en udf TOP 6 clk en udf TOP 7 S S S IRQ9 TIN1 P151 IRQ9 TIN2 P152 S S clk en udf TOP 8 clk en udf TOP 9 clk en udf TOP 10 F F0 F F1 F F2 F F3 F F4 F F5 F F6...

Page 309: ...rflows it is loaded with the reload register value and continues counting down The counter stops when it underflows next time The F F output waveform in delayed single shot output mode is inverted whe...

Page 310: ...nabled till when it actually starts operating In operation mode where the F F output is inverted when the timer is enabled there is also a count clock dependent delay before the F F output is inverted...

Page 311: ...ister 10 77 TOP1CC Use inhibited area H 0080 0260 TOP2 Counter 10 75 TOP2CT H 0080 0262 TOP2 Reload Register 10 76 TOP2RL H 0080 0264 Use inhibited area H 0080 0266 TOP2 Correction Register 10 77 TOP2...

Page 312: ...inhibited area H 0080 02B6 TOP7 Correction Register 10 77 TOP7CC Use inhibited area H 0080 02C0 TOP8 Counter 10 75 TOP8CT H 0080 02C2 TOP8 Reload Register 10 76 TOP8RL H 0080 02C4 Use inhibited area H...

Page 313: ...lect operation modes of TOP0 10 single shot output delayed single shot output or continuous output mode as well as select the count enable and count clock sources Following four TOP control registers...

Page 314: ...e source select bit 001 ditto 010 ditto 011 ditto 100 Input event bus 0 101 Input event bus 1 110 Input event bus 2 111 Input event bus 3 12 13 No function assigned Fix to 0 0 0 14 15 TOP05CKS 00 Cloc...

Page 315: ...1 0 clk en TOP 0 Clock bus Input event bus clk en TOP 1 clk en TOP 2 clk en TOP 3 3 2 1 0 clk en TOP 4 clk en TOP 5 S S Selector TIN0 P150 S TIN0S 3 2 1 0 Note This diagram only illustrates TOP contro...

Page 316: ...peration mode select bit 01 Delayed single shot output mode 10 Continuous output mode 11 ditto 8 No function assigned Fix to 0 0 0 9 11 TOP67ENS 000 External TIN1 input R W TOP6 TOP7 enable source sel...

Page 317: ...0 After reset H 0000 b Bit Name Function R W 0 1 No function assigned Fix to 0 0 0 2 3 TOP10M TOP10 operation mode select bit 00 Single shot output mode R W 4 5 TOP9M TOP9 operation mode select bit 0...

Page 318: ...r TOP6CT Address H 0080 02A0 TOP7 Counter TOP7CT Address H 0080 02B0 TOP8 Counter TOP8CT Address H 0080 02C0 TOP9 Counter TOP9CT Address H 0080 02D0 TOP10 Counter TOP10CT Address H 0080 02E0 b0 1 2 3...

Page 319: ...er TOP10RL Address H 0080 02E2 b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOP0RL TOP10RL After reset Undefined b Bit Name Function R W 0 15 TOP0RL TOP10RL 16 bit reload register value R W Note This regis...

Page 320: ...TOP10CC 16 bit correction register value R W Note This register must always be accessed in halfwords The TOP correction registers are used to correct the TOP counter value by adding or subtracting in...

Page 321: ...P0 external enable permit bit Note This register must always be accessed in halfwords The TOP External Enable Permit Register controls enable operation on TOP counters from external devices by enablin...

Page 322: ...TOP1 count enable bit 15 TOP0CEN TOP0 count enable bit Note This register must always be accessed in halfwords The TOP Count Enable Register controls operation of TOP counters To enable any TOP counte...

Page 323: ...n single shot output mode is inverted F F output levels change from low to high or vice versa at startup and upon underflow generating a single shot pulse waveform in width of reload regis ter set val...

Page 324: ...es counting down until it underflows after reaching the minimum count Count clock Correction register H FFFF H 0000 Enabled by writing to the enable bit or by external input F F output Disabled by und...

Page 325: ...ith a count clock pulse next to one at which the correction value was written to the TOP correction register If the counter is corrected this way note that because one down count in that clock period...

Page 326: ...rupt request due to underflow Enable bit Note This diagram does not show detailed timing information Reload register Write to the correction register Undefined value Disabled by underflow Counter In t...

Page 327: ...so that count is enabled If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit the latter has priority so that count is disabled Because...

Page 328: ...ternal input Disabled by underflow Undefined value Actual count after overflow Overflow occurs Undefined Figure 10 3 11 Example of an Operation in TOP Single shot Output Mode Where Count Overflows Due...

Page 329: ...e shot output mode is inverted F F output level changes from low to high or vice versa when the counter underflows first time and next generating a single shot pulse waveform in width of reload regist...

Page 330: ...ng down The counter stops when it underflows second time Figure 10 3 13 Typical Operation in TOP Delayed Single shot Output Mode H FFFF H 0000 Underflow first time Count down from the counter s set va...

Page 331: ...actually is corrected by correction register value 1 For example if the reload register value is 7 and the value 3 is written to the correction register when the counter has counted down to 3 after b...

Page 332: ...Counter Count clock Underflow first time Underflow second time Enabled by writing to the enable bit or by external input Undefined In the example below the counter and the reload register are initiall...

Page 333: ...latter has priority so that count is disabled Even if the counter overflows due to correction of counts no interrupt requests are generated for reasons of an overflow Therefore if the counter underflo...

Page 334: ...underflow occurs To stop the counter disable count by writing to the enable bit in software The F F output waveform in continuous output mode is inverted F F output level changes from low to high or...

Page 335: ...H 0000 H E000 H A000 H E000 H E000 1 H E000 1 H FFFF H FFFF Data inverted by underflow Data inverted by underflow Data inverted by enable Count clock Correction register F F output TOP interrupt reque...

Page 336: ...he same clock period as count is disabled by writing to the enable bit the latter has priority so that count is disabled If the counter is accessed for read immediately after being reloaded pursuant t...

Page 337: ...elow shows specifications of TIO The diagram in the next page shows a block diagram of TIO Table 10 4 1 Specifications of TIO Input Output Related 16 Bit Timer Item Specification Number of channels 10...

Page 338: ...LK2S S TIN8S IRQ8 TIN9 P141 clk en cap udf TIO 7 S S TIN9S IRQ8 TIN10 P142 S S TIN10S clk en cap udf TIO 8 clk en cap udf TIO 9 IRQ8 TIN11 P143 S S TIN11S F F11 F F12 F F13 F F14 F F15 S F F16 F F17 F...

Page 339: ...input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows the counter generates an interrupt request before stopping If...

Page 340: ...r value and continues counting down The counter stops when it underflows next time The F F output waveform in delayed single shot output mode is inverted when the counter underflows first time and nex...

Page 341: ...s enabled till when it actually starts operating In operation mode where the F F output is inverted when the timer is enabled there is also a count clock dependent delay before the F F output is inver...

Page 342: ...ed area H 0080 031A TIO0 3 Control Register 0 10 102 TIO03CR0 H 0080 031C Use inhibited area TIO0 3 Control Register 1 10 103 TIO03CR1 Use inhibited area H 0080 0320 TIO2 Counter 10 109 TIO2CT H 0080...

Page 343: ...07 TIO6CR TIO7CR 10 108 Use inhibited area H 0080 0370 TIO7 Counter 10 109 TIO7CT H 0080 0372 Use inhibited area H 0080 0374 TIO7 Reload 1 Register 10 111 TIO7RL1 H 0080 0376 TIO7 Reload 0 Measure Reg...

Page 344: ...output single shot output delayed single shot output or continuous output mode as well as select the count enable and count clock sources Following TIO control registers are provided for each timer g...

Page 345: ...11 TIO1M 000 Single shot output mode R W TIO1 operation mode select bit 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure fre...

Page 346: ...0 0 0 14 15 TIO03CKS 00 Clock bus 0 R W TIO0 3 clock source select bit 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 Figure 10 4 3 Outline Diagram of TIO0 4 Clock and Enable Inputs Clock bus Input even...

Page 347: ...3 5 7 TIO4M 000 Single shot output mode R W TIO4 operation mode select bit 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure...

Page 348: ...N7 P157 TCLK1 P125 clk en cap TIO 5 S TCLK1S S TIN7S TIN8 P140 TCLK2 P126 TIO 6 TIN9 P141 clk en cap TIO 7 S S TIN9S TIN10 P142 S S TIN10S clk en cap TIO 8 clk en cap TIO 9 TIN11 P143 S S TIN11S S Sel...

Page 349: ...tto 011 ditto 100 Clock bus 0 101 Clock bus 1 110 Clock bus 2 111 Clock bus 3 11 12 TIO5ENS 00 No selection R W TIO5 enable measure input source select bit 01 ditto 10 External input TIN7 11 Input eve...

Page 350: ...ditto 100 Clock bus 0 101 Clock bus 1 110 Clock bus 2 111 Clock bus 3 3 4 TIO6ENS 00 No selection R W TIO6 enable measure input source select bit 01 External input TIN8 10 Input event bus 2 11 Input...

Page 351: ...Measure free run input mode 110 Noise processing input mode 111 ditto Note Operation mode can only be set or changed while the counter is inactive TIO8 Control Register TIO8CR Address H 0080 038A 1 2...

Page 352: ...rs are a 16 bit down counter After the timer is enabled by writing to the enable bit in software or by external input the counter starts counting synchronously with the count clock These counters are...

Page 353: ...gainst write during measure input mode Note This register must always be accessed in halfwords The TIO Reload 0 Measure Registers serve dual purposes as a register for reloading data into the TIO Coun...

Page 354: ...0080 0374 TIO8 Reload 1 Register TIO8RL1 Address H 0080 0384 TIO9 Reload 1 Register TIO9RL1 Address H 0080 0394 b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TIO0RL1 TIO9RL1 After reset Undefined b Bit Name...

Page 355: ...nction assigned Fix to 0 0 0 6 TIO9PRO TIO9 enable protect bit 0 Enable rewrite R W 7 TIO8PRO TIO8 enable protect bit 1 Disable rewrite 8 TIO7PRO TIO7 enable protect bit 9 TIO6PRO TIO6 enable protect...

Page 356: ...nt 8 TIO7CEN TIO7 count enable bit 9 TIO6CEN TIO6 count enable bit 10 TIO5CEN TIO5 count enable bit 11 TIO4CEN TIO4 count enable bit 12 TIO3CEN TIO3 count enable bit 13 TIO2CEN TIO2 count enable bit 1...

Page 357: ...sure register In measure clear input mode the counter value is initialized to H FFFF upon capture from which the counter starts counting down again When the counter underflows it starts counting down...

Page 358: ...ame clock period the write value is set in the counter while at the same time latched into the measure register Figure 10 4 7 Typical Operation in Measure Clear Input Mode H FFFF H 0000 H 7000 H 0008...

Page 359: ...valid level before the counter underflows the counter temporarily stops counting and when a valid level signal is entered again the counter is reloaded with the initial count and restarts counting The...

Page 360: ...uty cycle When the timer is enabled by writing to the enable bit in software or by external input after setting the initial values in the reload 0 and reload 1 registers the counter is loaded with the...

Page 361: ...data written to the register is reflected in the next period 3 Precautions on using TIO PWM output mode The following describes precautions to be observed when using TIO PWM output mode If the timer i...

Page 362: ...8000 H 9000 Enlarged view Old PWM output period F F output H 7FFE H 0000 PWM period latched Reload 1 buffer H 2000 H 9000 New PWM output period New PWM output period Note This diagram does not show d...

Page 363: ...aveform in width of reload 0 register set value 1 only once An interrupt request can be generated when the counter underflows The count value is reload 0 register set value 1 For counting operation se...

Page 364: ...led by underflow Unused TIO interrupt request due to underflow Enable bit Count down from the reload 0 register set value Note This diagram does not show detailed timing information Reload 0 register...

Page 365: ...th of reload 0 register set value 1 after a finite time equal to first set value of counter 1 only once An interrupt request can be generated when the counter underflows first time and next The counte...

Page 366: ...reload 0 register set value H EFFF H F000 Data inverted by underflow Data inverted by underflow Count clock F F output Unused TIO interrupt request due to underflow Enable bit Note This diagram does n...

Page 367: ...low occurs To stop the counter disable count by writing to the enable bit in software The F F output waveform in continuous output mode is inverted F F output level changes from low to high or vice ve...

Page 368: ...errupt request due to underflow Enable bit Note This diagram does not show detailed timing information Reload 0 register Counter Reload 1 register Underflow first time Count down from thecounter set v...

Page 369: ...of 4 channels each 8 channels in total Counter 16 bit up counter 2 Measure register 16 bit measure register 8 Timer startup Started by writing to the enable bit in software Interrupt request generati...

Page 370: ...47 S S S S S TIN16S DMA5 TIN17S TIN16 P130 TIN17 P131 TIN18S TIN18 P132 TIN19S TIN19 P133 DMA6 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 Output event bus 0 1 2 3 IRQ7 S Selector 3 2 1 0 3 2 1 0 0 1 2...

Page 371: ...0 TMS0MR0 H 0080 03CA TMS0 Control Register TMS1 Control Register 10 129 TMS0CR TMS1CR Use inhibited area H 0080 03D0 TMS1 Counter 10 130 TMS1CT H 0080 03D2 TMS1 Measure 3 Register 10 130 TMS1MR3 H 00...

Page 372: ...TIN12 R W TMS0 measure 3 source select bit 1 Input event bus 3 4 5 TMS0CKS 00 External input TCLK3 R W TMS0 clock source select bit 01 Clock bus 0 10 Clock bus 1 11 Clock bus 3 6 No function assigned...

Page 373: ...MS1MR3 0 TMS0 Measure 3 Register TMS0MR3 Address H 0080 03C2 TMS0 Measure 2 Register TMS0MR2 Address H 0080 03C4 TMS0 Measure 1 Register TMS0MR1 Address H 0080 03C6 TMS0 Measure 0 Register TMS0MR0 Add...

Page 374: ...generated when the counter overflows Count clock Counter H FFFF H 0000 Enabled by writing to the enable bit Measure event 1 occurs Undefined Enable bit Note This diagram does not show detailed timing...

Page 375: ...register 1 Measure register 0 Measure register 3 Measure register 2 Measure register 1 Measure register 0 Counter 32 bit 10 6 TML Input Related 32 Bit Timer 10 6 1 Outline of TML TML Timer Measure La...

Page 376: ...egister map TML Related Register Map Address 0 address 1 address See pages b0 b7 b8 b15 H 0080 03E0 TML0 Counter Upper 10 135 TML0CT H 0080 03E2 Lower H 0080 03EA Use inhibited area TML0 Control Regis...

Page 377: ...ce for the counter If the selected clock source is not BCLK 2 do not write to the counter because it cannot be written normally TML1 Control Register TML1CR Address H 0080 0FEB 9 10 11 12 13 14 b15 b8...

Page 378: ...easure 3 Register TML0MR3 Address H 0080 03F0 TML0 Measure 2 Register TML0MR2 Address H 0080 03F4 TML0 Measure 1 Register TML0MR1 Address H 0080 03F8 TML0 Measure 0 Register TML0MR0 Address H 0080 03F...

Page 379: ...ed by measure signal input from an external device However no TML counter overflow interrupts are available Figure 10 6 2 Typical Operation of TML Measure Input Count clock Counter 32 bit H FFFF FFFF...

Page 380: ...er the counter cannot be written normally Therefore when using any clock other than BCLK 2 do not write to the counter If clock bus 1 is selected and any clock other than BCLK 2 is used for the timer...

Page 381: ...nt mode Up down event count mode The table below shows specifications of TID The diagram in the next page shows a block diagram of TID Table 10 7 1 Specifications of TID Input Related 16 Bit Timer Ite...

Page 382: ...TIN24S TIN26S TIN28S Clock control Reload register Up down counter TID 1 clk CLK1 CLK2 ovf udf Clock control Reload register TID 2 clk CLK1 CLK2 ovf udf Clock control Reload register PRS4 PRS5 Up dow...

Page 383: ...load Register 10 144 TID0RL H 0080 07D0 Prescaler Register 3 TID0 Control Prescaler 3 Enable Register 10 12 PRS3 TID0PRS3EN 10 141 H 0080 0B8C TID1 Counter 10 144 TID1CT H 0080 0B8E TID1 Reload Regist...

Page 384: ...nt count mode 111 Up down event count mode 11 TID0CEN 0 Stop TID0 count R W TID0 count enable bit 1 Start TID0 count 12 14 TOU0ENS 000 Disable event enable R W TOU0 enable source select bit 001 ditto...

Page 385: ...it 1 Start TID1 count 12 14 TOU1ENS 000 Disable event enable R W TOU1 enable source select bit 001 ditto 010 TID1 underflow overflow 011 TOU1_7 underflow 100 Disable event enable 101 ditto 110 TOU0 st...

Page 386: ...it 1 Start TID2 count 12 14 TOU2ENS 000 Disable event enable R W TOU2 enable source select bit 001 ditto 010 TID2 underflow overflow 011 TOU2_7 underflow 100 Disable event enable 101 ditto 110 TOU0 st...

Page 387: ...ad Registers TID0RL TID1RL and TID2RL TID0 Reload Register TID0RL Address H 0080 078E TID1 Reload Register TID1RL Address H 0080 0B8E TID2 Reload Register TID2RL Address H 0080 0C8E b0 1 2 3 4 5 6 7 8...

Page 388: ...nts down and when it underflows after reaching the minimum count the counter is loaded with the content of the reload register and continues counting To stop the counter disable count by writing to th...

Page 389: ...When after setting the counter the timer is enabled by writing to the enable bit in software the counter starts counting up from the set count value synchronously with the generated clock An interrupt...

Page 390: ...signals the timer generates clock pulses synchronized to the microcomputer s internal clock When after setting the counter the timer is en abled by writing to the enable bit in software the counter st...

Page 391: ...Multiply by 4 Count Operation Count Enabled Disabled 8000 TIN24 TIN26 TIN28 TIN25 TIN27 TIN29 8001 8000 8001 7FFE 7FFF 7FFE Timer enable Count disabled Count enabled 7FFF enabled Up count Down count C...

Page 392: ...ated clock The count direction is determined by the level of the up down select input signal see Table 10 7 3 An interrupt request can be generated when the counter underflows or overflows To stop the...

Page 393: ...wn counter when in PWM output or single shot PWM output mode Reload register 24 bit reload register or 16 bit reload register when in PWM output or single shot PWM output mode Timer startup TOU0 Writi...

Page 394: ...bit clk en udf TOU0_2 24 bit clk en udf TOU0_3 24 bit clk en udf TOU0_4 24 bit clk en udf TOU0_5 24 bit clk en udf TOU0_6 24 bit clk en udf TOU0_7 24 bit clk en udf TID 0 clk CLK1 CLK2 ovf udf TOU1_0...

Page 395: ...1 registers the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock The first time the counter underflows it is loaded with the reload 1 reg...

Page 396: ...starting from the set value of the counter and when the counter underflows it is loaded with the reload register value Thereafter this operation is repeated each time the counter underflows thus gene...

Page 397: ...1 10 167 H 0080 079E TOU0_1 Reload 0 Register 10 166 TOU01RL0 H 0080 07A0 TOU0_2 Counter Upper 10 161 TOU02CTW TOU02CTH H 0080 07A2 Lower 10 163 TOU02CT H 0080 07A4 TOU0_2 Reload Register TOU0_2 Reloa...

Page 398: ...0B92 Lower 10 163 TOU10CT H 0080 0B94 TOU1_0 Reload Register TOU1_0 Reload 1 Register 10 164 TOU10RLW TOU10RL1 10 167 H 0080 0B96 TOU1_0 Reload 0 Register 10 166 TOU10RL0 H 0080 0B98 TOU1_1 Counter Up...

Page 399: ...pt Request Mask Register TOU1 Interrupt Request Status Register 10 60 TOU1IMA TOU1IST H 0080 0BD8 TOU1 Control Register 1 10 159 TOU1CR1 H 0080 0BDA TOU1 Control Register 0 10 159 TOU1CR0 H 0080 0BDC...

Page 400: ...Register 10 164 TOU25RLW TOU25RL1 10 167 H 0080 0CBE TOU2_5 Reload 0 Register 10 166 TOU25RL0 H 0080 0CC0 TOU2_6 Counter Upper 10 161 TOU26CTW TOU26CTH H 0080 0CC2 Lower 10 163 TOU26CT H 0080 0CC4 TOU...

Page 401: ...anged while the counter is inactive TOU0 Control Register 1 TOU0CR1 Address H 0080 07D8 b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOU0CKS TOU00M1 TOU01M1 TOU02M1 TOU03M1 TOU05M1 TOU06M1 TOU07M1 TOU04M1...

Page 402: ...e counter is inactive TOU1 Control Register 1 TOU1CR1 Address H 0080 0BD8 b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOU1CKS TOU10M1 TOU11M1 TOU12M1 TOU13M1 TOU15M1 TOU16M1 TOU17M1 TOU14M1 0 0 0 0 0 0 0...

Page 403: ...e counter is inactive TOU2 Control Register 1 TOU2CR1 Address H 0080 0CD8 b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOU2CKS TOU20M1 TOU21M1 TOU22M1 TOU23M1 TOU25M1 TOU26M1 TOU27M1 TOU24M1 0 0 0 0 0 0 0...

Page 404: ...0 0BA0 TOU1_3 Counter TOU13CTW Address H 0080 0BA8 TOU1_4 Counter TOU14CTW Address H 0080 0BB0 TOU1_5 Counter TOU15CTW Address H 0080 0BB8 TOU1_6 Counter TOU16CTW Address H 0080 0BC0 TOU1_7 Counter TO...

Page 405: ...the counter is written to in 32 bit units it is rewritten successively in order of the 8 high order bits and then the 16 low order bits automatically During PWM output or single shot PWM output mode t...

Page 406: ...C9A TOU2_2 Counter TOU22CT Address H 0080 0CA2 TOU2_3 Counter TOU23CT Address H 0080 0CAA TOU2_4 Counter TOU24CT Address H 0080 0CB2 TOU2_5 Counter TOU25CT Address H 0080 0CBA TOU2_6 Counter TOU26CT A...

Page 407: ...Reload Register TOU12RLW Address H 0080 0BA4 TOU1_3 Reload Register TOU13RLW Address H 0080 0BAC TOU1_4 Reload Register TOU14RLW Address H 0080 0BB4 TOU1_5 Reload Register TOU15RLW Address H 0080 0BB...

Page 408: ...ontent of the reload register is loaded into the counter in the following cases When the counter is enabled in single shot output mode When the counter has underflowed in delayed single shot output or...

Page 409: ...25RL0 Address H 0080 0CBE TOU2_6 Reload 0 Register TOU26RL0 Address H 0080 0CC6 TOU2_7 Reload 0 Register TOU27RL0 Address H 0080 0CCE b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOU00RL0 TOU07RL0 TOU10RL0...

Page 410: ...ster TOU26RL1 Address H 0080 0CC4 TOU2_7 Reload 1 Register TOU27RL1 Address H 0080 0CCC b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOU00RL1 TOU07RL1 TOU10RL1 TOU17RL1 TOU20RL1 TOU27RL1 After reset Undefi...

Page 411: ...PRO TOUn 6PRO TOUn 7PRO 0 0 0 0 0 0 0 0 After reset H 00 b Bit Name Function R W 8 TOUn0PRO 0 Enable rewrite R W TOUn_0 enable protect bit 1 Disable rewrite 9 TOUn1PRO TOUn_1 enable protect bit 10 TOU...

Page 412: ...count enable bit 12 TOUn4CEN TOUn_4 count enable bit 13 TOUn5CEN TOUn_5 count enable bit 14 TOUn6CEN TOUn_6 count enable bit 15 TOUn7CEN TOUn_7 count enable bit The TOU count enable registers control...

Page 413: ...PRO WR EN ON TOU1mCEN F F F F TID1_udf ovf TOU1_7udf TIN27S TID0_udf ovf TOU0_7udf TIN25S TOU1m enable protect TOU0 enable source selection TOU0ENS Event enable disable Output event bus 0 Event enable...

Page 414: ...0S write control bit 5 7 PWMOFF0S 000 Input has no effect R W PWMOFF0 input processing control bit 001 Rising edge 010 Falling edge 011 Both edges 10X Low level 11X High level PWMOFF1 Input Processing...

Page 415: ...ve edge or level entered for PWM output disable control from an external pin For details about the PWM output disable function see Section 10 8 18 PWM Output Disable Function To set the PWMOFF input p...

Page 416: ...OFFnSP 1 PWMOFFnSP 0 PWMOFFnS Set value Example of correct settings Cases where settings have no effect Because a write cycle to other area exists the set value is not reflected PWMOFFnSP 1 Write to o...

Page 417: ...0 5 No function assigned Fix to 0 0 0 6 PO0DISP 0 W PO0DIS write control bit 7 PO0DIS 0 Enable output R W P160 TO21 P165 TO26 output disable select bit 1 Disable output PWM Output 1 Disable Control R...

Page 418: ...M output can be forcibly disabled placed in the high impedance state by controlling this reg ister For details see Section 10 8 18 PWM Output Disable Function Also if this register is accessed for rea...

Page 419: ...t was set in the POnDIS bit is not reflected POnDISP 1 POnDISP 0 POnDIS Set value Example of correct settings Cases where settings have no effect Because a write cycle to other area exists the set val...

Page 420: ...O29 P185 TO34 output disable level select bit 1 Select high output disable level 15 PO1LVEN 0 Disable selected output disable level R W Output disable level enable disable select bit 1 Enable selected...

Page 421: ...P183 TO32 TOU1_3 output pin output both are at the low level P184 TO33 TOU1_4 output pin output and P185 TO34 TOU1_5 output pin output both are at the low level 4 PO1LVSEL 1 If any one of the followin...

Page 422: ...time count is disabled by writing to the enable bit and not in synchronism with PWM output period The F F output waveform in PWM output mode is inverted F F output level changes from low to high or v...

Page 423: ...his diagram does not show detailed timing information Reload 0 register H A000 Underflow second time H C000 1 Data inverted by underflow Data inverted by enable H A000 1 Data inverted by underflow Rel...

Page 424: ...only the reload 0 register is updated Note also that if the reload 0 and reload 1 registers are accessed for read the read values are always the data that have been written to the respective registers...

Page 425: ...hed H 1000 H 2000 H 8000 H 9000 Enlarged view New PWM output period Old PWM output period F F output H 7FFE H 0000 PWM period latched Reload 1 buffer H 2000 H 9000 H 0001 H FFFF H 1000 H 0FFF H 2000 H...

Page 426: ...ated New PWM output period Operation by new reload value written Reload 0 register Reload 1 register F F output Write to reload 1 Write to reload 0 Reload 1 data latched Enlarged view New PWM output p...

Page 427: ...led If the value FFFF is set in the reload register F F output will not be inverted although an interrupt request is generated upon underflow making it possible to produce a 0 or 100 duty cycle PWM ou...

Page 428: ...ut Underflow first time Interrupt request due to underflow Enable bit Note This diagram does not show detailed timing information Reload 0 register H A000 H A000 Underflow second time H F000 H EFFF Da...

Page 429: ...t values For counting operation see also Section 10 3 10 Operation of TOP Delayed Single shot Output Mode 2 Precautions on using TOU delayed single shot output mode The following describes precautions...

Page 430: ...H 10 F000 H 10 EFFF Data inverted by underflow Data inverted by underflow H 08 A000 1 Count clock Enabled by writing to the enable bit or by external input F F output Underflow first time Interrupt re...

Page 431: ...ation see also Section 10 3 9 Opera tion of TOP Single shot Output Mode 2 Precautions on using TOU single shot output mode The following describes precautions to be observed when using TOU single shot...

Page 432: ...t clock H FF FFFF H 00 0000 Enabled by writing to the enable bit or by external input F F output Disable due to underflow Interrupt request due to underflow Enable bit Count down from the reload 0 reg...

Page 433: ...vice versa at startup and upon underflow generating a waveform of consecutive pulses until the timer stops counting An interrupt request can be generated each time the counter underflows The counter s...

Page 434: ...000 H 0A 0000 Underflow second time H 0E 0000 Count down from the reload 0 register set value H 00 FFFF Count down from the reload 0 register set value H 0D FFFF Data inverted by enable Data inverted...

Page 435: ...80 20 90 10 100 0 Count ratio 5 5 8 2 9 1 10 0 Register set values 0004 0004 0007 0001 0008 0000 0009 FFFF Because the counter counts n 1 the values actually set in the respective registers must be on...

Page 436: ...by external input Count down from the reload 1 register set value Count down from the reload 1 register set value Underflow Superficial underflow H FFFF H 0000 H FFFF H E000 H E000 1 H FFFF 1 H FFFF 1...

Page 437: ...e same timing Note This diagram does not show detailed timing information Data not inverted Counter Undefined value Enable bit Reload 0 register Reload 1 register F F output Interrupt request due to u...

Page 438: ...iming Note This diagram does not show detailed timing information Counter Undefined value Enable bit Reload 0 register Reload 1 register F F output Interrupt request due to underflow Note 1 Count cloc...

Page 439: ...is generated Enabled by writing to the enable bit or by external input Note 1 DMA transfer request also is generated with the same timing Note This diagram does not show detailed timing information C...

Page 440: ...F F F F F F F TIN16S PWMOFF0S RD b7 P160 TO21 P161 TO22 P162 TO23 P163 TO24 P164 TO25 P165 TO26 P166 TO27 P167 TO28 P160 internal P160 internal P161 internal P162 internal P163 internal P164 internal...

Page 441: ...P160 TO21 P165 TO26 that are provided for the PWM outputs of the TOU0_0 TOU0_5 timers Similarly the input signal on the external pin TIN17 PWMOFF1 may be used to disable outputs from the ports P180 TO...

Page 442: ...tputs from the ports P180 TO29 P185 TO34 that are provided for the PWM outputs of the TOU1_0 TOU1_5 timers Also the PWM Output 2 Control Register PO2DISCR may be used to disable outputs from the ports...

Page 443: ...TO42 that are provided for the PWM outputs of the TOU2_0 TOU2_5 timers To disable PWM outputs using the pin level of ports set up the PWM Output Disable Control Register POnLVCR as described below Whe...

Page 444: ...rm data only when the data needs to be rewritten Note that the transistor shorting prevention time can be provided by changing the set time of TOU in software 32180 Power MOS Motor U U V V W W TOU TOU...

Page 445: ...10 10 202 MULTIJUNCTION TIMERS 10 8 TOU Output Related 24 Bit Timer 32180 Group User s Manual Rev 1 0 This page is blank for reasons of layout...

Page 446: ...11 A D CONVERTERS 11 1 Outline of A D Converters 11 2 A D Converter Related Registers 11 3 Functional Description of A D Converters 11 4 Inflow Current Bypass Circuit 11 5 Precautions on Using A D Con...

Page 447: ...ode start after single mode execution Scan operation is started subsequently after executing conversion in single mode Conversion restart A D conversion being executed in single or scan mode is restar...

Page 448: ...D conversion start bit to 1 Hardware start A D0 Converter MJT input event bus 2 MJT input event bus 3 MJT output event bus 3 and MJT TIN23S A D1 Converter MJT input event bus 2 MJT input event bus 3 T...

Page 449: ...D0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 DMA transfer request Successive Approximation type A D Converter Unit Internal data bus A...

Page 450: ...ster 2 10 bit A D1 Data Register 3 10 bit A D1 Data Register 4 10 bit A D1 Data Register 5 10 bit A D1 Data Register 6 10 bit A D1 Data Register 7 10 bit A D1 Data Register 8 10 bit A D1 Data Register...

Page 451: ...ion result is stored in each channel s corresponding 10 bit A D Data Register There is also an 8 bit A D Data Register for each channel from which 8 bit A D conversion results can be read out An A D c...

Page 452: ...ed channels from channel 0 ADiIN0 i 0 or 1 to the channel channels 0 15 selected by the A D Scan Mode Register 1 scan loop select bit are sequen tially A D converted There are two types of scan mode S...

Page 453: ...inated B 0010 2 ADiIN0 ADiIN0 10 bit A Di Data Register 0 ADiIN2 ADiIN1 ADiIN1 10 bit A Di Data Register 1 ADiIN2 ADiIN2 10 bit A Di Data Register 2 Completed ADiIN0 10 bit A Di Data Register 0 Repeat...

Page 454: ...ister s A D conversion start bit to 1 For comparate mode write a comparison value to the A D Succes sive Approximation Register AD0SAR or AD1SAR during scan mode operation To start single mode convers...

Page 455: ...using the A D Scan Mode Register 0 A D conver sion start trigger select bit Then set the said register s A D conversion start bit to 1 during single mode conversion operation To start this mode in har...

Page 456: ...are trigger signal during scan operation and the channel being converted is canceled and A D conver sion is performed from channel 0 over again Figure 11 1 8 Conversion Restart during Single Mode Oper...

Page 457: ...ion The analog input voltage that was sampled immediately after A D conversion started is held on and A D conver sion is performed on that seized voltage The A D conversion time in normal sample and h...

Page 458: ...DT2 H 0080 0096 10 bit A D0 Data Register 3 11 31 AD0DT3 H 0080 0098 10 bit A D0 Data Register 4 11 31 AD0DT4 H 0080 009A 10 bit A D0 Data Register 5 11 31 AD0DT5 H 0080 009C 10 bit A D0 Data Register...

Page 459: ...22 H 0080 0A86 A D1 Disconnection Detection Assist Function Control Register A D1 Conversion Speed Control Register 11 25 AD1DDACR AD1CVSCR 11 24 H 0080 0A88 A D1 Successive Approximation Register 11...

Page 460: ...a 8 bit A D1 Data Register 5 11 32 AD18DT5 H 0080 0ADC Use inhibited area 8 bit A D1 Data Register 6 11 32 AD18DT6 H 0080 0ADE Use inhibited area 8 bit A D1 Data Register 7 11 32 AD18DT7 H 0080 0AE0 U...

Page 461: ...r request 5 ADSCMP 0 A D conversion comparate in progress R A D conversion comparate completed bit 1 A D conversion comparate completed 6 ADSSTP 0 No operation 0 W A D conversion stop bit 1 Stop A D c...

Page 462: ...A D Conversion Stop bit Bit 6 Setting this bit to 1 while the A D Converter is performing single mode operation A D conversion or comparate causes the operation being performed to stop Manipulation of...

Page 463: ...e and hold R W A D sample and hold conversion speed select bit 1 Fast sample and hold 12 15 ANSEL 0000 Select ADiIN0 i 0 1 R W A D analog input pin select bit 0001 Select ADiIN1 0010 Select ADiIN2 001...

Page 464: ...of this bit has no effect if comparator mode is selected with the ADSMSL A D conversion mode select bit 4 ADSSHSPD A D Sample and Hold Speed Select bit Bit 11 When the A D Converter s sample and hold...

Page 465: ...it 1 Hardware trigger 4 ADCREQ 0 A D conversion interrupt request R W Interrupt DMA transfer request select bit 1 DMA transfer request 5 ADCCMP 0 A D conversion in progress R A D conversion completed...

Page 466: ...pletion of A D conversion 5 ADCCMP A D Conversion Completed bit Bit 5 This is a read only bit whose value after reset is 1 This bit is 0 when the A D Converter is performing scan mode A D conversion a...

Page 467: ...1111 channels 0 15 For read during conversion i 0 1 0000 Converting ADiIN0 0001 Converting ADiIN1 0010 Converting ADiIN2 0011 Converting ADiIN3 0100 Converting ADiIN4 0101 Converting ADiIN5 0110 Conv...

Page 468: ...eed faster than normal A D conversion speed Setting of this bit has no effect if the sample and hold function is disabled by setting the ADCSHSL A D conversion method select bit to 0 For details about...

Page 469: ...0 After reset H 00 b Bit Name Function R W 8 14 No function assigned Fix to 0 0 0 15 ADCVSD Note 1 0 Slow mode R W A D conversion speed control bit 1 Fast mode Note 1 The A D conversion speed is dete...

Page 470: ...A D disconnection detection assist function enable bit 1 Enable A D disconnection detection assist function Note 1 For the A D disconnection detection assist function to be enabled the conversion star...

Page 471: ...DDASEL6 Channel 6 disconnection detection assist method select bit 7 ADDDASEL7 Channel 7 disconnection detection assist method select bit 8 ADDDASEL8 Channel 8 disconnection detection assist method se...

Page 472: ...lected Figure 11 2 2 Example of A D Disconnection Detection on AVSS Side Discharge Before Conversion Selected Analog input ADiINn Precharge Broken wire R C Precharge control signal Chopper amp capacit...

Page 473: ...ed Scan mode Disconnection detection disabled 2900 3100 3300 3500 3700 3900 4100 4300 4500 4700 4900 5100 0 20 40 60 80 100 120 A D conversion cycle kHz Voltage on disconnected port mV Scan mode Disco...

Page 474: ...the reference voltage VREF and analog input voltages are sequentially compared bitwise beginning with the high order bit and the comparison result is set in the A D Successive Approximation Register...

Page 475: ...voltage comparison voltage R A D comparate result flag 1 Analog input voltage comparison voltage Note 1 During comparator mode the bits in this register correspond one for one to channels 0 15 Note T...

Page 476: ...Data Register 5 AD1DT5 Address H 0080 0A9A 10 bit A D1 Data Register 6 AD1DT6 Address H 0080 0A9C 10 bit A D1 Data Register 7 AD1DT7 Address H 0080 0A9E 10 bit A D1 Data Register 8 AD1DT8 Address H 0...

Page 477: ...ata Register 4 AD18DT4 Address H 0080 0AD9 8 bit A D1 Data Register 5 AD18DT5 Address H 0080 0ADB 8 bit A D1 Data Register 6 AD18DT6 Address H 0080 0ADD 8 bit A D1 Data Register 7 AD18DT7 Address H 00...

Page 478: ...xact and stable constant voltage power supply is connected to VREF Also make sure the analog circuit power supply and ground AVCC AVSS are separated from those of the digital circuit with sufficient n...

Page 479: ...er bits from bit 7 to bit 15 7 The value stored in the A D Successive Approximation Register by the time comparison for bit 15 has finished is held in it as the A D conversion result 11 3 Functional D...

Page 480: ...convert operation is executed continuously until scan operation is forcibly termi nated by setting the A D conversion stop bit Scan Mode Register 0 bit 6 to 1 11 3 3 Comparator Operation When compara...

Page 481: ...ous scan mode from when the A D Converter has finished A D conversion on a channel to when it starts A D conversion on the next channel The equation to calculate the A D conversion time is as follows...

Page 482: ...operation starts End dummy Completed Sampling time Figure 11 3 4 Conceptual Diagram of A D Conversion Time when Sample and Hold is Enabled Table 11 3 2 Conversion Clock Periods during Normal Sample a...

Page 483: ...single shot scan 298 n 1 190 n 1 Note 2 continuous scan mode Slow Comparator mode 47 47 Mode Double speed Single mode 173 101 n channel single shot scan 172 n 1 100 n 1 continuous scan mode Comparato...

Page 484: ...the absolute accuracy of 2 LSB it means that if the input voltage is 25 mV for example the output code expected for an A D converter with ideal characteristics is H 005 and the actual A D conversion...

Page 485: ...000 H 001 H 002 H 003 H 004 H 005 H 006 Output code hexadecimal 0 Analog input voltage mV Ideal A D conversion characteristics A D conversion characteristics with infinite resolution 5 10 15 20 25 30...

Page 486: ...is circuit lets the current flow into the GND and prevents it from wrapping around to the selected analog input That way the accuracy of the A D conversion result is prevented from being deterio rated...

Page 487: ...9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 10mA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9mA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8mA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7mA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6mA 0 0 0 0 0...

Page 488: ...1 shows the internal equivalent circuit of the A D Converter s analog input part To obtain accurate A D conversion results make sure the internal capacitor C2 of the A D conversion circuit is charged...

Page 489: ...024 5 mV The potential fluctuation of 0 1 LSB means a 0 5 mV fluctuation Vp is also obtained by the equation below The relationship between the capacitance division of C1 and C2 and the potential flu...

Page 490: ...w mode Normal speed 27 5BCLK when sample and Double speed 15 5BCLK hold enabled Fast mode Normal speed 11 5BCLK Double speed 7 5BCLK Comparator mode Slow mode Normal speed 27 5BCLK Double speed 15 5BC...

Page 491: ...11 11 46 A D Converters 32180 Group User s Manual Rev 1 0 This page is blank for reasons of layout 11 5 Precautions on Using A D Converters...

Page 492: ...ed Registers 12 3 Transmit Operation in CSIO Mode 12 4 Receive Operation in CSIO Mode 12 5 Precautions on Using CSIO Mode 12 6 Transmit Operation in UART Mode 12 7 Receive Operation in UART Mode 12 8...

Page 493: ...SIO mode UART mode 4 channels SIO0 SIO1 SIO4 SIO5 UART only 2 channels SIO2 SIO3 Clock During CSIO mode Internal clock or external clock as selected Note 1 During UART mode Internal clock only Transfe...

Page 494: ...r receive error SIO2 3 transmit receive interrupt group interrupt SIO4 transmit buffer empty or transmission finished SIO4 5 transmit receive interrupt group interrupt SIO4 reception finished or recei...

Page 495: ...To DMA7 RXD2 TXD2 Transmit Receive Control Circuit SIO2 Transmit Shift Register SIO2 Receive Shift Register To DMA7 DMA9 RXD3 TXD3 Transmit Receive Control Circuit SIO3 Transmit Shift Register SIO3 Re...

Page 496: ...r 12 14 S2TCNT S2MOD 12 15 H 0080 0132 SIO2 Transmit Buffer Register 12 18 S2TXB H 0080 0134 SIO2 Receive Buffer Register 12 19 S2RXB H 0080 0136 SIO2 Receive Control Register SIO2 Baud Rate Register...

Page 497: ...upt request enable bit it can also be used to inspect the operating status of peripheral functions In interrupt handling make sure that within the grouped interrupt request status only the status bit...

Page 498: ...To clear the Interrupt Request Status Register 0 ISTREG interrupt request status 1 ISTAT1 0x02 bit To clear an interrupt request status always be sure to write 1 to all other interrupt request status...

Page 499: ...SIO3 together comprise one interrupt group so do SIO4 and SIO5 The transmission finished interrupt is effective when the internal clock is selected in UART or CSIO mode 4 Notes on using transmit inte...

Page 500: ...requested R Note 1 SIO4 transmit interrupt request status bit 1 Interrupt requested 1 IRQR4 0 Interrupt not requested R Note 1 SIO4 receive interrupt request status bit 1 Interrupt requested 2 IRQT5...

Page 501: ...st enable bit 1 Enable interrupt request 14 T3EN 0 Mask disable interrupt request R W SIO3 transmit interrupt request enable bit 1 Enable interrupt request 15 R3EN 0 Mask disable interrupt request R W...

Page 502: ...e interrupt request source select bit 1 Receive error interrupt 6 ISR2 0 Reception finished interrupt R W SIO2 receive interrupt request source select bit 1 Receive error interrupt 7 ISR3 0 Reception...

Page 503: ...finished transmit shift buffer empty interrupt is selected A transmission finished interrupt request is generated when all of the data in the transmit shift register has been transferred Note Do not s...

Page 504: ...b6 F F SIO2 transmit buffer empty SIO2 transmission finished IST2 b2 F F SIO3 transmit buffer empty SIO3 transmission finished IST3 b3 F F SIO3 reception finished SIO3 receive error ISR3 b7 SI03SEL H...

Page 505: ...ission 1 CDIV baud rate generator count source select bits Bits 2 3 These bits select the count source for the Baud Rate Generator BRG Note If f BCLK is selected as the count source for the BRG care m...

Page 506: ...d 3 bit 8 is fixed to 0 in hardware This bit cannot be set to 1 in software to select clock synchronous serial I O Note 2 Has no effect when UART mode selected Note 3 Bits 12 15 have no effect during...

Page 507: ...en this bit is set to 1 a parity bit is added immediately after the data bits of the transmit data and the received data is checked for parity The parity bit added to the transmit data is automaticall...

Page 508: ...nd parity bits agrees with the parity attribute known as parity check b7 b6 b5 b4 b3 b2 b1 b0 PAR SP ST LSB MSB If the result of b7 b6 b0 PAR does not agree with the selected parity attribute a parity...

Page 509: ...r Registers are used to set transmit data These registers are a write only register and the contents of these registers cannot be read out Data must be LSB aligned when set in these registers Therefor...

Page 510: ...s are used to store the received data When the serial I O has finished receiving data the content of the SIO Receive Shift Register is transferred to the SIO Receive Buffer Register These registers ar...

Page 511: ...5 6 b7 b0 PTY FLM ERS RSTAT RFIN REN OVR 0 0 0 0 0 0 0 0 After reset H 00 b Bit Name Function R W 0 No function assigned Fix to 0 0 0 1 RSTAT 0 Reception stopped R Receive status bit 1 Reception in p...

Page 512: ...ive operation stops if the Receive Enable bit is cleared to 0 while receiving data 4 OVR Overrun Error bit Bit 4 Set condition This bit is set to 1 when all bits of the next received data have been se...

Page 513: ...earing the SIO Receive Control Register REN Receive Enable bit However if an overrun error occurs this bit cannot be cleared by reading out the lower byte of the Receive Buffer Register In this case c...

Page 514: ...during transmit receive operation takes effect in the next cycle after the BRG counter has finished counting When using the internal clock to output the SCLKO signal in CSIO mode the serial I O divide...

Page 515: ...selected from 1 8 32 or 256 by using the CDIV baud rate generator count source select bits Transmit Control Register bits 2 3 The Baud Rate Generator divides the clock divider output by baud rate regi...

Page 516: ...interrupt related registers Select the source of transmit interrupt request transmit buffer empty or transmission finished SIO Interrupt Request Source Select Register Enable or disable transmit inter...

Page 517: ...Mbps Note 3 Transmission finished interrupts are effective only when the internal clock is selected Set the register to CSIO mode Select the internal or external clock When using the DMAC Set DMAC Wh...

Page 518: ...smit status bit is set to 1 at the time data is set in the lower byte of the SIO Transmit Buffer Register When transmission starts the serial I O sends data following the procedure described below Tra...

Page 519: ...en the TEN Transmit Enable bit is set to 1 disabled enabled while the transmit buffer empty interrupt has been enabled 2 Transmission finished interrupt If the transmission finished interrupt was sele...

Page 520: ...transmit buffer empty bit to 1 Transmit data Y Successive transmission Transmit conditions met Transmit conditions met Y N N Clear the transmit status bit to 0 Transmit DMA transfer request Transmit i...

Page 521: ...e 7 A transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which transmission of the transmit shift register data has finished or when the tra...

Page 522: ...ished interrupt request is generated by a falling edge of the internal transfer clock pulse at which transmission of the transmit shift register data has finished or when the transmit enable bit is cl...

Page 523: ...Control Register Select the clock divider s divide by ratio when internal clock selected 3 Setting SIO Baud Rate Register When the internal clock is selected set a baud rate generator value See Sectio...

Page 524: ...sing the DMAC Set DMAC When using interrupts Set Interrupt Controller Select the source of receive interrupt request Set SIO interrupt related registers Divide by ratio H 00 to H FF Note 2 Set SIO Bau...

Page 525: ...LSB first synchronously with the receive shift clock 12 4 3 Processing at End of CSIO Reception When data reception finishes the following operation is automatically performed in hardware 1 When rece...

Page 526: ...data in the receive buffer register Set the SIO Receive Control Register overrun error and receive error sum bits to 1 Receive conditions met Overrun error Y Y N N End of CSIO receive operation CSIO...

Page 527: ...fore the previous data is not read out an overrun error occurs and the subse quent received data are not transferred to the receive buffer register Before receive operation can be restarted the receiv...

Page 528: ...it side CSIO on receive side SCLKO TXD SCLKI RXD Internal clock selected External clock selected Receive clock SCLKO Set Receive enable bit RXD Receive status bit Reception finished bit SIO receive in...

Page 529: ...ption finished interrupt is enabled Note 3 When receive error interrupt is enabled Note 4 The receive enable bit is cleared Note 5 The Interrupt Controller s IVECT register is read or the SIO Receive...

Page 530: ...the SIO Transmit Buffer Register before a transmit operation on the transmitter side starts Transmission reception using DMA To transmit receive data in DMA request mode enable the DMAC to accept tran...

Page 531: ...ift clock The clock divider s divide by value is selected from 1 8 32 or 256 by using the SIO Transmit Control Regis ter CDIV baud rate generator count source select bits bits 2 3 Note 1 The Baud Rate...

Page 532: ...led immediately following the parity bit The stop bit can be chosen to be one bit or two bits long Figure 12 6 2 Selectable Data Formats during UART Mode ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP SP ST b7 b6...

Page 533: ...d Rate Register Set a baud rate generator value See Section 12 6 1 Setting the UART Baud Rate 4 Setting SIO interrupt related registers Select the source of transmit interrupt request transmit buffer...

Page 534: ...sters Set Interrupt Controller Set SIO interrupt related registers Divide by ratio H 00 to H FF Note 1 Set SIO Baud Rate Register Select the clock divider divide by ratio Set SIO Transmit Control Regi...

Page 535: ...sion Once data has been transferred from the transmit buffer register to the transmit shift register the next data can be written to the transmit buffer register even when the serial I O has not finis...

Page 536: ...Interrupt Request Source Select Register End of UART transmit operation UART transmit operation starts 2 Transmission finished interrupt If the transmission finished interrupt was selected using the S...

Page 537: ...uffer empty interrupt is selected When transmission finished interrupt is selected Note 1 Changes of the Interrupt Controller s SIO Transmit Interrupt Control Register interrupt request bit Note 2 Whe...

Page 538: ...ted Note 4 When transmit buffer empty interrupt is selected When transmission finished interrupt is selected Write to the transmit buffer register Note 1 Changes of the Interrupt Controller s SIO Tran...

Page 539: ...lock divider s divide by ratio 3 Setting SIO Baud Rate Register Set a baud rate generator value See Section 12 6 1 Setting the UART Baud Rate 4 Setting SIO interrupt related registers Select the sourc...

Page 540: ...ntroller s SIO Receive Interrupt Control Register Set SIO interrupt related registers Select the source of receive interrupt request Enable or disable receive interrupt requests Set SIO Baud Rate Regi...

Page 541: ...in hardware 1 When reception is completed normally The reception finished receive buffer full bit is set to 1 Notes An interrupt request is generated if the reception finished receive buffer full inte...

Page 542: ...Shift Register to the SIO Receive Buffer Register Set the SIO Receive Control Register reception finished bit to 1 Set the receive status bit to 1 Overrun error Parity error or framing error Receive...

Page 543: ...nsfer can also be requested at the same time Note 3 The Interrupt Controller s IVECT register is read or the SIO Receive Interrupt Control Register interrupt request bit cleared Receive enable bit SIO...

Page 544: ...errupt Controller s IVECT register is read or the SIO Receive Interrupt Control Register interrupt request bit cleared Receive enable bit SIO Receive Control Register b7 ST SP SP Reception finished bi...

Page 545: ...gnal is high before being determined to be the start bit the CPU starts hunting the falling edge of the received signal again Because the start bit is sampled synchronously with the internal BRG outpu...

Page 546: ...respectively That way a BRG output clock divided by 2 can be output from the SCLKO pin Note This clock is output not just during data transfer 12 8 Fixed Period Clock Output Function Figure 12 8 1 Ex...

Page 547: ...all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register i e an overrun error occurred the received data is not stored in t...

Page 548: ...Module 13 2 CAN Module Related Registers 13 3 CAN Protocol 13 4 Initializing the CAN Module 13 5 Transmitting Data Frames 13 6 Receiving Data Frames 13 7 Transmitting Remote Frames 13 8 Receiving Rem...

Page 549: ...atically sending a data frame response function Timestamp function This function is implemented using a 16 bit counter The count period is derived from the CAN bus bit period by dividing it by 1 2 3 o...

Page 550: ...receive error interrupt CAN1 error passive CAN1 transmit receive error interrupt CAN0 bus off CAN0 transmit receive error interrupt CAN1 bus off CAN1 transmit receive error interrupt CAN0 single shot...

Page 551: ...47 Use inhibited area H 0080 1028 CAN0 Global Mask Register Standard ID0 CAN0 Global Mask Register Standard ID1 13 48 C0GMSKS0 C0GMSKS1 H 0080 102A CAN0 Global Mask Register Extended ID0 CAN0 Global...

Page 552: ...H 0080 110A CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 13 67 C0MSL0DT4 C0MSL0DT5 13 68 H 0080 110C CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 13 69 C0MSL0DT6 C0MSL0DT7 13 70 H 0...

Page 553: ...13 67 C0MSL4DT4 C0MSL4DT5 13 68 H 0080 114C CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 13 69 C0MSL4DT6 C0MSL4DT7 13 70 H 0080 114E CAN0 Message Slot 4 Timestamp 13 71 C0MSL4TSP H 0080 1150...

Page 554: ...C0MSL8DT5 13 68 H 0080 118C CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 13 69 C0MSL8DT6 C0MSL8DT7 13 70 H 0080 118E CAN0 Message Slot 8 Timestamp 13 71 C0MSL8TSP H 0080 1190 CAN0 Message Sl...

Page 555: ...MSL12DT4 C0MSL12DT5 13 68 H 0080 11CC CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 13 69 C0MSL12DT6 C0MSL12DT7 13 70 H 0080 11CE CAN0 Message Slot 12 Timestamp 13 71 C0MSL12TSP H 0080 11D0...

Page 556: ...EC CAN1TEC H 0080 140C CAN1 Slot Interrupt Request Status Register 13 29 CAN1SLIST H 0080 140E Use inhibited area H 0080 1410 CAN1 Slot Interrupt Request Enable Register 13 30 CAN1SLIEN H 0080 1412 Us...

Page 557: ...ibited area H 0080 1500 CAN1 Message Slot 0 Standard ID0 CAN1 Message Slot 0 Standard ID1 13 57 C1MSL0SID0 C1MSL0SID1 13 58 H 0080 1502 CAN1 Message Slot 0 Extended ID0 CAN1 Message Slot 0 Extended ID...

Page 558: ...13 67 C1MSL3DT4 C1MSL3DT5 13 68 H 0080 153C CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 13 69 C1MSL3DT6 C1MSL3DT7 13 70 H 0080 153E CAN1 Message Slot 3 Timestamp 13 71 C1MSL3TSP H 0080 1540...

Page 559: ...13 67 C1MSL7DT4 C1MSL7DT5 13 68 H 0080 157C CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 13 69 C1MSL7DT6 C1MSL7DT7 13 70 H 0080 157E CAN1 Message Slot 7 Timestamp 13 71 C1MSL7TSP H 0080 1580...

Page 560: ...1MSL11DT4 C1MSL11DT5 13 68 H 0080 15BC CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 13 69 C1MSL11DT6 C1MSL11DT7 13 70 H 0080 15BE CAN1 Message Slot 11 Timestamp 13 71 C1MSL11TSP H 0080 15C0...

Page 561: ...1MSL14DT4 C1MSL14DT5 13 68 H 0080 15EC CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 13 69 C1MSL14DT6 C1MSL14DT7 13 70 H 0080 15EE CAN1 Message Slot 14 Timestamp 13 71 C1MSL14TSP H 0080 15F0...

Page 562: ...eration R Note 1 Timestamp counter reset bit 1 Initialize count to H 0000 6 7 TSP 00 Select CAN bus bit clock R W Timestamp prescaler bit 01 Select CAN bus bit clock divided by 2 10 Select CAN bus bit...

Page 563: ...tocol control unit is reset after setting the FRST bit Notes In order for CAN communication to start the FRST and RST bits must be cleared to 0 If the FRST bit is set to 1 during communication the CTX...

Page 564: ...frame can be received Notes ACK is not returned for the transmit frame Do not change settings of the LBM bit while CAN is operating CAN Status Register CRS bit 0 7 RST CAN Reset bit Bit 15 When the RS...

Page 565: ...red 4 BCS 0 Normal mode R BasicCAN mode status bit 1 BasicCAN mode 5 No function assigned Fix to 0 0 0 6 LBS 0 Normal mode R Loopback status bit 1 Loopback mode 7 CRS 0 Operating R CAN reset status bi...

Page 566: ...error passive state 3 CBS CAN Bus Error bit Bit 3 Set condition This bit is set to 1 when an error is detected on the CAN bus Clear condition This bit is cleared when the CAN module finished sending...

Page 567: ...n This bit is cleared when the CAN module starts operating as a receive node or enters a bus idle state 9 RSC Reception Completed Status bit Bit 10 Set condition This bit is set to 1 when the CAN modu...

Page 568: ...bit 4 FFE4 slot 4 extended format bit 5 FFE5 slot 5 extended format bit 6 FFE6 slot 6 extended format bit 7 FFE7 slot 7 extended format bit 8 FFE8 slot 8 extended format bit 9 FFE9 slot 9 extended fo...

Page 569: ...011 Phase Segment1 4Tq 100 Phase Segment1 5Tq 101 Phase Segment1 6Tq 110 Phase Segment1 7Tq 111 Phase Segment1 8Tq 8 10 PRB 000 Propagation Segment 1Tq R W Propagation Segment setting bit 001 Propaga...

Page 570: ...y circuit from three sampled values each sampled 2 Tq s before 1 Tq before and at the end of Phase Segment1 Table 13 2 1 Typical Settings of Bit Timing when CPU Clock 80 MHz Baud Rate BRP Set Value Tq...

Page 571: ...the CAN module finishes sending or receiving it captures the count register value and stores the value in a message slot The counter is made to start counting by clearing the CAN Control Register CANn...

Page 572: ...eceiving normally when REC 128 error passive REC is set to 127 During a bus off state an undefined value is stored in this register The count is reset to H 00 upon returning to an error active state C...

Page 573: ...R W 0 7 BRP Baud rate prescaler value R W This register sets the Tq period of CAN The CAN baud rate is determined by Tq period number of Tq s in one bit Tq period BRP 1 CPU clock 2 CAN transfer baud r...

Page 574: ...also be used to inspect the operating status of peripheral functions In interrupt handling make sure that within the grouped interrupt request status only the status bit for the interrupt request that...

Page 575: ...To clear the Interrupt Request Status Register 0 ISTREG interrupt request status 1 ISTAT1 0x02 bit To clear an interrupt request status always be sure to write 1 to all other interrupt request status...

Page 576: ...B15 slot 15 interrupt request status bit Note 1 Only writing 0 is effective Writing 1 has no effect the bit retains the status it had before the write When using CAN interrupts this register helps to...

Page 577: ...bit 5 IRB5 slot 5 interrupt request enable bit 6 IRB6 slot 6 interrupt request enable bit 7 IRB7 slot 7 interrupt request enable bit 8 IRB8 slot 8 interrupt request enable bit 9 IRB9 slot 9 interrupt...

Page 578: ...ts if the interrupt request sources are associated with errors this register helps to know which source generated the interrupt 1 BEIS CAN Bus Error Interrupt Request Status bit Bit 5 The BEIS bit is...

Page 579: ...N Bus off interrupt request enable bit 1 BEIEN CAN Bus Error Interrupt Request Enable bit Bit 5 The BEIEN bit enables or disables the interrupt requests to be generated when CAN bus errors occurred CA...

Page 580: ...request status 8 SSIST8 Slot 8 single shot interrupt request status 9 SSIST9 Slot 9 single shot interrupt request status 10 SSIST10 Slot 10 single shot interrupt request status 11 SSIST11 Slot 11 sing...

Page 581: ...single shot interrupt request enable bit 6 SSIEN6 Slot 6 single shot interrupt request enable bit 7 SSIEN7 Slot 7 single shot interrupt request enable bit 8 SSIEN8 Slot 8 single shot interrupt reques...

Page 582: ...Slot 1 transmission reception completed Slot 2 transmission reception completed Slot 3 transmission reception completed Slot 4 transmission reception completed Slot 5 transmission reception completed...

Page 583: ...reception completed Slot 9 transmission reception completed Slot 10 transmission reception completed Slot 11 transmission reception completed Slot 12 transmission reception completed Slot 13 transmis...

Page 584: ...it Receive Error Interrupt Requests 3 5 F F F F EOIEN EOIS F F F F EPIEN EPIS F F F F BEIEN BEIS b15 b7 b14 b6 b13 b5 Data bus CAN bus error occurs Go to error passive state Go to bus off state To the...

Page 585: ...or occurs Slot 1 arbitration lost transmit error occurs Slot 2 arbitration lost transmit error occurs Slot 3 arbitration lost transmit error occurs Slot 4 arbitration lost transmit error occurs Slot 5...

Page 586: ...F SSIEN8 SSIST8 b15 b15 b14 b14 b13 b13 b12 b12 b11 b11 b10 b10 b9 b9 b8 b8 Data bus Slot 8 arbitration lost transmit error occurs Slot 9 arbitration lost transmit error occurs Slot 10 arbitration los...

Page 587: ...b5 b5 b4 b4 b3 b3 b2 b2 b1 b1 b0 b0 Data bus Slot 0 transmission reception completed Slot 1 transmission reception completed Slot 2 transmission reception completed Slot 3 transmission reception comp...

Page 588: ...reception completed Slot 9 transmission reception completed Slot 10 transmission reception completed Slot 11 transmission reception completed Slot 12 transmission reception completed Slot 13 transmis...

Page 589: ...mit Receive Error Interrupt Requests 3 5 F F F F EOIEN EOIS F F F F EPIEN EPIS F F F F BEIEN BEIS b15 b7 b14 b6 b13 b5 Data bus CAN bus error occurs Go to error passive state Go to bus off state To th...

Page 590: ...b6 b6 b5 b5 b4 b4 b3 b3 b2 b2 b1 b1 b0 b0 Data bus Slot 0 arbitration lost transmit error occurs Slot 1 arbitration lost transmit error occurs Slot 2 arbitration lost transmit error occurs Slot 3 arbi...

Page 591: ...F SSIEN8 SSIST8 b15 b15 b14 b14 b13 b13 b12 b12 b11 b11 b10 b10 b9 b9 b8 b8 Data bus Slot 8 arbitration lost transmit error occurs Slot 9 arbitration lost transmit error occurs Slot 10 arbitration los...

Page 592: ...detected This register indicates error information when a communication error occurred 1 ETR Transmit Receive Error Judgement bit Bit 2 This bit is set to 1 if the CAN module was operating as a recep...

Page 593: ...n mode Normal transmit receive operations can be performed Bus monitor mode Only receive operation is performed During bus monitor mode the CTX output is fixed high and neither ACK nor an error frame...

Page 594: ...reception in slot 14 is completed Notes If slot 14 has been set for remote frame transmission a DMA transfer request is generated when remote frame transmission is completed as well as when data fram...

Page 595: ...AS1 Address H 0080 1431 CAN1 Local Mask Register B Standard ID1 C1LMSKBS1 Address H 0080 1439 9 10 11 12 13 14 b15 b8 SID6M SID5M SID7M SID8M SID9M SID10M 0 0 0 0 0 0 0 0 After reset H 00 b Bit Name F...

Page 596: ...Bit Name Function R W 0 3 No function assigned Fix to 0 0 0 4 7 EID0M EID3M 0 ID not checked R W Extended mask ID0 extended mask ID3 1 ID checked CAN0 Global Mask Register Extended ID1 C0GMSKE1 Addres...

Page 597: ...ed Three mask registers are used in acceptance filtering global mask register local mask register A and local mask register B The global mask register is used for message slots 0 13 while local mask r...

Page 598: ...register set value 0 The received message and slot IDs are not checked for matching and handled as Don t care masked 1 The received message and slot IDs are checked for matching Mask bit value Accepta...

Page 599: ...SSCNT7 Slot 7 single shot mode bit 8 SSCNT8 Slot 8 single shot mode bit 9 SSCNT9 Slot 9 single shot mode bit 10 SSCNT10 Slot 10 single shot mode bit 11 SSCNT11 Slot 11 single shot mode bit 12 SSCNT12...

Page 600: ...L13CNT Address H 0080 105D CAN0 Message Slot 14 Control Register C0MSL14CNT Address H 0080 105E CAN0 Message Slot 15 Control Register C0MSL15CNT Address H 0080 105F CAN1 Message Slot 0 Control Registe...

Page 601: ...mission idle 1 Transmit request accepted During a receive slot 0 Reception idle 1 Storing received data 7 TRFIN During a transmit slot R Note 1 Transmission reception completed 0 Not transmitted yet 1...

Page 602: ...to be performed after receiving a remote frame If this bit is set to 0 the message slot automati cally changes to a transmit slot after receiving a remote frame and transmits the data set in it as a...

Page 603: ...receiving When set for a transmit slot This bit is set to 1 when the CAN module finished sending the data stored in the message slot This bit is cleared by writing 0 in software However it cannot be...

Page 604: ...ID0 Address H 0080 11F0 CAN1 Message Slot 0 Standard ID0 C1MSL0SID0 Address H 0080 1500 CAN1 Message Slot 1 Standard ID0 C1MSL1SID0 Address H 0080 1510 CAN1 Message Slot 2 Standard ID0 C1MSL2SID0 Addr...

Page 605: ...F1 CAN1 Message Slot 0 Standard ID1 C1MSL0SID1 Address H 0080 1501 CAN1 Message Slot 1 Standard ID1 C1MSL1SID1 Address H 0080 1511 CAN1 Message Slot 2 Standard ID1 C1MSL2SID1 Address H 0080 1521 CAN1...

Page 606: ...1502 CAN1 Message Slot 1 Extended ID0 C1MSL1EID0 Address H 0080 1512 CAN1 Message Slot 2 Extended ID0 C1MSL2EID0 Address H 0080 1522 CAN1 Message Slot 3 Extended ID0 C1MSL3EID0 Address H 0080 1532 CAN...

Page 607: ...80 1503 CAN1 Message Slot 1 Extended ID1 C1MSL1EID1 Address H 0080 1513 CAN1 Message Slot 2 Extended ID1 C1MSL2EID1 Address H 0080 1523 CAN1 Message Slot 3 Extended ID1 C1MSL3EID1 Address H 0080 1533...

Page 608: ...essage Slot 1 Extended ID2 C1MSL1EID2 Address H 0080 1514 CAN1 Message Slot 2 Extended ID2 C1MSL2EID2 Address H 0080 1524 CAN1 Message Slot 3 Extended ID2 C1MSL3EID2 Address H 0080 1534 CAN1 Message S...

Page 609: ...gth Register C1MSL1DLC Address H 0080 1515 CAN1 Message Slot 2 Data Length Register C1MSL2DLC Address H 0080 1525 CAN1 Message Slot 3 Data Length Register C1MSL3DLC Address H 0080 1535 CAN1 Message Sl...

Page 610: ...e Slot 2 Data 0 C1MSL2DT0 Address H 0080 1526 CAN1 Message Slot 3 Data 0 C1MSL3DT0 Address H 0080 1536 CAN1 Message Slot 4 Data 0 C1MSL4DT0 Address H 0080 1546 CAN1 Message Slot 5 Data 0 C1MSL5DT0 Add...

Page 611: ...Message Slot 1 Data 1 C1MSL1DT1 Address H 0080 1517 CAN1 Message Slot 2 Data 1 C1MSL2DT1 Address H 0080 1527 CAN1 Message Slot 3 Data 1 C1MSL3DT1 Address H 0080 1537 CAN1 Message Slot 4 Data 1 C1MSL4D...

Page 612: ...AN1 Message Slot 1 Data 2 C1MSL1DT2 Address H 0080 1518 CAN1 Message Slot 2 Data 2 C1MSL2DT2 Address H 0080 1528 CAN1 Message Slot 3 Data 2 C1MSL3DT2 Address H 0080 1538 CAN1 Message Slot 4 Data 2 C1M...

Page 613: ...Message Slot 1 Data 3 C1MSL1DT3 Address H 0080 1519 CAN1 Message Slot 2 Data 3 C1MSL2DT3 Address H 0080 1529 CAN1 Message Slot 3 Data 3 C1MSL3DT3 Address H 0080 1539 CAN1 Message Slot 4 Data 3 C1MSL4D...

Page 614: ...AN1 Message Slot 1 Data 4 C1MSL1DT4 Address H 0080 151A CAN1 Message Slot 2 Data 4 C1MSL2DT4 Address H 0080 152A CAN1 Message Slot 3 Data 4 C1MSL3DT4 Address H 0080 153A CAN1 Message Slot 4 Data 4 C1M...

Page 615: ...Message Slot 1 Data 5 C1MSL1DT5 Address H 0080 151B CAN1 Message Slot 2 Data 5 C1MSL2DT5 Address H 0080 152B CAN1 Message Slot 3 Data 5 C1MSL3DT5 Address H 0080 153B CAN1 Message Slot 4 Data 5 C1MSL4D...

Page 616: ...AN1 Message Slot 1 Data 6 C1MSL1DT6 Address H 0080 151C CAN1 Message Slot 2 Data 6 C1MSL2DT6 Address H 0080 152C CAN1 Message Slot 3 Data 6 C1MSL3DT6 Address H 0080 153C CAN1 Message Slot 4 Data 6 C1M...

Page 617: ...Message Slot 1 Data 7 C1MSL1DT7 Address H 0080 151D CAN1 Message Slot 2 Data 7 C1MSL2DT7 Address H 0080 152D CAN1 Message Slot 3 Data 7 C1MSL3DT7 Address H 0080 153D CAN1 Message Slot 4 Data 7 C1MSL4...

Page 618: ...ss H 0080 150E CAN1 Message Slot 1 Timestamp C1MSL1TSP Address H 0080 151E CAN1 Message Slot 2 Timestamp C1MSL2TSP Address H 0080 152E CAN1 Message Slot 3 Timestamp C1MSL3TSP Address H 0080 153E CAN1...

Page 619: ...d frame Frames are separated from each other by an interframe space 13 3 CAN Protocol SOF Arbitration field Control field Data field CRC field ACK field EOF 11 1 6 0 64 16 2 7 11 1 1 1 18 6 0 64 16 2...

Page 620: ...e of an error passive state 3 8 0 SOF of the next frame Bus idle Intermission Note The number in each field denotes the number of bits 1 1 13 3 2 Data Formats during CAN Transmission Reception Figure...

Page 621: ...r flag is transmitted 3 Bus off state This is a state where a very large number of errors have occurred CAN communication with other nodes cannot be performed until the CAN module returns to an error...

Page 622: ...ation Register and CAN Baud Rate Prescaler set the bit timing and the number of times the CAN bus is sampled 1 Setting the bit timing Determine the period Tq that is the base of bit timing the configu...

Page 623: ...ance filtering of received messages 6 Settings for use in BasicCAN mode Set the CAN Extended ID Register IDE14 and IDE15 bits We recommend setting the same value in these bits Set IDs in message slots...

Page 624: ...cCAN mode Set the CAN Extended ID Register Set IDs in message slots 14 and 15 Set the Message Slot Control Register Release the CAN module from reset Set the CAN Error Interrupt Request Enable Registe...

Page 625: ...AT Transmit Receive Status bit to see that transmission reception has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot Therefore wait until the bit is...

Page 626: ...ng a transmit frame The CAN module checks slots which have transmit requests including remote frame transmit slots every intermission to determine the frame to transmit If two or more transmit slots e...

Page 627: ...nsmission aborted Transmit request accepted Transmission aborted Transmission completed Transmission aborted Transmission completed Wait for transmission B 0000 0010 Lost in CAN bus arbitration or a C...

Page 628: ...Register that has just been initialized and check the TRSTAT Transmit Receive Status bit to see that reception has stopped and remains idle If this bit 1 it means that the CAN module is accessing the...

Page 629: ...describes data frame receive operation The operations described below are automatically per formed in hardware 1 Acceptance filtering When the CAN module finished receiving data it starts searching fo...

Page 630: ...trol Register s TRSTAT Transmit Receive Status bit and TRFIN Transmit Receive Finished bit to 1 while at the same time writing the received data to the message slot If the TRFIN Transmit Receive Finis...

Page 631: ...Notes If message lost check by the ML bit is needed write H 4E to clear the TRFIN bit If the TRFIN bit was cleared by writing H 4E H 40 or H 00 it is possible that new data will be stored in the slot...

Page 632: ...Data Frames Reading out received data Clear the TRFIN bit to 0 Read out from the message slot Finished reading out received data Read the CAN Message Slot Control Register TRFIN bit 0 YES NO Write H 4...

Page 633: ...TRSTAT Transmit Receive Status bit to see that transmission reception has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot Therefore wait until the bi...

Page 634: ...operations described below are automatically performed in hardware 1 Setting the RA Remote Active bit The RA Remote Active bit is set to 1 at the same time H A0 Transmit Request Remote is written to t...

Page 635: ...received frame is a data frame The receive ID and the slot ID are identical assuming the ID Mask Register bits set to 0 are Don t care The standard and extended frame types are the same Note In Basic...

Page 636: ...frame Figure 13 7 2 Operation of the CAN Message Slot Control Register during Remote Frame Transmission 13 7 3 Reading Out Received Data Frames when Set for Remote Frame Transmission The following sh...

Page 637: ...out a message from the message slot 3 Checking the TRFIN Transmit Receive Finished bit Read the CAN Message Slot Control Register to check the TRFIN Transmit Receive Finished bit 1 If TRFIN Transmit...

Page 638: ...bit is cleared to 0 3 Setting the receive ID Set the desired receive ID in the message slot 4 Setting the Extended ID Register Set the corresponding bit in the Extended ID Register to 0 if a standard...

Page 639: ...he conditions for receiving the received message sequentially from slot 0 up to slot 15 The following shows receive condi tions for the slots that have been set for data frame reception Conditions The...

Page 640: ...er receiving a remote frame the slot automatically changes to a data frame transmit slot and performs the transmit operation described below In this case the transmitted data conforms to the ID and DL...

Page 641: ...B 0000 1010 B 0000 0000 Wait for reception Send a data frame Clear the receive request Finished sending a data frame Finished sending a data frame Send a data frame Finished storing the received data...

Page 642: ...ransmission Figure 13 9 1 Opertion Flow when Aborting Remote Frame Transmission 2 When canceling remote frame receiving Figure 13 9 2 Opertion Flow when Canceling Remote Frame Receiving RA Remote Acti...

Page 643: ...13 13 96 32180 Group User s Manual Rev 1 0 CAN MODULE 13 9 Precautions about CAN Module This page is blank for reasons of layout...

Page 644: ...CHAPTER 14 REAL TIME DEBUGGER RTD 14 1 Outline of the Real Time Debugger RTD 14 2 Pin Functions of the RTD 14 3 Functional Description of the RTD 14 4 Typical Connection with the Host...

Page 645: ...ck synchronous serial I O Generation of transfer clock Generated by external host RAM access area Entire area of the internal RAM controlled by A16 A29 Transmit receive data length 32 bits fixed Bit t...

Page 646: ...nchronously with the beginning clock edge of the output data word The width of this pulse indicates the type of instruction or data the RTD has received 1 clock period VER continuous monitor command 1...

Page 647: ...it Bits 16 18 are effective for the command specified Note 2 The RCV command must always be transmitted twice in succession Note 3 For the RCV command all bits not just 16 19 i e bits 0 15 and bits 20...

Page 648: ...D A2 Note An Specified address D An Data at specified address An RTDCLK RTDRXD RTDTXD RTDACK 32 clock periods 32 clock periods 32 clock periods 2 clock periods Figure 14 3 2 Operation of the RDR Comm...

Page 649: ...or read from the internal RAM The two low order address bits specified by a command are ignored Data are written to the internal RAM in 32 bit units The external host should transmit the command and a...

Page 650: ...32 clock periods 32 clock periods Figure 14 3 7 Operation of the VER Continuous Monitor Command 14 3 5 Operation of VEI Interrupt Request When the VEI interrupt request command is issued the RTD gener...

Page 651: ...upt D A1 Read value Note 1 WRR command can also be used Notes An Specified address D An Data at specified address An 32 clock periods 32 clock periods 32 clock periods Note 1 D A1 Read value Figure 14...

Page 652: ...r Setting a Specified Address when Using the RTD In the Real Time Debugger RTD the low order 16 bit addresses of the internal RAM can be specified Be cause the internal RAM is located in a 48 KB area...

Page 653: ...Pin Name Status RTDACK High level output RTDTXD High level output The first command transfer to the RTD after being reset is initiated by transferring data to the RTDRXD pin synchronously with the fal...

Page 654: ...bit units data is transferred separately in four operations 8 bits at a time The RTDACK signal is used to verify that communication is performed normally The RTDACK signal goes low after a command is...

Page 655: ...14 14 12 REAL TIME DEBUGGER RTD 32180 Group User s Manual Rev 1 0 14 4 Typical Connection with the Host This page is blank for reasons of layout...

Page 656: ...1 Outline of the External Bus Interface 15 2 External Bus Interface Related Registers 15 3 Read Write Operations 15 4 Bus Arbitration 15 5 Typical Connection of External Extension Memory 15 6 Example...

Page 657: ...must be set for chip select using the corresponding Port Operation Mode Register as necessary 3 Read strobe RD Output during an external read cycle this signal indicates the timing at which to read d...

Page 658: ...y 8 Wait WAIT When the 32180 started an external bus cycle it automatically inserts wait states while the WAIT input signal is asserted For details see Chapter 16 Wait Controller When not using the WA...

Page 659: ...ss signal pins at any time irrespective of the CPU operation mode Ports P41 P43 always function as external access signal pins during external extension and processor modes P0 Operation Mode Register...

Page 660: ...0 P17 R W Port P17 operation mode bit 1 DB15 Note Settings of the P1 Operation Mode Register are effective only when the CPU is operating in external extension mode P2 Operation Mode Register P2MOD Ad...

Page 661: ...ort P35 operation mode bit 1 A20 14 P36MD 0 P36 R W Port P36 operation mode bit 1 A21 15 P37MD 0 P37 R W Port P37 operation mode bit 1 A22 Note Settings of the P3 Operation Mode Register are effective...

Page 662: ...ode bit 1 RTDCLK P22 Operation Mode Register P22MOD Address H 0080 0756 1 2 3 4 5 6 b7 b0 P220MD P222MD P223MD P224MD P225MD P226MD P227MD 0 0 0 0 0 0 0 0 After reset H 00 b Bit Name Function R W 0 P2...

Page 663: ...eral Output Select Register because the A11 and CS2 pins and the A12 and CS3 pins are shared P22 Peripheral Output Select Register P22SMOD Address H 0080 0776 1 2 3 4 5 6 b7 b0 P224 SMD P225 SMD 0 0 0...

Page 664: ...us Mode Control bit BUSMOD 1 the byte enable signal is output separately for each byte area Signals RD BHE BLE WR and WAIT can be used In a WAIT control circuit configuration because BCLK output is no...

Page 665: ...nal output for the byte position to which to write is asserted low as data is written to the bus When an external bus cycle starts wait states are inserted as long as the WAIT signal is low Unless nec...

Page 666: ...t Control Register see Section 16 2 1 CS Area Wait Control Registers Note When zero wait state is selected assertion of WAIT is not accepted DB0 DB15 WAIT Read 1 cycle Don t Care BCLK A11 A30 CS0 CS3...

Page 667: ...Register see Section 16 2 1 CS Area Wait Control Registers Note Circles in the above diagram denote the sampling timing L Internal 2 wait states External 1 wait state Don t Care H Don t Care Write 4...

Page 668: ...or BLE signal output for the byte position to which to write is asserted low with data written to the necessary byte position When an external bus cycle starts wait states are inserted as long as the...

Page 669: ...t Control Register see Section 16 2 1 CS Area Wait Control Registers Notes When zero wait state is selected assertion of WAIT is not accepted BCLK is not output Read 1 cycle WR Don t Care BCLK A11 A30...

Page 670: ...Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram denote the sampling timing BCLK is not output H Internal 2 wait states External 1 wait state WR L Don t Care Write 4 cy...

Page 671: ...hold state and return to normal operating state release the HREQ signal back high Figure 15 4 1 Bus Arbitration Timing DB0 DB15 BCLK Bus cycle Idle Go to hold state Hold state Return Next bus cycle N...

Page 672: ...rating state release the HREQ signal back high Figure 15 4 2 Bus Arbitration Timing DB0 DB15 BCLK Note 1 For details about the Bus Mode Control Register see Section 15 2 3 Bus Mode Control Register No...

Page 673: ...t 0 Note The address and data are connected in such a way that pin 0 is the MSB and pin 15 is the LSB When connecting external extension memory connections of the MSB and LSB sides must be reversed Me...

Page 674: ...a are connected in such a way that pin 0 is the MSB and pin 15 is the LSB When connecting external extension memory connections of the MSB and LSB sides must be reversed SRAM M32180F8 A11 1024KB A30 D...

Page 675: ...ly used as port WAIT is used only when seven or more wait states are needed H 0000 0000 H 0040 0000 H 0020 0000 H 000F FFFF H 0010 0000 External memory area 2MB 1M CS0 area 2M CS1 area SRAM 8 bit memo...

Page 676: ...VDDE VCC BUS Bus Connected at 5 V 5V 5V Memory 5V VCC OSC VCC M32R ECU Port Figure 15 6 1 When Both Port and Memory are Connected at 5 V 2 When ports and memory are connected at 3 3 V and 5 V respecti...

Page 677: ...and memory are connected at 5 V and 3 3 V respectively Ports and memory can be connected with external circuits via a 5 V interface directly as is and a 3 3 V interface respectively VCCE VDDE VCC BUS...

Page 678: ...CHAPTER 16 WAIT CONTROLLER 16 1 Outline of the Wait Controller 16 2 Wait Controller Related Registers 16 3 Typical Operation of the Wait Controller...

Page 679: ...ls CS0 to CS3 are output each corre sponding to one of the four extended external areas referred to as CS0 through CS3 16 1 Outline of the Wait Controller H 0000 0000 H 0010 0000 H 000F FFFF H 0020 00...

Page 680: ...priority processor mode CS1 area H 0020 0000 to H 003F FFFF Zero to 7 wait states set by software external extension and any number of wait states entered from the WAIT pin processor modes However sof...

Page 681: ...e 110 6 wait state 111 7 wait state 4 When using external bus set this bit to 0 Note 3 R W 5 SWAIT 0 No strobe wait R W Strobe signal wait bit 1 Strobe wait added 6 RECOV 0 No recovery cycle R W Recov...

Page 682: ...ECOV Bit and IDLE Bit Settings and the Number of Idle Cycles Inserted RECOV IDLE Read Followed by Write Read Followed by Read Write 0 0 1 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 0 Note Under each of the above...

Page 683: ...combination with the Wait Controller 1 When the Bus Mode Control Register 0 External read write operations are performed using the address bus data bus and the signals CS0 CS3 RD BHW BLW WAIT and BCLK...

Page 684: ...about the CS Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Note When zero wait state is selected wait states inserted by WAIT are not accepted DB0 DB15 WAIT Read 1 cycle...

Page 685: ...r Note 2 For details about the CS Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Note Circles in the above diagram indicate the sampling timing 1 wait state Don t Care H...

Page 686: ...For details about the CS Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Note Circles in the above diagram indicate the sampling timing Internal 7 wait states Don t Care H...

Page 687: ...s about the CS Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Note Circles in the above diagram indicate the sampling timing L Internal 2 wait states External 1 wait stat...

Page 688: ...CS Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Note Circles in the above diagram indicate the sampling timing L Internal 2 wait states External n wait states Don t Ca...

Page 689: ...Register Note 2 For details about the CS Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Note Circles in the above diagram indicate the sampling timing 1 wait state Don t...

Page 690: ...s about the CS Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Note Circles in the above diagram indicate the sampling timing Internal 1 wait state Recovery cycle Don t Ca...

Page 691: ...ea Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing No idle cycles are added after the write cycle Internal 1 wai...

Page 692: ...it Control Register see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing No idle cycles are added after the write cycle Internal 1 wait sta...

Page 693: ...ignals CS0 CS3 RD BHE BLE WAIT and WR Figure 16 3 11 Internal Bus Access during Bus Free State H WR Bus free state Internal bus access H BCLK A11 A30 CS0 CS3 BHE BLE DB0 DB15 WAIT RD H Hi z Don t Care...

Page 694: ...S Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing When zero wait state is selected wait states inserted by...

Page 695: ...the CS Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing BCLK is not output Don t Care BHE BLE Internal 1 wai...

Page 696: ...bout the CS Area Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing BCLK is not output Internal 7 wait states Don t...

Page 697: ...Control Register see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing BCLK is not output Don t Care BHE BLE Internal 2 wait states Don t Ca...

Page 698: ...Control Register see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing BCLK is not output L Internal 2 wait states External n wait states Do...

Page 699: ...rea Wait Control Register see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing BCLK is not output Don t Care BHE BLE Internal 1 wait state...

Page 700: ...egister see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing BCLK is not output Don t Care BHE BLE Internal 1 wait state Don t Care H Recov...

Page 701: ...gister see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing BCLK is not output No idle cycles are added after the write cycle Don t Care BH...

Page 702: ...see Section 16 2 1 CS Area Wait Control Registers Notes Circles in the above diagram indicate the sampling timing BCLK is not output No idle cycles are added after the write cycle Don t Care BHE BLE...

Page 703: ...16 16 26 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller 32180 Group User s Manual Rev 1 0 This page is blank for reasons of layout...

Page 704: ...CHAPTER 17 RAM BACKUP MODE 17 1 Outline of RAM Backup Mode 17 2 Example of RAM Backup when Power is Down 17 3 Example of RAM Backup for Saving Power Consumption 17 4 Exiting RAM Backup Mode Wakeup...

Page 705: ...e power is down For the M32R ECU to turn off the power to the CPU at any time as needed to reduce the system s power consumption while retaining the internal RAM data RAM backup for saving the power c...

Page 706: ...g explains how the RAM can be backed up by using this circuit as an example 17 2 1 Normal Operating State Figure 17 2 2 shows the normal operating state of the M32R ECU During normal operation input o...

Page 707: ...e of RAM Backup when Power is Down 17 2 2 RAM Backup State Figure 17 2 3 shows the power outage RAM backup state of the M32R ECU When the power supply goes down the power supply monitor IC starts feed...

Page 708: ...rating State Figure 17 3 2 shows the normal operating state of the M32R ECU During normal operation the RAM backup signal output by the external circuit is high Also input on the SBI pin or ADnINi i 0...

Page 709: ...ns except VDDE is shut off C and D in Figure 17 3 3 Due to settings in 1 to 3 the VDDE pin voltage goes to 3 0 5 5 V and all other pin voltages drop to 0 V and the M32R ECU is thereby placed in RAM ba...

Page 710: ...e 17 3 4 Example of a RAM Backup Sequence for Low Power Operation 17 3 3 Precautions to Be Observed at Power On When changing port X from input mode to output mode after power on pay attention to the...

Page 711: ...t the RAM check data created before entering RAM backup mode c in Figure 17 4 1 4 If the comparison in 3 did not match initialize the RAM d in Figure 17 4 1 If the comparison in 3 matched use the reta...

Page 712: ...CHAPTER 18 OSCILLATOR CIRCUIT 18 1 Oscillator Circuit 18 2 Clock Generator Circuit...

Page 713: ...ing a ceramic or crystal resonator between the XIN and XOUT pins external to the chip Figure 18 1 1 shows an example of a system clock generating circuit using a resonator connected external to the ch...

Page 714: ...g XSTAT in software Figure 18 1 2 Block Diagram of the XIN Oscillation Stoppage Detection Circuit Port Input Special Function Control Register PICNT Address H 0080 0745 9 10 11 12 13 14 b15 b8 PIEN0 P...

Page 715: ...cleared Writing 1 to XSTAT is ignored 3 Method for using XSTAT to detect XIN oscillation stoppage Because the M32R ECU internally contains a PLL the internal clock remains active even when XIN oscill...

Page 716: ...drive capability performance ratio R W XIN XOUT drive capability select bit 00 Low 0 25 01 0 50 10 0 75 11 High 1 00 1 XDRV write control bit XDRVP Bit 5 This bit controls writing to the XIN XOUT dri...

Page 717: ...correct setting Settings that do not have effect Because a write cycle to other area exists the set value is not reflected XDRVP 1 Write to other area XDRVP 0 XDRV Set value 1 2 Because these two cons...

Page 718: ...0 P73 R W Port P73 operation mode bit 1 HACK 12 P74MD 0 P74 R W Port P74 operation mode bit 1 RTDTXD 13 P75MD 0 P75 R W Port P75 operation mode bit 1 RTDRXD 14 P76MD 0 P76 R W Port P76 operation mode...

Page 719: ...ck Generator Circuit 18 2 Clock Generator Circuit Supply independent clocks to the CPU and the internal peripheral circuit XIN pin 8MHz 10MHz BCLK peripheral clock 16MHz 20MHz CPUCLK CPU clock 64MHz 8...

Page 720: ...e of JTAG 19 2 Configuration of the JTAG Circuit 19 3 JTAG Registers 19 4 Basic Operation of JTAG 19 5 Boundary Scan Description Language 19 6 Notes on Board Design when Connecting JTAG 19 7 Processin...

Page 721: ...Signal Name I O Function TAP JTCK Test clock Input Clock input to the test circuit Note 1 JTDI Test data Input Input Synchronous serial data input pin used to supply the test instruction code and test...

Page 722: ...t of registers which are accessed through the boundary scan path boundary scan register bypass regis ter and ID code register Test access port abbreviated TAP controller to control the JTAG unit s sta...

Page 723: ...attempted the microcomputer may inadvertently handle b 110001 as instruction code which makes the microcomputer unable to operate normally Capture IR Exit1 IR Update IR Following instructions are supp...

Page 724: ...t of boundary scan test Connected between the JTDI and JTDO pins this register is selected when issuing BYPASS instruction This register is loaded with b 0 fixed value in the Capture DR state 3 ID Cod...

Page 725: ...scan path The sample value is output to the outside at the same time data is set from the outside As a register operation the bits are shifted right between each shift register stage Update operation...

Page 726: ...TAP Controller State Transition The state transition of the TAP Controller and the basic configuration of the JTAG related registers are shown below Data input G 0 1 D T Q D T R Q Shift DR or Shift I...

Page 727: ...Instruc tion Register s shift register stage 3 Proceed and apply JTMS low to enter the Shift IR state In the Shift IR state the value of the shift register stage is shifted right one bit every cycle a...

Page 728: ...tage To stop the shift operation in the middle enter the Pause DR state temporarily via the Exit1 DR state by setting JTMS input from high to low To return from the Pause DR state enter the Shift DR s...

Page 729: ...le state Note 3 Note 3 Specify the data register to inspect or set Note 1 Note 2 Note 1 Note 2 DR path sequence DR path sequence Setup data Setup data Note 3 Fixed value Fixed value Specify the data r...

Page 730: ...hat defines the logical direction of signal flow is deter mined here Physical pin map The physical pin map correlates the chip s logical ports to the physical pins on each package By using separate na...

Page 731: ...TDI TMS TCK TRST TDO GND Note 1 The RESET related circuit and resistance capacitance values must be determined depending on the user board s system design conditions and the microcomputer s operating...

Page 732: ...channel open drain output is recommended for the RESET output of JTAG tools For details see JTAG tool specifications Notes Only if the JTRST pin is firmly tied to ground the JTDO JTDI JTMS and JTCLK...

Page 733: ...Not Using JTAG The following shows how the pins on the chip should be processed when not using JTAG tools Figure 19 7 1 Processing Pins when Not Using JTAG for 240QFP M32R ECU JTDI JTMS JTCK JTRST Use...

Page 734: ...CHAPTER 20 POWER SUPPLY CIRCUIT 20 1 Configuration of the Power Supply Circuit 20 2 Power On Sequence 20 3 Power Off Sequence...

Page 735: ...verter VREF0 VREF1 Reference voltage for the A D converter VCC BUS Power supply for the external bus OSC VCC Power supply for the oscillator circuit VDDE Power supply for the internal RAM backup Figur...

Page 736: ...llation stabilization time release the RESET pin back high to deassert the reset input Notes Power on limitations VCCE OCS VCC VDDE VCCE OSC VCC However if the above power on limitations cannot be met...

Page 737: ...e power on limitations cannot be met sufficient evaluation must be made during system design in order to ensure that no power will be applied to the microcomputer with a potential difference of 1 V or...

Page 738: ...pin goes low before turning the power supply off Notes Power off limitations VCCE OCS VCC VDDE VCCE OSC VCC However if the above power off limitations cannot be met sufficient evaluation must be made...

Page 739: ...ote 2 Pull the RESET input pin low while the CPU is halted or RAM access is disabled Note 3 Wait until the RESET pin goes low before turning the power supply off Note 4 Lower the VDDE voltage from 5 0...

Page 740: ...Note 3 Wait until the RESET pin goes low before turning the power supply off Note 4 Lower the VDDE voltage from 3 3 V to 3 0 V as necessary Notes Power off limitations VCCE OCS VCC However if the abov...

Page 741: ...up Voltage Generator Circuit Sub VDC Note 2 Peripheral Circuit Flash Memory Oscillator Circuit A D Converter Circuit External Bus Figure 20 3 5 SRAM Data Backup State VCCE 5 0 V or 3 3 V VCCE 32180 OS...

Page 742: ...f XIN 10 MHz 21 3 Electrical Characteristics when VCCE 5 V f XIN 8 MHz 21 4 Electrical Characteristics when VCCE 3 3 V f XIN 10 MHz 21 5 Electrical Characteristics when VCCE 3 3 V f XIN 8 MHz 21 6 Fla...

Page 743: ...5 V AVCC Analog Power Supply VCCE AVCC VREF 0 3 6 5 V VREF Reference Voltage Input VCCE AVCC VREF 0 3 6 5 V VI Xin 0 3 OSC VCC 0 3 V VCNT 0 3 3 2 V Other 0 3 VCCE 0 3 V VO Xout 0 3 OSC VCC 0 3 V Other...

Page 744: ...0 5VCCE FP MOD0 1 JTMS JTRST JTDI RESET 0 8VCCE VCCE V Standard input for the following pins 0 8VCCE VCCE V RTDCLK RTDRXD SCLKI0 1 4 5 RXD0 5 TCLK0 3 TIN0 33 CRX0 1 Standard input for the following p...

Page 745: ...d JTDO JTMS 80 pF Capacitance Other than above 50 pF f XIN External Clock Input Frequency 5 10 MHz Note 1 Subject to conditions VCCE AVCC VREF VCCE OSC VCC Note 2 Make sure the total output current pe...

Page 746: ...nt VI VCCE 5 5 A IIL Low State Input Current VI 0V 5 5 A ICC Total Power Supply Current Note 1 f XIN 10 0MHz 75 mA When reset f XIN 10 0MHz 80 120 When operating IDDEhold RAM Retention VDDE 5 5V Ta 25...

Page 747: ...ng fast Slow mode Normal speed 9 55 sample and Double speed 5 05 hold Fast mode Normal speed 4 75 Double speed 2 65 IIAN Analog Input Leakage Current Note 2 AVSS ANi AVCC 5 5 A Note 1 Absolute accurac...

Page 748: ...E 0 5VCCE FP MOD0 1 JTMS JTRST JTDI RESET 0 8VCCE VCCE V Standard input for the following pins 0 8VCCE VCCE V RTDCLK RTDRXD SCLKI0 1 4 5 RXD0 5 TCLK0 3 TIN0 33 CRX0 1 Standard input for the following...

Page 749: ...A CL Output Load JTDO JTMS 80 pF Capacitance Other than above 50 pF f XIN External Clock Input Frequency 5 10 MHz Note 1 Subject to conditions VCCE AVCC VREF VCCE OSC VCC Note 2 Make sure the total ou...

Page 750: ...wing pins 1 0 RTDCLK RTDRXD SCLKI0 1 4 5 RXD0 5 TCLK0 3 TIN0 33 CRX0 1 Standard input for the following pins SBI HREQ 0 3 When threshold 0 7VCCE 0 35VCCE 1 0 switching function 0 7VCCE 0 5VCCE 0 3 is...

Page 751: ...V Conversion Without sample Slow mode Normal speed 18 6875 s Time and hold or Double speed 10 8125 during normal Fast mode Normal speed 8 1875 sample and hold Double speed 5 5625 During fast Slow mode...

Page 752: ...5VCCE FP MOD0 1 JTMS JTRST JTDI RESET 0 8VCCE VCCE V Standard input for the following pins 0 8VCCE VCCE V RTDCLK RTDRXD SCLKI0 1 4 5 RXD0 5 TCLK0 3 TIN0 33 CRX0 1 Standard input for the following pins...

Page 753: ...L Output Load JTDO JTMS 80 pF Capacitance Other than above 50 pF f XIN External Clock Input Frequency 5 10 MHz Note 1 Subject to conditions VCCE AVCC VREF VCCE OSC VCC Note 2 Make sure the total outpu...

Page 754: ...ate Input Current VI VCCE 5 5 A IIL Low State Input Current VI 0V 5 5 A ICC Total Power Supply Current Note 1 f XIN 10 0MHz 75 mA When reset f XIN 10 0MHz 80 120 When operating IDDEhold RAM Retention...

Page 755: ...ast Slow mode Normal speed 9 55 sample and Double speed 5 05 hold Fast mode Normal speed 4 75 Double speed 2 65 IIAN Analog Input Leakage Current Note 2 AVSS ANi AVCC 5 5 A Note 1 Absolute accuracy re...

Page 756: ...5VCCE FP MOD0 1 JTMS JTRST JTDI RESET 0 8VCCE VCCE V Standard input for the following pins 0 8VCCE VCCE V RTDCLK RTDRXD SCLKI0 1 4 5 RXD0 5 TCLK0 3 TIN0 33 CRX0 1 Standard input for the following pin...

Page 757: ...JTDO JTMS 80 pF Capacitance Other than above 50 pF f XIN External Clock Input Frequency 5 8 MHz Note 1 Subject to conditions VCCE AVCC VREF VCCE OSC VCC Note 2 Make sure the total output current peak...

Page 758: ...e Input Current VI VCCE 5 5 A IIL Low State Input Current VI 0V 5 5 A ICC Total Power Supply Current Note 1 f XIN 8 0MHz 65 mA When reset f XIN 8 0MHz 65 90 When operating IDDEhold RAM Retention Power...

Page 759: ...d TBD TCONV Conversion Without sample Slow mode Normal speed 18 6875 s Time and hold or Double speed 10 8125 during normal Fast mode Normal speed 8 1875 sample and hold Double speed 5 5625 During fast...

Page 760: ...Related Characteristics Symbol Parameter Test Condition Rated Value Unit MIN TYP MAX Topr Flash Rewrite Ambient Temperature 0 70 C cycle Flash Rewrite Durability 100 times tPRG Program Space 1page 8 1...

Page 761: ...trol Register IDLE bit or inserted by default when a write operation is executed immediately after a read ID 0 or 1 W Number of wait states selected by the WTCSEL bit 21 7 1 Timing Requirements 1 Inpu...

Page 762: ...t states 2W S 20 td RDH BLWL Write Delay Time after Read tc BCLK R ID 10 ns 56 td RDH BHWL td BLWH RDL Read Delay Time after Write With zero wait state ns 57 td BHWH RDL 10 With 1 or more wait states...

Page 763: ...ted values here are guaranteed for the case where the measured pin load capacitance CL 80 pF Symbol Parameter Rated Value Unit See Fig MIN MAX 21 7 11 tsu HREQL BCLKH HREQ Input Setup Time before BCLK...

Page 764: ...8 tsu RTDRXD RTDCLKL RTDRXD Input Setup Time 60 160 ns 89 8 JTAG interface timing Symbol Parameter Rated Value Unit See Fig MIN MAX 21 7 13 tc JTCK JTCK Input Cycle Time 100 ns 60 tw JTCKH JTCK Input...

Page 765: ...th internal clock selected Symbol Parameter Rated Value Unit See Fig MIN MAX 21 7 1 td E P Port Data Output Delay Time 100 ns 3 Symbol Parameter Rated Value Unit See Fig MIN MAX 21 7 2 td CLK D TXD Ou...

Page 766: ...K With zero wait state 4 ns 28 With 1 or more wait states 10 tpzx BCLKL DZ Data Output Enable Time after BCLK 10 ns 29 tpxz BCLKH DZ Data Output Disable Time after BCLK 5 ns 30 td A RDL Address Delay...

Page 767: ...it state 5 ns 72 byte enable mode With 1 or more wait states tc BCLK R 5 td BLE WRL Byte Enable Delay Time before Write 1 S 15 ns 73 td BHE WRL byte enable mode tv WRH BLE Byte Enable Valid Time after...

Page 768: ...d not with the VCCE power supply Therefore the reference voltage for these ports is the VCC BUS input voltage P00 P07 P10 P17 P20 P27 P30 P37 P41 P47 P70 P73 P224 P225 SCLKO TXD RXD 6 td CLK D 4 tsu D...

Page 769: ...nual Rev 1 0 Figure 21 7 3 SBI Timing Figure 21 7 5 TINi Timing Figure 21 7 4 TOi Timing SBI 13 tw SBIL 0 2VCCE 0 2VCCE BCLK TOi 15 td BCLK TOi 0 8VCCE 0 2VCCE 0 2VCC BUS TINi 0 8VCCE 0 2VCCE 0 8VCCE...

Page 770: ...17 tw BCLKH 21 tv BCLKH A 18 tw BCLKL 20 td BCLKH CS 22 tv BCLKH CS 22 tv BCLKH CS 24 tv BCLKH RDL 92 td BCLKH RDL 0 16VCC BUS 0 43VCC BUS 0 16VCC BUS 23 td BCLKL RDL 20 td BCLKH CS 0 43VCC BUS 0 16V...

Page 771: ...CLKL RDL 0 16VCC BUS 32 th BCLKH D 31 tsu D BCLKH 90 tv BCLKH BLWL tv BCLKH BHWL 28 tv BCLKH D 30 tpxz BCLKH DZ 29 tpzx BCLKL DZ 27 td BCLKL D 25 td BCLKL BLWL td BCLKL BHWL 0 16VCC BUS 0 43VCC BUS 0...

Page 772: ...DH CS 0 16VCC BUS 0 43VCC BUS 0 16VCC BUS 40 td CS RDL 0 16VCC BUS 45 th RDH D 44 tsu D RDH 0 16VCC BUS 0 43VCC BUS CS Non access area RD Data input DB0 DB15 57 td BLWH RDL td BHWH RDL 56 td RDH BLWL...

Page 773: ...US 0 16VCC BUS 0 16VCC BUS 0 43VCC BUS CS Non access area RD Data output DB0 DB15 56 td RDH BLWL td RDH BHWL 57 td BLWH RDL td BHWH RDL 0 43VCC BUS 51 tw BLWL tw BHWL 47 td A BLWL td A BHWL 49 tv BLWH...

Page 774: ...VCC BUS 0 43VCC BUS 0 16VCC BUS 0 16VCC BUS 0 16VCC BUS 0 43VCC BUS CS Non access area RD Data output DB0 DB15 81 td WRH RDL 0 43VCC BUS 68 tw WRL 77 tpxz WRH DZ BLE BHE 0 16VCC BUS 73 td BLEL WRL td...

Page 775: ...KL HACKL HREQ 0 16VCC BUS 0 43VCC BUS 0 16VCC BUS 0 16VCC BUS 0 16VCC BUS 35 tsu HREQL BCLKH 0 16VCC BUS Figure 21 7 12 Input Transition Time of JTAG Pins JTCK JTDI JTMS JTRST 58 tr 59 tf 0 8VCCE 0 2V...

Page 776: ...ACK 89 tsu RTDRXD RTDCLKL 87 td RTDCLKH RTDTXD 88 th RTDCLKH RTDRXD Figure 21 7 13 JTAG Interface Timing JTCK 0 5VCCE 60 tc JTCK 67 tw JTRST Data input JTDI JTMS Data output JIDO JTRST 0 8VCCE 0 2VCCE...

Page 777: ...trol Register IDLE bit or inserted by default when a write operation is executed immediately after a read ID 0 or 1 W Number of wait states selected by the WTCSEL bit 21 8 1 Timing Requirements 1 Inpu...

Page 778: ...states 2W S 20 td RDH BLWL Write Delay Time after Read tc BCLK R ID 10 ns 56 td RDH BHWL td BLWH RDL Read Delay Time after Write With zero wait state ns 57 td BHWH RDL 10 With 1 or more wait states t...

Page 779: ...ed values here are guaranteed for the case where the measured pin load capacitance CL 80 pF Symbol Parameter Rated Value Unit See Fig MIN MAX 21 8 11 tsu HREQL BCLKH HREQ Input Setup Time before BCLK...

Page 780: ...tsu RTDRXD RTDCLKL RTDRXD Input Setup Time 60 160 ns 89 8 JTAG interface timing Symbol Parameter Rated Value Unit See Fig MIN MAX 21 8 13 tc JTCK JTCK Input Cycle Time 100 ns 60 tw JTCKH JTCK Input H...

Page 781: ...h internal clock selected Symbol Parameter Rated Value Unit See Fig MIN MAX 21 8 1 td E P Port Data Output Delay Time 100 ns 3 Symbol Parameter Rated Value Unit See Fig MIN MAX 21 8 2 td CLK D TXD Out...

Page 782: ...With zero wait state 4 ns 28 With 1 or more wait states 10 tpzx BCLKL DZ Data Output Enable Time after BCLK 10 ns 29 tpxz BCLKH DZ Data Output Disable Time after BCLK 5 ns 30 td A RDL Address Delay T...

Page 783: ...t state 5 ns 72 byte enable mode With 1 or more wait states tc BCLK R 5 td BLE WRL Byte Enable Delay Time before Write 1 S 15 ns 73 td BHE WRL byte enable mode tv WRH BLE Byte Enable Valid Time after...

Page 784: ...not with the VCCE power supply Therefore the reference voltage for these ports is the VCC BUS input voltage P00 P07 P10 P17 P20 P27 P30 P37 P41 P47 P70 P73 P224 P225 SCLKO TXD RXD 6 td CLK D 4 tsu D...

Page 785: ...ual Rev 1 0 Figure 21 8 3 SBI Timing Figure 21 8 5 TINi Timing Figure 21 8 4 TOi Timing SBI 13 tw SBIL 0 2VCCE 0 2VCCE BCLK TOi 15 td BCLK TOi 0 8VCCE 0 2VCCE 0 2VCC BUS TINi 0 8VCCE 0 2VCCE 0 8VCCE 0...

Page 786: ...0 BLW BHW CS Access area WAIT 0 43VCC BUS 0 16VCC BUS 19 td BCLKH A 0 43VCC BUS 17 tw BCLKH 21 tv BCLKH A 18 tw BCLKL 20 td BCLKH CS 22 tv BCLKH CS 22 tv BCLKH CS 24 tv BCLKH RDL 92 td BCLKH RDL 0 16V...

Page 787: ...LKL RDL 0 16VCC BUS 32 th BCLKH D 31 tsu D BCLKH 90 tv BCLKH BLWL tv BCLKH BHWL 28 tv BCLKH D 30 tpxz BCLKH DZ 29 tpzx BCLKL DZ 27 td BCLKL D 25 td BCLKL BLWL td BCLKL BHWL 0 16VCC BUS 0 43VCC BUS 0 1...

Page 788: ...H CS 0 16VCC BUS 0 43VCC BUS 0 16VCC BUS 40 td CS RDL 0 16VCC BUS 45 th RDH D 44 tsu D RDH 0 16VCC BUS 0 43VCC BUS CS Non access area RD Data input DB0 DB15 57 td BLWH RDL td BHWH RDL 56 td RDH BLWL t...

Page 789: ...S 0 16VCC BUS 0 16VCC BUS 0 43VCC BUS CS Non access area RD Data output DB0 DB15 56 td RDH BLWL td RDH BHWL 57 td BLWH RDL td BHWH RDL 0 43VCC BUS 51 tw BLWL tw BHWL 47 td A BLWL td A BHWL 49 tv BLWH...

Page 790: ...CC BUS 0 43VCC BUS 0 16VCC BUS 0 16VCC BUS 0 16VCC BUS 0 43VCC BUS CS Non access area RD Data output DB0 DB15 81 td WRH RDL 0 43VCC BUS 68 tw WRL 77 tpxz WRH DZ BLE BHE 0 16VCC BUS 73 td BLEL WRL td B...

Page 791: ...L HACKL HREQ 0 16VCC BUS 0 43VCC BUS 0 16VCC BUS 0 16VCC BUS 0 16VCC BUS 35 tsu HREQL BCLKH 0 16VCC BUS Figure 21 8 12 Input Transition Time of JTAG Pins JTCK JTDI JTMS JTRST 58 tr 59 tf 0 8VCCE 0 2VC...

Page 792: ...CK 89 tsu RTDRXD RTDCLKL 87 td RTDCLKH RTDTXD 88 th RTDCLKH RTDRXD Figure 21 8 13 JTAG Interface Timing JTCK 0 5VCCE 60 tc JTCK 67 tw JTRST Data input JTDI JTMS Data output JTDO JTRST 0 8VCCE 0 2VCCE...

Page 793: ...21 21 52 ELECTRICAL CHARACTERISTICS 32180 Group User s Manual Rev 1 0 This page is blank for reasons of layout 21 8 A C Characteristics when VCCE 3 3 V...

Page 794: ...CHAPTER 22 TYPICAL CHARACTERISTICS...

Page 795: ...22 22 2 32180 Group User s Manual Rev 1 0 TYPICAL CHARACTERISTICS To be written at a later time...

Page 796: ...APPENDIX 1 MECHANICAL SPECIFICAITONS Appendix 1 1 Dimensional Outline Drawing...

Page 797: ...Lead Material Cu Alloy 240P6Y A Plastic 240pin 32 32mm body QFP 0 35 0 45 Symbol Min Nom Max A A2 b c D E HE L L1 y b2 Dimension in Millimeters HD A1 0 225 I2 1 2 MD 32 6 ME 32 6 10 0 0 1 1 3 0 7 0 5...

Page 798: ...APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2 1 32180 Instruction Processing Time...

Page 799: ...er of Execution Cycles in Each Stage Instruction IF D E MEM1 MEM2 WB Load instructions LD LDB LDUB LDH LDUH LOCK R Note 1 1 1 R Note 1 1 1 Store instructions ST STB STH UNLOCK R Note 1 1 1 W Note 1 1...

Page 800: ...internal resource RAM 1 CPUCLK cycle When reading the internal resource ROM 2 CPUCLK cycles When reading the internal resource SFR byte or halfword 4 CPUCLK cycles When reading the internal resource...

Page 801: ...Appendix 2 Appendix 2 4 32180 Group User s Manual Rev 1 0 INSTRUCTION PROCESSING TIME Appendix 2 1 32180 Instruction Processing Time This page is blank for reasons of layout...

Page 802: ...APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3 1 Example Processing of Unused Pins...

Page 803: ...iring length possible within 20 mm from the microcomputer pins Note 2 If any port is set for output mode and left open care should be taken because the port remains set for input before it is changed...

Page 804: ...pin is instable and the power supply current tends to increase while the port remains set for input Because it is possible that the content of the port direction register will inadvertently be altere...

Page 805: ...being reset Therefore the voltage level at the pin is instable and the power supply current tends to increase while the port remains set for input Because it is possible that the content of the port d...

Page 806: ...ash Memory Appendix 4 5 Precautions to Be Observed after Reset Appendix 4 6 Precautions about Input Output Ports Appendix 4 7 Precautions about the DMAC Appendix 4 8 Precautions about the Multijunctio...

Page 807: ...d memory are different Word data 32 bits 0 1 2 3 b0 b31 HH HL LH LL b0 b31 HH HL LH LL Halfword data 16 bits 0 1 2 3 b0 b31 H L b0 b15 H L Byte data 8 bits 0 1 2 3 b0 b31 b0 b7 R0 R15 R0 R15 R0 R15 0...

Page 808: ...ress exception handler to the program that was being executed when the exception occurred Appendix 4 4 Precautions To Be Observed when Programming Internal Flash Memory The following describes precaut...

Page 809: ...alue set in it before the Port Direction Register can be set for output Conversely if the Port Direction Register is set for output before setting data in the Port Data Register the Port Data Register...

Page 810: ...ritten to it is ignored 3 Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer Although this operation means accessing the DMAC related registers while DMA is e...

Page 811: ...count clock a count clock dependent delay is included before F F output is inverted after the timer is enabled When writing to the correction register be careful not to cause the counter to overflow E...

Page 812: ...F0 0014 H 0004 H FFF0 H 0014 H FFF8 H FFFF Data inverted by enable Data inverted by underflow H FFF8 1 Counter Count clock Correction register F F output TOP interrupt request due to underflow Enable...

Page 813: ...unt is disabled Even if the counter overflows due to correction of counts no interrupt requests are generated for reasons of an overflow Therefore if the counter underflows in the subsequent down coun...

Page 814: ...when using TIO PWM output mode If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit the latter has priority so that count is disabled If...

Page 815: ...changes to reload value 1 at the next clock edge Appendix 4 8 8 Precautions on Using TIO Continuous Output Mode The following describes precautions to be observed when using TIO continuous output mode...

Page 816: ...en normally Therefore when using any clock other than BCLK 2 do not write to the counter If clock bus 1 is selected and any clock other than BCLK 2 is used for the timer the value captured into the me...

Page 817: ...ges to reload value 1 at the next clock edge Because a 0 or 100 duty cycle needs to be determined when reloading the counter there is a one count clock equivalent delay before F F is inverted and an i...

Page 818: ...cession Because the timer operates synchronously with the prescaler output a count clock dependent delay is included before F F output is inverted after the timer is enabled Appendix 4 8 15 Precaution...

Page 819: ...beforeread Regarding the analog input pins Figure 4 9 1 shows the internal equivalent circuit of the A D Converter s analog input part To obtain accurate A D conversion results make sure the internal...

Page 820: ...sampled for only the first bit a Example for calculating the external stabilizing capacitor C1 addition of this capacitor is recommended Assuming the R1 in Figure 4 9 1 is infinitely large and that th...

Page 821: ...Single mode Slow mode Normal speed 27 5BCLK when sample and Double speed 15 5BCLK hold enabled Fast mode Normal speed 11 5BCLK Double speed 7 5BCLK Comparator mode Slow mode Normal speed 27 5BCLK Dou...

Page 822: ...n the SIO Transmit Buffer Register before a transmit operation on the transmitter side starts Transmission reception using DMA To transmit receive data in DMA request mode enable the DMAC to accept tr...

Page 823: ...verrun error If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register i e an overrun error occurred the received data is...

Page 824: ...ut mode after power on pay attention to the following If port X is set for output mode while no data is set in the Port X Data Register the port s initial output level is instable Therefore before cha...

Page 825: ...SDI connector JTAG connector Power TDI TMS TCK TRST TDO GND Note 1 The RESET related circuit and resistance capacitance values must be determined depending on the user board s system design condition...

Page 826: ...ating conditions Note 2 N channel open drain output is recommended for the RESET output of JTAG tools For details see JTAG tool specifications Notes Only if the JTRST pin is firmly tied to ground the...

Page 827: ...he following shows how the pins on the chip should be processed when not using JTAG tools Figure 4 12 3 Processing Pins when Not Using JTAG for 240QFP M32R ECU JTDI JTMS JTCK JTRST User board JTDO VCC...

Page 828: ...he RESET pin Reduce the length of wiring connecting to the RESET pin Especially when connecting a capacitor between the RESET and VSS pins make sure it is wired to each pin in the shortest distance po...

Page 829: ...nd is connected to GND Reasons The microcomputer operates synchronously with the clock generated by an oscillator circuit Inclusion of noise on the clock input output pins causes the clock waveform to...

Page 830: ...much thick and short wiring as possible for connections to the VCNT pin When connecting a capacitor to VCNT make sure its grounding lead wire and the OSC VSS pin on the microcomputer are connected in...

Page 831: ...ridden Furthermore if the capacitor connected between the analog input pin and AVSS pin is grounded at a position apart from the AVSS pin noise riding on the ground line may pen etrate into the micro...

Page 832: ...e oscillator and VCNT pin as possible Also make sure the circuit is protected with a GND pattern Reasons Systems using a microcomputer have signal lines to control a motor LED or thermal head for exam...

Page 833: ...s as their voltage level frequently rises and falls Especially if these signal lines intersect the clock related signal lines they will cause the clock waveform to become distorted which may result in...

Page 834: ...y as possible If greater stability is required do not use those that belong to the same port group and set them for input and connect to GND via a resistor If they need to be used insert a limiting re...

Page 835: ...input mode Noise Method for limiting noise with a resistor Noise Fast switching Adjacent pin peripheral pin set for input Method for limiting the effect of noise in input mode Adjacent pin peripheral...

Page 836: ...series to the input output ports Software measures For input ports read out data in a program two or more times to verify that the levels coincide For output ports rewrite the data register at certai...

Page 837: ...Appendix 4 Appendix 4 32 32180 Group User s Manual Rev 1 0 SUMMARY OF PRECAUTIONS This page is blank for reasons of layout Appendix 4 13 Precautions about Noise...

Page 838: ...Microcomputers USER S MANUAL 32180 Group Rev 1 0 All Rights Reserved No part of this manual may be reproduced or distributed in any form or by any means without the written permission of Mitsubishi 20...

Page 839: ...User s Manual 32180 Group New publication effective Jan 2003 Specifications subject to change without notice 2003 MITSUBISHI ELECTRIC CORPORATION...

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