Renesas M32R/ECU Series, User Manual

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10
10-186
MULTIJUNCTION TIMERS
10.8 TOU (Output-Related 24-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
10.8.14 Operation in TOU Delayed Single-shot Output Mode (without Correction Function)
(1) Outline of TOU delayed single-shot output mode
In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1)
after a finite time equal to (counter set value + 1) only once and then stops.
When the timer is enabled after setting the counter and reload register, it starts counting down from the
counter’s set value synchronously with the count clock. The first time the counter underflows, it is loaded with
the reload register value and continues counting down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from low
to high or vice versa) when the counter underflows first time and next, generating a single-shot pulse wave-
form in width of (reload register set value + 1) after a finite time equal to (first set value of c 1) only
once. An interrupt request can be generated when the counter underflows first time and next.
The (counter set value + 1) and (reload register set value + 1) respectively are effective as count values. (For
counting operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”)
(2) Precautions on using TOU delayed single-shot output mode
The following describes precautions to be observed when using TOU delayed single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the
enable bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the
enable bit, the latter has priority so that count is disabled.
• To read the counter on-the-fly, make sure the read timing does not coincide with an underflow of the 16
low-order bits (8 high-order bits decremented). When reading the counter on-the-fly, take the appropriate
measure to ensure that the read value is correct by, for example, reading the counter twice in succession.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FF FFFF but immediately changes to (reload value – 1) at the next clock
edge.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is in-
cluded before F/F output is inverted after the timer is enabled.