1
1-5
OVERVIEW
32180 Group User’s Manual (Rev.1.0)
1.2 Block Diagram
1.2 Block Diagram
Figure 1.2.1 shows a block diagram of the 32180. The features of each block are described in Table 1.2.1.
Figure 1.2.1 Block Diagram of the 32180
PLL Clock Generator
Internal Bus
Interface
Address
Data
Internal RAM
(48 Kbytes)
Internal Flash Memory
(1 Mbytes = 1,024 Kbytes)
M32R-FPU Core
(80 MHz)
Multiplier/Accumulator
(32 bits
×
16 bits + 56 bits)
DMAC
(10 channels)
Multijunction Timer
(64 channels)
Serial I/O
(6 channels)
A-D Converter
×
2
(A-D0 : 10-bit converter, 16 channels)
(A-D1 : 10-bit converter, 16 channels)
Wait Controller
Interrupt Controller
(32 sources, 8 levels)
Real-Time Debugger
(RTD)
External Bus
Interface
Inter
nal
32-bit b
u
s
Input/output ports, 158 lines
Full CAN
(2 channels)
Single-precision FPU
(fully IEEE 754 compliant)
Inter
nal
16-bit b
u
s
Inter
nal
32-bit b
u
s
Internal Power Supply
Generator (VDC)
Summary of Contents for M32R/ECU Series
Page 17: ...12 This page is blank for reasons of layout...
Page 712: ...CHAPTER 18 OSCILLATOR CIRCUIT 18 1 Oscillator Circuit 18 2 Clock Generator Circuit...
Page 794: ...CHAPTER 22 TYPICAL CHARACTERISTICS...
Page 796: ...APPENDIX 1 MECHANICAL SPECIFICAITONS Appendix 1 1 Dimensional Outline Drawing...
Page 798: ...APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2 1 32180 Instruction Processing Time...
Page 802: ...APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3 1 Example Processing of Unused Pins...
