3
3-11
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
32180 Group User’s Manual (Rev.1.0)
SFR Area Register Map (4/27)
Address
+0 address
+1 address
See pages
b0
b7 b8
b15
H'0080 0204
Prescaler Register 2
Output Event Bus Control Register
10-12
(PRS2)
(OEBCR)
10-17
(Use inhibited area)
H'0080 0210
TCLK Input Processing Control Register
10-20
(TCLKCR)
H'0080 0212
TIN0–4 Input Processing Control Register
10-21
(TIN04CR)
H'0080 0214
TIN5–8 Input Processing Control Register
10-22
(TIN58CR)
H'0080 0216
TIN9–11 Input Processing Control Register
10-23
(TIN911CR)
H'0080 0218
TIN12–19 Input Processing Control Register
10-24
(TIN1219CR)
H'0080 021A
TIN20–23, TIN30–33 Input Processing Control Register
10-24
(TIN2023_3033CR)
(Use inhibited area)
H'0080 0220
F/F6–15 Source Select Register
10-28
(FF615S)
H'0080 0222
(Use inhibited area)
F/F16–19 Source Select Register
10-29
(FF1619S)
H'0080 0224
F/F0–15 Protect Register
10-30
(FF015P)
H'0080 0226
F/F0–15 Data Register
10-32
(FF015D)
H'0080 0228
(Use inhibited area)
F/F16–20 Protect Register
10-30
(FF1620P)
H'0080 022A
(Use inhibited area)
F/F16–20 Data Register
10-32
(FF1620D)
(Use inhibited area)
H'0080 0230
TOP0–5 Interrupt Request Status Register
TOP0–5 Interrupt Request Mask Register
10-39
(TOP05IST)
(TOP05IMA)
H'0080 0232
TOP6, 7 Interrupt Request Mask & Status Register
TOP8, 9 Interrupt Request Mask & Status Register
10-41
(TOP67IMS)
(TOP89IMS)
10-42
H'0080 0234
TIO0–3 Interrupt Request Mask & Status Register
TIO4–7 Interrupt Request Mask & Status Register
10-43
(TIO03IMS)
(TIO47IMS)
10-44
H'0080 0236
TIO8, 9 Interrupt Request Mask & Status Register
TMS0, 1 Interrupt Request Mask & Status Register
10-45
(TIO89IMS)
(TMS01IMS)
10-46
H'0080 0238
TIN0–2 Interrupt Request Mask & Status Register
TIN3–6 Interrupt Request Mask & Status Register
10-47
(TIN02IMS)
(TIN36IMS)
10-48
H'0080 023A
TIN7–11 Interrupt Request Status Register
TIN7–11 Interrupt Request Mask Register
10-49
(TIN711IST)
(TIN711IMA)
H'0080 023C
TIN12–19 Interrupt Request Status Register
TIN12–19 Interrupt Request Mask Register
10-51
(TIN1219IST)
(TIN1219IMA)
H'0080 023E
TIN20–23 Interrupt Request Mask & Status Register
TIN30–33 Interrupt Request Mask & Status Register
10-53
(TIN2023IMS)
(TIN3033IMS)
10-57
H'0080 0240
TOP0 Counter
10-75
(TOP0CT)
H'0080 0242
TOP0 Reload Register
10-76
(TOP0RL)
H'0080 0244
(Use inhibited area)
H'0080 0246
TOP0 Correction Register
10-77
(TOP0CC)
(Use inhibited area)
H'0080 0250
TOP1 Counter
10-75
(TOP1CT)
H'0080 0252
TOP1 Reload Register
10-76
(TOP1RL)
H'0080 0254
(Use inhibited area)
H'0080 0256
TOP1 Correction Register
10-77
(TOP1CC)
(Use inhibited area)
|
|
|
|
|
Summary of Contents for M32R/ECU Series
Page 17: ...12 This page is blank for reasons of layout...
Page 712: ...CHAPTER 18 OSCILLATOR CIRCUIT 18 1 Oscillator Circuit 18 2 Clock Generator Circuit...
Page 794: ...CHAPTER 22 TYPICAL CHARACTERISTICS...
Page 796: ...APPENDIX 1 MECHANICAL SPECIFICAITONS Appendix 1 1 Dimensional Outline Drawing...
Page 798: ...APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2 1 32180 Instruction Processing Time...
Page 802: ...APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3 1 Example Processing of Unused Pins...