Renesas M32R/ECU Series, User Manual

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4
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EIT
32180 Group User’s Manual (Rev.1.0)
4.8 Exception Processing
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in
hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector
entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT
handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack.
Also, save the accumulator and FPSR register as necessary.
(6) Returning from the EIT handler
At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction.
When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time,
the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure
4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruc-
tion exception suggests that the system has some fatal fault already existing in it. In such a case, therefore,
do not return from the reserved instruction exception handler to the program that was being executed when
the exception occurred.
4.8.2 Address Exception (AE)
[Occurrence Conditions]
Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store
instructions. The following lists the combination of instructions and accessed addresses that may cause
address exceptions to occur.
• Two low-order address bits accessed in the LDH, LDUH or STH instruction are ‘01’ or ‘11’
• Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are ‘01,’ ‘10’ or ‘11’
When an address exception occurs, memory access by the instruction that generated the exception is not
performed. If an external interrupt is requested at the same time an address exception is detected, it is the
address exception that is accepted.
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM
←
SM
BIE
←
IE
BC
←
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM
←
Unchanged
IE
←
0
C
←
0
(3) Saving the PC
The PC value of the instruction that generated the address exception is set in the BPC register. For ex-
ample, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC
register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set
in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that
generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on
a word boundary (BPC register bit 30 = "1").
However, in either case of the above, the address to which the RTE instruction returns after the EIT handler
has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned
to the PC.)