Renesas M32R/ECU Series, User Manual

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12
12-39
Serial I/O
32180 Group User's Manual (Rev.1.0)
12.5 Precautions on Using CSIO Mod
12.5 Precautions on Using CSIO Mode
• Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register
The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s
BRG count source select bit must always be set before the serial I/O starts operating. If these settings need
to be changed after a transmit or receive operation has started, first check to see that transmit and receive
operations have finished and then clear the transmit and receive enable bits before making changes.
• Settings of BRG (Baud Rate Register)
If f(BCLK) is selected with the BRG clock source select bit, use caution when setting the BRG register so that
the transfer rate will not exceed 2 Mbps.
• About successive transmission
To transmit data successively, make sure the next transmit data is set in the SIO Transmit Buffer Register
before the current data transmission finishes.
• About reception
Because the receive shift clock in CSIO mode is derived by an operation of the transmit circuit, transmit
operation must always be executed (by sending dummy data) even when the serial I/O is used for only
receiving data. In this case, be aware that if the port function is set for the TXD pin (by setting the operation
mode register to "1"), dummy data may actually be output from the pin.
• About successive reception
To receive data successively, make sure that data (dummy data) is set in the SIO Transmit Buffer Register
before a transmit operation on the transmitter side starts.
• Transmission/reception using DMA
To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the
DMA Mode Register) before serial communication starts.
• About reception finished bit
If a receive error (overrun error) occurs, the reception finished bit can only be cleared by clearing the receive
enable bit, and cannot be cleared by reading out the receive buffer register.
• About overrun error
If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO
Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer
register, with the previous received data retained in it. Although a receive operation continues thereafter, the
subsequent received data is not stored in the receive buffer register (receive status bit = "1").
Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared to "0".
And this is the only way that the overrun error flag can be cleared.
• About DMA transfer request generation during SIO transmission
If the transmit buffer register becomes empty (transmit buffer empty flag = "1") while the transmit enable bit
remains set to "1" (transmission enabled), an SIO transmit buffer empty DMA transfer request is generated.
• About DMA transfer request generation during SIO reception
If the reception finished bit is set to "1" (receive buffer register full), a reception finished DMA transfer request
is generated. Be aware, however, that if an overrun error occurred during reception, this DMA transfer re-
quest is not generated.