Renesas M32R/ECU Series, User Manual

Page: 512 / 839

12
12-21
Serial I/O
12.2 Serial I/O Related Registers
32180 Group User's Manual (Rev.1.0)
(1) RSTAT (Receive Status) bit (Bit 1)
[Set condition]
This bit is set to "1" by a start of receive operation. When this bit = "1", the serial I/O is receiving data.
[Clear condition]
This bit is cleared to "0" upon completion of receive operation or by clearing the REN (Receive Enable) bit.
(2) RFIN (Reception Finished) bit (Bit 2)
[Set condition]
This bit is set to "1" when all data bits have been received in the Receive Shift Register and whose
content is transferred to the Receive Buffer Register.
[Clear condition]
This bit is cleared to "0" by reading out the lower byte of the Receive Buffer Register or by clearing the
REN (Receive Enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out
the lower byte of the Receive Buffer Register. In this case, clear REN (Receive Enable) bit.
(3) REN (Receive Enable) bit (Bit 3)
Reception is enabled by setting this bit to "1", and is disabled by clearing this bit to "0", in which case the
receiver unit is initialized. Accordingly, the receive status and reception finished flags, as well as the overrun
error, framing error, parity error and error sum flags all are cleared.
The receive operation stops if the Receive Enable bit is cleared to "0" while receiving data.
(4) OVR (Overrun Error) bit (Bit 4)
[Set condition]
This bit is set to "1" when all bits of the next received data have been set in the Receive Shift Register
while the Receive Buffer Register still contains the previous received data. In this case, the received
data is not stored in the Receive Buffer Register. Although receive operation continues even when the
overrun error flag = "1", the received data is not stored in the Receive Buffer Register. This error bit must
be cleared before normal reception can be restarted.
[Clear condition]
This bit is cleared to "0" by only clearing the REN (Receive Enable) bit.
(5) PTY (Parity Error) bit (Bit 5)
This bit is effective in only UART mode. It is fixed to "0" during CSIO mode.
[Set condition]
The PTY (Parity Error) bit is set to "1" when the SIO Transmit/Receive Mode Register PEN (Parity
Enable/Disable) bit is enabled and the parity (even or odd) of the received data does not agree with one
that was set by the said register’s PSEL (Parity Select) bit.
[Clear condition]
The PTY bit is cleared to "0" by reading out the lower byte of the SIO Receive Buffer Register or by
clearing the SIO Receive Control Register REN (Receive Enable) bit. However, if an overrun error
occurs, this bit cannot be cleared by reading out the lower byte of the Receive Buffer Register. In this
case, clear the REN (Receive Enable) bit.