Renesas M32R/ECU Series, User Manual

Page: 514 / 839

12
12-23
Serial I/O
12.2 Serial I/O Related Registers
32180 Group User's Manual (Rev.1.0)
12.2.7 SIO Baud Rate Registers
SIO0 Baud Rate Register (S0BAUR) <Address: H'0080 0117>
SIO1 Baud Rate Register (S1BAUR) <Address: H'0080 0127>
SIO2 Baud Rate Register (S2BAUR) <Address: H'0080 0137>
SIO3 Baud Rate Register (S3BAUR) <Address: H'0080 0147>
SIO4 Baud Rate Register (S4BAUR) <Address: H'0080 0A17>
SIO5 Baud Rate Register (S5BAUR) <Address: H'0080 0A27>
9 10 11 12 13 14 b15 b8
BRG
? ? ? ? ? ? ? ?
<After reset: Undefined>
b Bit Name Function R W
8–15 BRG The baud rate count source selected by SIO Mode Register R W
Baud rate divide value is divided by (n + 1) where n = BRG set value.
(1) BRG (baud rate divide value) (Bits 8–15)
The SIO Baud Rate Registers are used to set a baud rate divide value, so that the baud rate count source
selected by SIO Mode Register is divided by (n + 1) where n = BRG set value.
Because the BRG value initially is undefined, be sure to set the divide value before the serial I/O starts
operating. The value written to the BRG during transmit/receive operation takes effect in the next cycle after
the BRG counter has finished counting.
When using the internal clock (to output the SCLKO signal) in CSIO mode, the serial I/O divides the internal
BCLK using a clock divider and then divides the resulting clock by (n + 1) where n = BRG set value and
further by 2, thereby generating a transmit/receive shift clock.
When using an external clock in CSIO mode, the serial I/O does not use the BRG. (Transmit/receive opera-
tions are synchronized to the externally supplied clock.)
During UART mode, the serial I/O divides the internal BCLK using a clock divider and then divides the
resulting clock by (n + 1) where n = BRG set value and further by 16, thereby generating a transmit/receive
shift clock.
When using SIO0, SIO1, SIO4 or SIO5 in UART mode, set the relevant port (P84, P87, P65 or P66) to
function as an SCLKO pin, so that a BRG output clock divided by 2 can be output from that SCLKO pin.
When using the internal clock (internally clocked CSIO mode or UART mode), if f(BCLK) is selected as the
BRG count source, make sure the transfer rate does not exceed 2 Mbits/second during CSIO mode, and that
BRG is equal to or greater than 7 during UART mode.