Renesas M32R/ECU Series, User Manual

Page: 515 / 839

12
12-24
Serial I/O
12.3 Transmit Operation in CSIO Mode
32180 Group User's Manual (Rev.1.0)
12.3 Transmit Operation in CSIO Mode
12.3.1 Setting the CSIO Baud Rate
The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock
source from which a transmit/receive shift clock derives is selected from the internal clock f(BCLK) or external
clock. The CKS (Internal/External Clock Select) bit (SIO Transmit/Receive Mode Register bit 11) is used to
select the clock source.
The equation used to calculate the transmit/receive baud rate differs depending on whether an internal or exter-
nal clock is selected.
(1) When internal clock is selected in CSIO mode
When the internal clock is selected, f(BCLK) is divided by a clock divider before being supplied to the Baud
Rate Generator (BRG).
The clock divider’s divide-by value is selected from 1, 8, 32 or 256 by using the CDIV (baud rate generator
count source select) bits (Transmit Control Register bits 2–3).
The Baud Rate Generator divides the clock divider output by (baud rate register set value + 1) and further by
2, thus generating a transmit/receive shift clock.
When the internal clock is selected in CSIO mode, the baud rate is calculated using the equation below.
Baud rate =
f(BCLK)
[bps]
Clock divider’s divide-by value x (baud rate register set value + 1) x 2
Baud rate register set value = H’00 to H’FF (Note 1)
Clock divider’s divide-by value = 1, 8, 32 or 256
Note 1: If divide-by-1 (i.e., f(BCLK) itself) is selected as the baud rate generator count source, use
caution when setting the baud rate register so that the transfer rate will not exceed 2 Mbps.
(2) When external clock is selected in CSIO mode
In this case, the Baud Rate Generator is not used, and the input clock from the SCLKI pin serves directly as
a transmit/receive shift clock for CSIO.
The maximum frequency of the SCLKI pin input clock is f(BCLK)/16.
Baud rate = SCLKI pin input clock
[bps]