Renesas M32R/ECU Series, User Manual

Page: 242 / 839

9
DMAC
9-37
32180 Group User’s Manual (Rev.1.0)
9.3 Functional Description of the DMAC
Figure 9.3.4 Example of How Addresses Are Incremented in 32-channel Ring Buffer Mode
9.3.10 End of DMA and Interrupt
In normal mode, DMA transfer is terminated by an underflow of the transfer count register. When transfer fin-
ishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. Also, an interrupt request is
generated at completion of transfer. However, if interrupt requests on any channel have been masked by the
DMA Interrupt Request Mask Register, no interrupt requests are generated on that channel.
During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the
transfer enable bit is cleared to "0" (to disable transfer). In this case, therefore, no interrupt requests are gener-
ated at completion of DMA transfer. Nor are these DMA transfer-completed interrupt requests are generated
even when transfer in ring buffer mode is terminated by clearing the transfer enable bit.
9.3.11 Each Register Status after Completion of DMA Transfer
When DMA transfer is completed, the status of the source and destination address registers becomes as fol-
lows:
(1) Address fixed
• The values set in the address registers before DMA transfer started remain intact (fixed).
(2) Address incremental
• For 8-bit transfer, the values of the address registers are the last transfer a 1.
• For 16-bit transfer, the values of the address registers are the last transfer a 2.
The transfer count register at completion of DMA transfer is in an underflow state (H’FFFF). Therefore, before
another DMA transfer can be performed, the transfer count register must be set newly again, except when trying
to perform transfers 65,536 times (H’FFFF).
<When transfer size = 8 bits>
Transfer count Transfer address
1 H'0080 1000
2 H'0080 1001
3 H'0080 1002
31 H'0080 101E
32 H'0080 101F
↓ ↓ ↓ ↓
1 H'0080 1000
2 H'0080 1001
<When transfer size = 16 bits>
Transfer count Transfer address
1 H'0080 1000
2 H'0080 1002
3 H'0080 1004
31 H'0080 103C
32 H'0080 103E
1 H'0080 1000
2 H'0080 1002
| | | |
| | | |