Renesas M32R/ECU Series, User Manual

Page: 124 / 839

5
5-13
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
Figure 5.5.1 Example of Priority Resolution when Accepting Interrupt Requests
5.5 Description of Interrupt Operation
5.5.1 Acceptance of Internal Peripheral I/O Interrupts
An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by comparing its
ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register.
If its priority is higher than the IMASK value, the interrupt request is accepted. However, if two or more interrupt
requests occur simultaneously, the Interrupt Controller resolves priority between these interrupt requests follow-
ing the procedure described below.
1) The ILEVEL values set in the Interrupt Control Registers for the respective internal peripheral I/Os are
compared with each other.
2) If the ILEVEL values are the same, priorities are resolved according to the predetermined hardware priority.
3) The ILEVEL and IMASK values are compared.
If two or more interrupt requests occur simultaneously, the Interrupt Controller first compares their priority levels
set in each Interrupt Control Register’s ILEVEL bit to select an interrupt request that has the highest priority. If
the interrupt requests have the same ILEVEL value, their priorities are resolved according to the hardware fixed
priority. The interrupt request thus selected has its ILEVEL value compared with the IMASK value and if its
priority is higher than the IMASK value, the Interrupt Controller sends an EI request to the CPU.
Interrupt requests may be masked by setting the Interrupt Request Mask Register and the Interrupt Control
Register’s ILEVEL bit (disabled at level 7) provided for each internal peripheral I/O and the PSW register IE bit.
5.5 Description of Interrupt Operation
Interrupt
requested
or not
Resolve priority
according to
Interrupt Priority
Level (ILEVEL)
Resolve priority
according to
hardware priority
Compare with
IMASK value
TIN3-6 input interrupt request
TIO4-7 output interrupt request
TOP8,9 output interrupt request
SIO0 transmit interrupt request
DMA0-4 interrupt request
A-D0 conversion interrupt request
(ILEVEL settings)
Level 3
Level 4
Level 5
Level 3
Level 1
Level 3
Not requested
Requested
Requested
Requested
Requested
Requested
Hardware
fixed priority
Accept interrupt
if PSW register
IE bit = 1
Level 3
Level 3
Level 3
Can be accepted
when IMASK = 4-7
1) 2) 3)