Renesas M32R/ECU Series, User Manual

Page: 95 / 839

4
4-6
EIT
32180 Group User’s Manual (Rev.1.0)
4.2.3 Trap
Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector
addresses are provided corresponding to TRAP instruction operands 0–15.
4.3 EIT Processing Procedure
EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which
they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted,
except for a rest interrupt, is shown below.
4.2 EIT Events
Figure 4.3.1 Outline of the EIT Processing Procedure
When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described
later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for
the EIT handler (not the jump address itself) is written.
In the hardware preprocessing, the PC is transferred to the BPC (backup PC), and the content of the PSW register’s
PSW field is transferred to the BPSW field in that register.
Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC and
PSW registers (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the
stack. In addition, the accumulator and the FPSR register must be saved to the stack as necessary. Remember
that all these registers must be saved to the stack in a program by the user.
When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute
the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed
when the EIT occurred. (This does not apply to the System Break Interrupt, however.)
In the hardware postprocessing, the BPC is returned to the PC, and the content of the PSW register’s BPSW field
is returned to the PSW field in that register. Note that the values stored in the BPC and the PSW register’s BPSW
field after executing the RTE instruction are undefined.
Instruction
A
PC
→
BPC
PSW
→
BPSW
EIT vector
entry
EIT handler except for SBI
RTE
instruction
Program suspended
and EIT request
accepted
Instruction
processing-canceled
type (RIE, AE)
Instruction processing-completed
type (FPE, EI, TRAP)
Program execution restarted
EIT request
generated
Hardware preprocessing
BPC, PSW, FPSR
and general-purpose
registers are saved
to the stack
Branch
instruction
General-purpose
registers, PSW, FPSR
and BPC are restored
from the stack
Hardware postprocessing
(SBI)
Program terminated
or system is reset
User-created EIT handler
BPSW
→
PSW
BPC
→
PC
Processing
by handler
Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.
(Note 1)
(Note 1)
SBI
(System Break
Interrupt processing)
Instruction
B
Instruction
C
Instruction
C
Instruction
D