Renesas M32R/ECU Series, User Manual

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Appendix 4
Appendix
4-12
32180 Group User's Manual (Rev. 1.0)
SUMMARY OF PRECAUTIONS
Appendix 4.8.11 Precautions on Using TOU PWM Output Mode
The following describes precautions to be observed when using TOU PWM output mode.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included
before F/F output is inverted after the timer is enabled.
Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count
clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. However,
startup requests to other timers are not delayed. For details, see Section 10.8.17, “0% or 100% Duty-Cycle
Wave Output during PWM Output and Single-shot PWM Output Modes.”
Appendix 4.8.12 Precautions on Using TOU Single-Shot PWM Output Mode
The following describes precautions to be observed when using TOU single-shot PWM output mode.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.
Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count
clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. However,
startup requests to other timers are not delayed. For details, see Section 10.8.17, “0% or 100% Duty-Cycle
Wave Output during PWM Output and Single-shot PWM Output Modes.”
Appendix 4.8.13 Precautions on Using TOU Delayed Single-Shot Output Mode
The following describes precautions to be observed when using TOU delayed single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable
bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• To read the counter on-the-fly, make sure the read timing does not coincide with an underflow of the 16 low-
order bits (8 high-order bits decremented). When reading the counter on-the-fly, take the appropriate mea-
sure to ensure that the read value is correct by, for example, reading the counter twice in succession.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H’FF FFFF but immediately changes to (reload value – 1) at the next clock edge.
• Because the timer operates synchronously with the prescaler output, a count clock-dependent delay is
included before F/F output is inverted after the timer is enabled.
Appendix 4.8 Precautions about the Multijunction Timers