JTAG and EOnCE Module Programming Model
MSC8113 Reference Manual, Rev. 0
Freescale Semiconductor
18-23
You can observe the status of all three SC140 cores by programming the GPR and shifting in a
JTAG instruction three times. However, it is easier to observe the status of all three SC140 cores
at once by shifting out the contents of the parallel input register. The Parallel Input Register
(PIREG) is selected using the
READ
PIREG
command and then shifting out 32 bits from the
PIREG. The bits shifted out reflect the status of the SC140 cores. See Table 18-7 for the bit-field
definitions.
Table 18-7. PIREG Bit Descriptions
Number
Reset
Description
Settings
—
31–25
0
Reserved.
core 2 cores
24–23
0
Core 2 Core Status
Reflects the status of core 2
00 Core is executing instructions.
01 Core is in Wait or Stop mode.
10 Core is waiting for bus.
11 Core is in debug mode.
core 2
upd_ack
22
0
Core 2 Update Acknowledge
Indicates whether the core 2 SC140 EOnCE
module has executed the last instruction
dispatched to it
0
EOnCE module has executed the last
instruction dispatched to it.
1
EOnCE module has not executed the
last instruction dispatched to it.
core 1 cores
21–20
0
Core 1 Core Status
Reflects the status of core 1
00 Core is executing instructions.
01 Core is in Wait or Stop mode.
10 Core is waiting for bus.
11 Core is in debug mode.
core 1 upd_ack
19
0
Core 1 Update Acknowledge
Indicates whether the SC140 core 1 EOnCE
module has executed the last instruction
dispatched to it.
0
EOnCE module has executed the last
instruction dispatched to it.
1
EOnCE module has not executed the
last instruction dispatched to it.
core 0 cores
18–17
0
Core 0 Core Status
Reflects the status of core 0.
00 Core is executing instructions.
01 Core is in Wait or Stop mode.
10 Core is waiting for bus.
11 Core is in debug mode.
core 0
upd_ack
16
0
Core 0 Update Acknowledge
Indicates whether the SC140 core 0 EOnCE
module has executed the last instruction
dispatched to it.
0
EOnCE module has executed the last
instruction dispatched to it.
1
EOnCE module has not executed the
last instruction dispatched to it.
—
15–0
0
Reserved.
Summary of Contents for MSC8113
Page 1: ...MSC8113 Reference Manual Tri Core 16 Bit Digital Signal Processor MSC8113RM Rev 0 May 2008 ...
Page 20: ...MSC8113 Reference Manual Rev 0 xx Freescale Semiconductor Contents ...
Page 28: ...MSC8113 Reference Manual Rev 0 xxviii Freescale Semiconductor ...
Page 56: ...MSC8113 Reference Manual Rev 0 1 28 Freescale Semiconductor MSC8113 Overview ...
Page 76: ...MSC8113 Reference Manual Rev 0 2 20 Freescale Semiconductor SC140 Core Overview ...
Page 134: ...MSC8113 Reference Manual Rev 0 4 30 Freescale Semiconductor System Interface Unit SIU ...
Page 168: ...MSC8113 Reference Manual Rev 0 6 18 Freescale Semiconductor Boot Program ...
Page 180: ...MSC8113 Reference Manual Rev 0 7 12 Freescale Semiconductor Clocks ...
Page 260: ...MSC8113 Reference Manual Rev 0 8 80 Freescale Semiconductor Memory Map ...
Page 300: ...MSC8113 Reference Manual Rev 0 9 40 Freescale Semiconductor Extended Core ...
Page 304: ...MSC8113 Reference Manual Rev 0 10 4 Freescale Semiconductor MQBus and M2 Memory ...
Page 308: ...MSC8113 Reference Manual Rev 0 11 4 Freescale Semiconductor SQBus ...
Page 590: ...MSC8113 Reference Manual Rev 0 17 46 Freescale Semiconductor Interrupt Processing ...
Page 614: ...MSC8113 Reference Manual Rev 0 18 24 Freescale Semiconductor Debugging ...
Page 622: ...MSC8113 Reference Manual Rev 0 19 8 Freescale Semiconductor Internal Peripheral Bus IPBus ...
Page 724: ...MSC8113 Reference Manual Rev 0 21 32 Freescale Semiconductor UART ...
Page 920: ...MSC8113 Reference Manual Rev 0 25 150 Freescale Semiconductor Ethernet Controller ...
Page 1171: ...MSC8113 Reference Manual Rev 0 Freescale Semiconductor C 61 EF wait_rts P 01077FFC 9F rts 71 ...
Page 1172: ...MSC8113 Reference Manual Rev 0 C 62 Freescale Semiconductor MSC8113 Boot Code ...
Page 1202: ...MSC8113 Reference Manual Rev 0 Index 30 Freescale Semiconductor Index ...