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NXP Semiconductors MSC8113, Reference Manual

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MSC8113 Reference Manual, Rev. 0

13-36

Freescale Semiconductor

System Bus

13.2.4   Data Tenure Operations

This section describes the operation of the MSC8113 device during the data bus arbitration, 
transfer, and termination phases of the data tenure.

13.2.4.1   Data Bus Arbitration

The beginning of an address transfer, marked by the assertion of transfer start (

TS

), is also an 

implicit data bus request if the transfer type signals (

TT[0–4]

) indicate that the transaction is not 

address-only. (The address-only transactions are not applicable for MSC8113). The MSC8113 
arbiter supports three external masters and uses 

DBG

 signals to grant the external master data bus. 

The 

DBG

 signals are not asserted if the data bus, which is shared with memory, is busy with a 

transaction. A qualified data bus grant occurs if 

DBG

 is asserted while the data bus operation 

signals 

DBB

 and 

ARTRY

 are deasserted. The MSC8113 arbiter should assert 

DBG

 only when the 

first 

TA

 is asserted with or after the associated 

ARTRY

. The MSC8113 

DBG

 is asserted with 

TS

 if 

the data bus is free and if PPC_ACR[DBGD] = 0. If PPC_ACR[DBGD]  = 1 and the data bus is 
not busy, 

DBG

 is asserted one cycle after 

TS

. The 

DBG

 delay should ensure that 

ARTRY

 is not 

asserted after the first or only 

TA

 assertion. For the programming model, see the discussion of the 

60x Bus Arbiter Configuration Register (PPC_ACR) in Section 4.2.1, System Configuration and 
Protection Registers.

Note:

DBB

 should not be asserted after the data tenure is finished. Assertion of 

DBB

 after the 

last 

TA

 causes improper operation of the bus. MSC8113 internal masters do not assert 

DBB

 after the last 

TA

.

If the data bus is not busy with the data of a previous transaction on the bus, the external arbiter 
must assert 

DBG

 in the same cycle in which 

TS

 is asserted (by a master that was granted the bus) 

or in the following cycle. If the external arbiter asserts 

DBG

 on the cycle in which 

TS

 is asserted, 

PPC_ACR[DBGD] should be set to zero. Otherwise, PPC_ACR[DBGD] should be set to one. 
External masters connected to the system bus must assert 

DBB

 only for the duration of their data 

tenure. External masters should not use 

DBB

 to prevent other masters from using the data bus after 

their data tenure has ended.

13.2.4.2   Data Streaming Mode

A special MSC8113 data streaming mode improves bus performance in some conditions. 
Generally, the bus protocol requires one idle cycle between any two data tenures to prevent 
contention on the data bus when the driver of the data is changing. However, when the driver on 
the data bus is the same for both data tenures, this idle cycle can be omitted. In data streaming 
mode, the MSC8113 omits the idle cycle where possible. MSC8113 applications often require 
data stream transfers of more than 4

×

64 bits. For example, the ATM cell payload is 6 

×

 64 (12 

×

 

32) bits. All this data is driven from a single device on the bus, so data-streaming saves a cycle 
for such a transfer. When data-streaming mode is enabled, transactions initiated by bus masters 
within the device omit the idle cycle if the data driver is the same. Note that data streaming mode 

Summary of Contents for MSC8113

Page 1: ...MSC8113 Reference Manual Tri Core 16 Bit Digital Signal Processor MSC8113RM Rev 0 May 2008 ...

Page 2: ...uch unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim all...

Page 3: ...ctionary I Index Universal Asynchronous Receiver Transmitter UART External Signals Reset Boot Program Memory Map Extended Core Hardware Semaphores Direct Memory Access DMA Controller Internal Peripheral Bus IPBus Time Division Multiplexing TDM Interface Timers General Purpose Input Output GPIO 3 5 6 8 9 15 16 19 20 22 23 MQBus and M2 Memory 10 SQBus 11 I2 C Software Module 24 Ethernet Controller 2...

Page 4: ...ctionary I Index Universal Asynchronous Receiver Transmitter UART External Signals Reset Boot Program Memory Map Extended Core Hardware Semaphores Direct Memory Access DMA Controller Internal Peripheral Bus IPBus Time Division Multiplexing TDM Interface Timers General Purpose Input Output GPIO 3 5 6 8 9 15 16 19 20 22 23 MQBus and M2 Memory 10 SQBus 11 I2 C Software Module 24 Ethernet Controller 2...

Page 5: ...em 1 14 1 2 2 Power Saving Modes 1 15 1 2 2 1 Extended Core Wait Mode 1 15 1 2 2 2 Extended Core Stop Mode 1 16 1 2 3 M2 Memory 1 16 1 2 4 System Interface Unit SIU 1 16 1 2 4 1 60x Compatible System Bus Interface 1 16 1 2 4 2 Memory Controller 1 17 1 2 5 Direct Slave Interface DSI 1 17 1 2 6 Direct Memory Access DMA Controller 1 18 1 2 7 Internal and External Bus Architecture 1 19 1 2 8 TDM Seria...

Page 6: ... 2 2 2 Data Arithmetic Logic Programming Model 2 11 2 2 3 Program Control Unit Programming Model 2 12 2 3 Instruction Set Overview 2 12 2 4 Additional Programming Considerations 2 19 3 External Signals 3 1 Power Signals 3 3 3 2 Clock Signals 3 3 3 3 Reset and Configuration Signals 3 3 3 4 Direct Slave Interface System Bus Ethernet and Interrupt Signals 3 4 3 5 Memory Controller Signals 3 16 3 6 GP...

Page 7: ...ces in a System With No EPROM 5 13 5 6 Reset Programming Model 5 13 5 6 1 Hard Reset Configuration Word 5 13 5 6 2 Reset Status Registers 5 16 6 Boot Program 6 1 Boot Basics 6 2 6 2 Booting From an External Memory Device 6 3 6 3 Booting from an External Host DSI or System Bus 6 4 6 4 Booting From the TDM Interface 6 4 6 4 1 Initializing the TDM Physical Layer 6 5 6 4 1 1 Receiver Initialization 6 ...

Page 8: ... 2 Extended Core Memory M1 9 3 9 2 1 Memory Organization 9 4 9 2 1 1 Memory Groups 9 4 9 2 1 2 Memory Contention and Priority 9 6 9 2 2 Errors and Exceptions 9 6 9 2 2 1 Errors 9 6 9 2 2 2 Exceptions 9 6 9 3 Extended QBus System 9 7 9 3 1 Architecture 9 8 9 3 1 1 Fetch Unit 9 9 9 3 2 QBus Execution Order 9 11 9 3 3 QBus Banks 9 11 9 3 4 Bank Registers 9 12 9 3 5 Bank Addressing 9 12 9 3 6 Reservat...

Page 9: ...ystem Bus 11 3 11 2 3 Conditions for Failure of the Reservation Operation 11 3 12 Memory Controller 12 1 Basic Architecture 12 3 12 1 1 Address and Address Space Checking 12 8 12 1 2 Page Hit Checking 12 8 12 1 3 Parity Generation and Checking 12 8 12 1 4 Transfer Error Acknowledge TEA Generation 12 9 12 1 5 Machine Check Interrupt MCP Generation 12 9 12 1 6 Data Buffer Controls BCTL 0 1 12 9 12 1...

Page 10: ... Signals Timing Configuration 12 34 12 3 1 1 Chip Select Assertion Timing 12 34 12 3 1 2 Chip Select and Write Enable Deassertion Timing 12 36 12 3 1 3 Relaxed Timing 12 37 12 3 1 4 Output Enable POE Timing 12 38 12 3 1 5 Programmable Wait State Configuration 12 38 12 3 1 6 Extended Hold Time on Read Accesses 12 40 12 3 2 GPCM Signals External Access Termination 12 42 12 3 3 Boot Chip Select Opera...

Page 11: ...2 6 5 External Masters Timing 12 85 12 7 Internal SRAM and IPBus Peripherals Support 12 92 12 7 1 UPM Programming Example Internal SRAM 12 92 12 7 2 GPCM Programming Example IPBus Peripherals 12 94 12 7 3 Flyby Mode 12 94 12 8 Memory Controller Programming Model 12 95 13 System Bus 13 1 System Bus Signals 13 1 13 1 1 Address Arbitration 13 3 13 1 2 Address Start 13 5 13 1 3 Address Bus 13 5 13 1 4...

Page 12: ...ansfers and PSDVAL Termination 13 38 13 2 4 6 Data Bus Termination by Assertion of TEA Signal 13 40 14 Direct Slave Interface DSI 14 1 Data Bus 14 3 14 1 1 Data Bus Width 14 3 14 1 2 DCR BEM Bit Access Considerations 14 4 14 2 Address Bus 14 6 14 2 1 Sliding Window Addressing Mode 14 6 14 2 2 Full Address Addressing Mode 14 8 14 2 3 Host Chip ID Signals HCID 0 3 14 10 14 2 4 DSI Endian Modes 14 10...

Page 13: ...4 16 2 DMA Operating Modes Transfer Types 16 8 16 2 1 DMA Transfer Size and Peripheral Port Size 16 8 16 2 2 DMA Access Modes 16 8 16 2 3 Application Examples 16 10 16 2 3 1 External Memory and an External Peripheral on the System Bus 16 10 16 2 3 2 External Peripheral to Internal Memory 16 11 16 2 3 3 External Peripheral to External Peripheral 16 12 16 2 3 4 External Memory and External Memory on...

Page 14: ...C Stop Mode 17 8 17 1 2 Local Interrupt Controller LIC 17 9 17 1 2 1 Resolving LIC Interrupts by the SC140 Cores 17 11 17 1 2 2 Level Interrupt Mode 17 12 17 1 2 3 Edge Interrupt Mode 17 13 17 1 2 4 DMA Interrupts 17 13 17 1 2 5 LIC Interrupt Sources 17 13 17 1 3 Programmable Interrupt Controller PIC 17 17 17 1 4 Peripheral Bus QBus Interface 17 18 17 1 4 1 Interrupt Request Generation 17 18 17 1 ...

Page 15: ... 5 Exiting Debug Mode 18 15 18 5 6 Accessing EOnCE Registers Through JTAG in Real Time 18 15 18 5 7 External Debug Exception Request 18 15 18 5 8 Generating a Debug Exception From an EDCA PC Detection Event 18 16 18 6 Tracing in the MSC8113 18 16 18 7 General JTAG Mode Restrictions 18 17 18 8 JTAG and EOnCE Module Programming Model 18 18 18 8 1 Identification Register 18 18 18 8 2 Boundary Scan Re...

Page 16: ... Mapped on the Local Bus 20 22 20 2 6 1 Data Buffer Size and A m law Channels 20 22 20 2 6 2 Data Buffer Address 20 23 20 2 6 3 Threshold Pointers and Interrupts 20 26 20 2 6 4 Unified Buffer Mode 20 28 20 2 7 Adaptation Machine 20 29 20 3 TDM Power Saving 20 31 20 4 Channel Activation 20 31 20 5 Loopback Support 20 32 20 6 TDM Initialization 20 33 20 7 TDM Programming Model 20 34 20 7 1 Configura...

Page 17: ...ceiver Standby Mode 21 23 21 5 Interrupt Operation 21 24 21 6 UART Programming Model 21 24 22 Timers 22 1 Timers Programming Model 22 8 22 1 1 Configuration Registers 22 9 22 1 2 Control Registers 22 16 22 1 3 Status Registers 22 17 23 GPIO 23 1 Features 23 1 23 2 GPIO Block Diagram 23 2 23 3 Ethernet Functionality of GPIO 23 4 23 4 GPIO Connection Functions 23 6 23 5 GPIO Programming Model 23 9 2...

Page 18: ... RMII 25 14 25 6 2 1 RMII Transmit Flow 25 15 25 6 2 2 RMII Receive Flow 25 16 25 6 3 SMII 25 16 25 6 3 1 SMII Transmit Flow 25 17 25 6 3 2 SMII Receive Flow Mode 25 19 25 7 MAC Control of CSMA CD 25 21 25 7 1 Handling Packet Collisions 25 21 25 7 2 Controlling Packet Flow 25 22 25 7 3 Controlling PHY Links 25 22 25 8 RMON Support 25 23 25 9 Frame Recognition 25 23 25 9 1 Pattern Matching Recognit...

Page 19: ...us Registers 25 62 25 17 3 Transmit Control and Status Registers 25 69 25 17 4 Receive Control and Status Registers 25 78 25 17 5 MAC Registers 25 84 25 17 6 MII Management Registers 25 92 25 17 7 MIIGSK Registers 25 96 25 17 8 RMON Management Information Base MIB 25 105 25 17 9 Hash Function Registers 25 131 25 17 10 Pattern Matching Registers 25 133 25 17 11 Data Structures Buffer Descriptors 25...

Page 20: ...MSC8113 Reference Manual Rev 0 xx Freescale Semiconductor Contents ...

Page 21: ...for data and command communication The programmable interrupt controller PIC and local interrupt controller LIC process all internal interrupt requests notifying the SC140 DSP cores or external devices of an interrupt event Three Extended Cores Communications SIU Includes four TDM interfaces with 256 channels each a UART thirty two 16 bit timers thirty two programmable GPIO signals eight hardware ...

Page 22: ...anual is intended for software and hardware developers and applications programmers who want to develop products with the MSC8113 It is assumed that you have a working knowledge of DSP technology and that you may be familiar with Freescale products based on the Freescale DSP56000 or DSP56300 core Familiarity with Freescale DSP products is not necessary For your convenience the chapters of this man...

Page 23: ...items in bulleted lists 0x Prefix to denote a hexadecimal number 0b Prefix to denote a binary number REG FIELD Abbreviations or acronyms for registers or buffer descriptors appear in uppercase text Specific bits fields or numeric ranges appear in brackets For example ICR INIT refers to the Force Initialization bit in the host Interface Control Register ACTIVE HIGH SIGNALS Names of active high sign...

Page 24: ...ry and a brief description of the chapters of this manual Chapter 1 MSC8113 Overview Features descriptive overview of main modules configurations and application examples Chapter 2 SC140 Core Overview Target markets features overview of development tools descriptive overview of main modules Chapter 3 External Signals Identifies the external signals lists signal groupings including the number of si...

Page 25: ...ller PIC and the local interrupt controller LIC Chapter 10 MQBus and M2 Memory Describes how the MQBus supports a multi core environment by allowing all three SC140 cores to share the M2 memory through the MQBus The MQBus ensures a low miss ratio for SC140 ICache accesses Chapter 11 SQBus Explains the structure and function of the SQBus which is available to all SC140 cores to fetch program code f...

Page 26: ...s to be defined and provides additional information specific to the MSC8113 implementation Chapter 19 Internal Peripheral Bus IPBus Describes the internal peripheral buss IPBus the devices that connect to it energy management capabilities for devices on the bus Stop modes and the programming model Chapter 20 TDM Interface Describes the four TDM interfaces Each can handle up to 256 channels The int...

Page 27: ...a sheet MSC8113 Details the signals AC DC characteristics PLL DLL performance issues clock configuration and signal characteristics package and pinout and electrical design considerations of the MSC8113 device Application Notes Cover various programming topics related to the StarCore DSP core and the MSC8113 device Further Reading StarCore SC140 DSP Core Reference Manual Covers the SC140 core arch...

Page 28: ...MSC8113 Reference Manual Rev 0 xxviii Freescale Semiconductor ...

Page 29: ...tended core that includes a level 1 224 KB internal memory M1 for program and data storage a 16 KB 16 way instruction cache ICache a fetch unit for the ICache and a 4 entry write buffer queue for boosting core performance Each extended core also includes a programmable interrupt controller PIC a local interrupt controller LIC and debugging registers in an Enhanced On Chip Emulation EOnCE module an...

Page 30: ...ollowing 224 KB M1 memory that is accessed by the SC140 core with zero wait states Support for atomic accesses to the M1 memory 16 KB instruction cache 16 ways A four entry write buffer that frees the SC140 core from waiting for a write access to finish External cache support by asserting the global signal GBL when predefined memory banks are accessed Programmable Interrupt Controller PIC Local In...

Page 31: ... one CS signal for multiple DSPs Broadcast CS signal enables parallel write to multiple DSPs Big endian little endian and munged little endian support 3 Mode Signal Multiplexing 64 bit DSI and 32 bit system bus 32 bit DSI and 64 bit system bus 32 bit DSI and 32 bit system bus Memory Controller Flexible eight bank memory controller Three user programmable machines UPMs general purpose chip select m...

Page 32: ... data lines with one clock and one frame sync shared among the transmit and receive lines Glueless interface to E1 T1 framers and switches as well as to common buses such as the ST BUS Hardware A law μ law conversion Up to 62 5 Mbps per TDM 62 5 MHz bit clock if one data line is used 31 25 MHz if two data lines are used 15 625 MHz if four data lines are used Up to 256 channels Up to 16 MB per chan...

Page 33: ...ceiver and transmitter interrupt requests Eight flags the first five can generate interrupt request Transmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun Noise error Framing error Parity error Receiver framing error detection Hardware parity checking 1 16 bit time noise detection Maximum bit rate 6 25 Mbps Single wire and loop operations General Purpose I O GPI...

Page 34: ... up to 256 bytes deep into the frame Offsets to a maximum of 252 bytes Programmable pattern size in 4 byte increments up to 64 bytes Accept or reject frames if a match is detected Up to eight unicast addresses for exact matches Pattern matching accepts rejects IP addresses Filing of receive frames based on pattern match prioritization of frames Insertion with expansion or replacement for transmit ...

Page 35: ...ion dependent peripheral dependent and mode dependent Packaging 0 8 mm pitch High Temperature Coefficient for Expansion Flip Chip Ceramic Ball Grid Array CBGA HCTE 431 connection ball 20 mm 20 mm Table 1 8 Software Support Feature Description Real Time Operating System RTOS The Real Time Operating System RTOS fully supports device architecture multi core memory hierarchy ICache timers DMA controll...

Page 36: ...code assembly code or mixed mode Simulator Device simulation models enables design and simulation before the hardware arrival Profiler An analysis tool using a patented Binary Code Instrumentation BCI technique that enables the developer to identify program design inefficiencies Version control CodeWarrior includes plug ins for ClearCase Visual SourceSafe and CVS Boot Options External memory Exter...

Page 37: ...is accessed for a bounded number of times while the critical code is run in loops for many cycles DSP applications have a high degree of code locality and a low degree of data locality Different channels can share code but do not share data A small portion of the code is run for most of the time the 20 80 rule Figure 1 1 MSC8113 Block Diagram MQBus SQBus Local Bus 128 128 Boot ROM 64 PLL JTAG RS 2...

Page 38: ...l memories located on the system bus between internal peripherals and internal SRAM located on the local bus and between internal memories The SC140 core accesses the M2 memory through the MQBus All accesses to other internal peripherals and accesses external to the MSC8113 occur on a separate bus the SQBus This separation ensures that the latencies for SC140 core accesses to the M2 memory remain ...

Page 39: ...40 is that all instructions are 16 bits wide During each clock cycle the SC140 core reads eight instruction words referred to as a fetch set The SC140 core identifies which instructions can be performed in parallel and runs them on the ALUs and address generation units In one clock cycle up to six instructions four ALU operations and two address generation operations can be performed In the rich i...

Page 40: ...ally the case since program code is stored in a different group than the data space of the program The DMA stores the next buffers in yet a different group Even in the same group if two data elements are placed on a different 4 KB module a collision between two SC140 core buses is prevented When a collision does occur the SC140 core stalls for one clock cycle The overall memory size available for ...

Page 41: ...ly used instructions in the cache the operating system can exclude the ways of task A from the part of the cache that can be thrashed Another method of guaranteeing that the critical routines are always available for a task is to store them in the SC140 core M1 private memory All the cache entries are flushed by issuing a cache flush command from the SC140 core which is useful for example when new...

Page 42: ...140 core The module handles the SC140 core and the instruction cache requests bringing the data on the QBus As Figure 1 4 shows the EQBS consists of a bus switch to handle data read operations a write buffer to handle data write operations a fetch unit to handle all program read operations a control unit and the banks to handle the communication with the slaves and all EQBS registers Note For deta...

Page 43: ...ffer in the following cases The address of the destination belongs to a bank that is defined as immediate It is an atomic operation essentially writing to a semaphore The write buffer is disabled The write buffer counts the number of clocks that elapse between the time data is written to the write buffer and the time it is emptied When the counter exceeds a pre programmed value the contents of the...

Page 44: ...8101 This unit controls the system bus and the internal local bus It contains a flexible memory controller for accessing various memory devices both internally and externally The SIU also controls the system start up and initialization as well as operation and protection Note For details see Chapter 4 System Interface Unit SIU 1 2 4 1 60x Compatible System Bus Interface The system bus interface ca...

Page 45: ...s to low performance memory mapped peripherals The UPMs support address multiplexing of the system bus and refresh timers as well as generation of programmable control signals for row address and column address strobes providing a glueless interface to DRAMs burstable SRAMs and almost any other kind of peripheral The refresh timers allow refresh cycles to be initiated The UPM can generate differen...

Page 46: ...s and the local bus Transfers on both buses can be performed in parallel Transfers that occur on the same bus between clients with the same port size can use the flyby mode on which the data is read and written in the same cycle Other transfers are dual accesses that occur in two phases so that data is first read to a DMA internal FIFO and then written from that FIFO Eight internal DMA FIFOs suppo...

Page 47: ... states using its internal 128 bit instruction bus and two 64 bit data buses These buses include 32 bit program address bus PAB that allows the SC140 core to specify program addresses in the local unified memory M1 128 bit program data bus PDB that transfers the program data to and from M1 or the ICache Two 32 bit address buses XABA and XABB to specify data locations in M1 for the two data streams...

Page 48: ...an IP master that connects the local bus and SQBus to some system peripherals This one master multi slave bus runs at up to 166 MHz and enables access to the control and the status registers of the DSI the TDM interface the ethernet controller the timers the UART the hardware semaphores the virtual interrupt registers and the GPIOs Either an external host or an SC140 core accesses the clients on t...

Page 49: ...ice uses it to access internal resources Slave support direct access by an external host to internal resources including the M1 and M2 memories Internal arbitration between up to four master devices The external buses can be configured during reset in three modes 64 bit data DSI and 32 bit data system bus 32 bit data DSI and 64 bit data system bus 32 bit data DSI 32 bit data system and Ethernet MI...

Page 50: ...t and the second threshold lines Both the first and the second threshold lines are programmable Using threshold lines the SC140 core and the TDM can implement a double buffer handshake In addition the TDM generates an interrupt on frame start to the SC140 core which helps synchronize to the TDM system For transmits the SC140 core fills all the buffers belonging to a specific TDM interface and the ...

Page 51: ...ntion The transmitter takes data from the Tx FIFO and transmits data to the MAC The MAC transmits the data through the MII RMII SMII interface to the physical media Once initialized the transmitter runs until the end of frame EOF condition is detected unless a collision within the collision window occurs half duplex mode or an abort condition is encountered In addition to the MAC to PHY interface ...

Page 52: ... goes to tri state high impedance when driving a high voltage GPIO signals do not have internal pull up resistors Dedicated MSC8113 peripheral functions are multiplexed onto the shared external connections The functions are grouped to maximize connection use for the greatest number of MSC8113 applications Note For details see Chapter 23 GPIO 1 2 13 Reset and Boot The Hard Reset Configuration Word ...

Page 53: ...rupt pulse can be captured as well as an edge source in all of the LIC modules and each SC140 core can process the interrupt and clear the local status bit separately without unnecessary arbitration A global interrupt controller GIC concentrates interrupts from the SIU the UART and external signals and drives the INT_OUT signal It also generates the virtual interrupts for core to core and external...

Page 54: ...y writing the destination core number and the virtual interrupt number to a virtual interrupt register Each generated interrupt destination is programmable and can be forwarded to one or multiple destination SC140 cores Note For details see Chapter 17 Interrupt Processing 1 0 1 00 MII 0 1 64 32 MII 1 0 1 01 RMII 0 1 3 64 32 RMII 1 0 1 10 SMII 0 1 3 64 32 SMII 1 1 X None 0 1 2 3 64 32 Notes 1 Repre...

Page 55: ...the same location Snoopers also protect the M1 and the M2 memories which are accessible to both the SC140 cores and external hosts Note For details see Section 9 3 Extended QBus System 1 3 3 Hardware Semaphores There are eight coded hardware semaphores Each semaphore is an 8 bit register with a selective write protection mechanism When the register value is zero it is writable to any new value Whe...

Page 56: ...MSC8113 Reference Manual Rev 0 1 28 Freescale Semiconductor MSC8113 Overview ...

Page 57: ...mming model and instruction set list Note The information in this chapter is based on Revision 3 of the SC140 DSP Core Reference Manual To get the updates in later revisions of this manual visit the Freescale Web site shown on the back cover of this manual The 16 bit SC140 core packs four data arithmetic logic execution units ALUs each consisting of a multiply accumulate unit MAC a logic unit and ...

Page 58: ...n be kept busy on any given cycle and enabling programs to take better advantage of the SC140 core parallel architecture 2 1 Architecture This section discusses the main functional blocks of the SC140 core Figure 2 1 shows a block diagram of the core as used by the MSC8113 Note The SC140 DSP core defines the PLL Control Registers 0 1 PCTL 0 1 for PLL and clock control The MSC8113 does not use thes...

Page 59: ... a 40 bit barrel shifter Eight data bus shifter limiter circuits to allow limiting four 16 bit fractional words over each of the 64 bit data buses in a single cycle All the MAC units and BFUs can access all the Data ALU registers Each register is partitioned into three portions two 16 bit registers low and high portion of the register and one 8 bit register extension portion The 16 bit high and lo...

Page 60: ...clock cycle The destination of every arithmetic operation can be used as a source operand for the operation immediately following without any time penalty 2 1 1 2 Multiply Accumulate MAC Unit The MAC unit comprises the main arithmetic processing unit of each SC140 core and performs all the calculations on data operands The MAC unit outputs one 40 bit result in the form of Extension Most Significan...

Page 61: ...tions using the integer arithmetic necessary to address data operands in memory and it contains the registers to generate the addresses It performs four types of arithmetic linear modulo multiple wrap around modulo and reverse carry The AGU operates in parallel with other chip resources to minimize address generation overhead The AGU also generates change of flow program addresses and manages the ...

Page 62: ...AGU registers or PC to from an AGU register Add or subtract an immediate value to from an AGU register Compare to or test an AGU register Logical and arithmetic shift operations on AGU registers Sign or zero extend an AGU register Add with reverse carry Figure 2 3 AGU Block Diagram Program Counter PC Address R0 R1 R2 R3 R4 R5 R6 R7 N0 N1 N2 N3 PAB XABB XABA NSP ESP MCTL B0 R8 B1 R9 B2 R1 B3 R1 B4 ...

Page 63: ...tack pointers make it easier to support multitasking systems and optimizes stack usage for these systems 2 1 2 2 Bit Mask Unit BMU The BMU performs bit mask operations such as setting clearing changing or testing a destination according to an immediate mask operand Data is loaded to the BMU over the data memory buses XDBA or XDBB The result is written back over XDBA or XDBB to the destinations in ...

Page 64: ...e main units of the SC140 DSP core programming model are the Address Generation Unit AGU the Data Arithmetic Logic Unit Data ALU and the PSEQ see Figure 2 4 This section gives a brief overview of each of these units 2 2 1 AGU Programming Model The address registers can be programmed for linear modulo regular or multiple wrap around and bit reverse addressing Automatic updating of address registers...

Page 65: ...the implicit POP operations Note You must explicitly initialize both stack pointer registers after reset Offset Registers N 0 3 The 32 bit read write offset registers N 0 3 contain offset values to increment or decrement address registers in address register update calculations These registers are also used for 32 bit general purpose storage For example the contents of an offset register specify t...

Page 66: ...UNIT 7 0 15 0 15 0 D0 D0 e D0 h D0 I D1 D1 e D1 h D1 I D2 D2 e D2 h D2 I D3 D3 e D3 h D3 I D4 D4 e D4 h D4 I D5 D5 e D5 h D5 I D6 D6 e D6 h D6 I D7 D7 e D7 h D7 I D8 D8 e D8 h D8 I D9 D9 e D9 h D9 I D10 D10 e D10 h D10 I D11 D11 e D11 h D11 I D12 D12 e D12 h D12 I D13 D13 e D13 h D13 I D14 D14 e D14 h D14 I D15 D15 e D15 h D15 I ADDRESS GENERATION UNIT 31 0 R8 B0 R9 B1 R10 B2 R11 B3 R12 B4 R13 B5 ...

Page 67: ... written from the ALU to the Dx register The data registers are accessed with three types of data width A long word type access writing or reading 32 bit operands A word type access writing or reading 16 bit operands A byte type access writing or reading 8 bit operands Fractional data in Dx registers that is transferred to memory over XDBA and XDBB is replaced by a limiting constant if the value c...

Page 68: ...rogram Counter Register PC Status Register SR Four Start Address Registers SA 0 3 Four Loop Counter Registers LC 0 3 Exception and Mode Register EMR The EMR reflects and controls exception situations in the core It contains bits that reflect memory configuration servicing of a non maskable interrupt and the following exception conditions Data ALU overflow illegal execution set and illegal instruct...

Page 69: ...a register to immediate for greater than CMPHI Compare for higher unsigned DECEQ Decrement a data register and set T if zero DECGE Decrement a data register and set T if greater than or equal to zero DIV Divide iteration DMACSS Multiply signed by signed and accumulate with data register right shifted by word size DMACSU Multiply signed by unsigned and accumulate with data register right shifted by...

Page 70: ...actional multiply and round MPYSU Signed unsigned fractional multiply MPYUS Unsigned signed fractional multiply MPYUU Unsigned unsigned fractional multiply NEG Negate RND Round SAT F Saturate value in data register to fit in top 16 bits SAT L Saturate value in data register to fit in 32 bits SBC Subtract long with carry SBR Subtract and round SUB Subtract SUB2 Subtract two 16 bit values SUBL Shift...

Page 71: ...ight LSRW Word logical shift right 16 bit shift NOT Logical complement OR Logical inclusive OR ROL Rotate one bit left through the carry bit ROR Rotate one bit right through the carry bit SXT B Sign extend byte SXT L Sign extend long SXT W Sign extend word ZXT B Zero extend byte ZXT L Zero extend long ZXT W Zero extend word Table 2 4 AGU Arithmetic Instructions Instruction Description ADDA AGU add...

Page 72: ...ry to a register quadrant MOVE 4W Move four integer words to from a register quadrant MOVE B Move byte sign extended for memory reads MOVE F Move fractional word to and from memory MOVE L Move long sign extended for memory or register reads MOVE W Move integer word sign extended for memory reads MOVEF Move address register to address register depending on T bit of SR MOVES F Move fractional word t...

Page 73: ... BMCHG Bit mask change for a 16 bit operand BMCHG W Bit mask change for a 16 bit operand in memory BMCLR Bit mask clear for a 16 bit operand BMCLR W Bit mask clear for a 16 bit operand in memory BMSET Bit mask set for a 16 bit operand BMSET W Bit mask set for a 16 bit operand in memory BMTSET Bit mask test and set for a 16 bit operand BMTSET W Bit mask test and set for a 16 bit operand in memory B...

Page 74: ...Return from subroutine RTSD Return from subroutine delayed RTSTK Force restore PC from the stack updating SP RTSTKD Force restore PC from the stack updating SP delayed TRAP Execute a precise software exception Table 2 9 AGU Loop Control including Loop COF Instructions Instruction Description BREAK Terminate the loop and branch to an address CONT Jump to the start of the loop to start the next iter...

Page 75: ...ter the settings of system registers or cause the SC140 core to enter a freeze state that can only be released by reset The SC140 illegal instruction trap does not provide 100 percent protection against illegal instruction execution Table 2 10 AGU Program Control Instructions Instruction Description DEBUG Enter debug mode DEBUGEV Signal debug event DI Disable interrupts sets the DI bit in the stat...

Page 76: ...MSC8113 Reference Manual Rev 0 2 20 Freescale Semiconductor SC140 Core Overview ...

Page 77: ...roupings Functional Group Number of Signal Connections Detailed Description Power VDD VCC and GND 155 Table 3 2 on page 3 3 Clock 3 Table 3 3 on page 3 3 Reset and Configuration 4 Table 3 4 on page 3 3 DSI System Bus Ethernet and Interrupts 210 Table 3 1 on page 3 4 Memory Controller 16 Table 3 2 on page 3 16 General Purpose Input Output GPIO Time Division Multiplexed TDM Interface Universal Async...

Page 78: ...E M C S Y S 1 BCTL0 HCLKIN 1 1 BCTL1 CS5 GPIO0 CHIP_ID0 IRQ4 ETHTXD0 1 G P I O T D M E T H E R N E T T I M E R S I 2 C 3 BM 0 2 TC 0 2 BNKSEL 0 2 GPIO1 TIMER0 CHIP_ID1 IRQ5 ETHTXD1 1 1 ALE GPIO2 TIMER1 CHIP_ID2 IRQ6 1 4 PWE 0 3 PSDDQM 0 3 PBS 0 3 GPIO3 TDM3TSYN IRQ1 ETHTXD2 1 1 PSDA10 PGPL0 GPIO4 TDM3TCLK IRQ2 ETHTX_ER 1 1 PSDWE PGPL1 GPIO5 TDM3TDAT IRQ3 ETHRXD3 1 1 POE PSDRAS PGPL2 GPIO6 TDM3RSYN...

Page 79: ...ections except GNDSYN The user must provide adequate external decoupling capacitors GNDSYN System PLL Ground Ground dedicated for system PLL use The connection should be provided with an extremely low impedance path to ground Table 3 3 Clock Signals Signal Name Type Signal Description CLKIN Input Clock In Primary clock input to the MSC8113 PLL CLKOUT Output Clock Out The bus clock Reserved Input P...

Page 80: ...ter the hard reset state After the device enters a hard reset state it drives the signal as an open drain output SRESET Input Output Soft Reset When asserted as an input this signal causes the MSC8113 to enter the soft reset state After the device enters a soft reset state it drives the signal as an open drain output Table 3 5 DSI System Bus Ethernet and Interrupt Signals Signal Name Type Descript...

Page 81: ...nected HD40 D40 ETHRXD0 Input Output Input Output Input Host Data Bus 40 Bit 40 of the DSI data bus System Bus Data 40 For write transactions the bus master drives valid data on this line For read transactions the slave drives valid data on this bus Ethernet Receive Data 0 In MII and RMII modes bit 0 of the Ethernet receive data HD41 D41 ETHRXD1 Input Output Input Output Input Host Data Bus 41 Bit...

Page 82: ...utput Host Data Bus 46 Bit 46 of the DSI data bus System Bus Data 46 For write transactions the bus master drives valid data on this line For read transactions the slave drives valid data on this bus Ethernet Transmit Data 0 In MII and RMII modes bit 0 of the Ethernet transmit data HD47 D47 ETHTXD1 Input Output Input Output Output Host Data Bus 47 Bit 47 of the DSI data bus System Bus Data 47 For ...

Page 83: ...ta 54 For write transactions the bus master drives valid data on this line For read transactions the slave drives valid data on this bus Ethernet Transmit Data Enable In MII and RMII modes indicates that the transmit data is valid HD55 D55 ETHTX_ER Reserved Input Output Input Output Output Input Host Data Bus 55 Bit 55 of the DSI data bus System Bus Data 55 For write transactions the bus master dr...

Page 84: ...ta on this bus Ethernet Management Data In MII and RMII modes used for station management data input output HD60 D60 ETHCOL Reserved Input Output Input Output Input Output Input Host Data Bus 60 Bit 60 of the DSI data bus System Bus Data 60 For write transactions the bus master drives valid data on this line For read transactions the slave drives valid data on this bus Ethernet Collision In MII mo...

Page 85: ...s dual mode One bit per byte is used as a strobe for host write accesses Host Data Byte Strobe in Asynchronous single mode One bit per byte is used as a strobe for host read or write accesses Host Write Byte Enable In Synchronous dual mode One bit per byte is used to indicate a valid data byte for host write accesses Host Data Byte Enable in Synchronous single mode One bit per byte is used as a st...

Page 86: ...nternal bus masters and responds to addresses generated by external bus masters When the MSC8113 is in internal master bus mode these pins are used as address lines connected to memory devices and are controlled by the MSC8113 memory controller TT0 HA7 Input Output Bus Transfer Type 0 The bus master drives this pins during the address tenure to specify the type of the transaction Host Bus Address ...

Page 87: ...crementors controlled by the MSC8113 memory controller IRQ5 BADDR29 Input Output Interrupt Request 51 One of fifteen external lines that can request a service routine via the internal interrupt controller from the SC140 Bus Burst Address 291 There are five burst address output pins which are outputs of the memory controller These pins connect directly to burstable memory devices without internal a...

Page 88: ...ut Output Bus Transfer Start Assertion of this pin signals the beginning of a new address bus tenure The MSC8113 asserts this signal when one of its internal bus masters begins an address tenure When the MSC8113 senses that this pin is asserted by an external bus master it responds to the address bus tenure as required snoop if enabled access internal MSC8113 resources memory controller support AA...

Page 89: ...m Bus Data Parity 2 The agent that drives the data bus also drives the data parity signals The value driven on the data parity 2 pin should give odd parity odd number of ones on the group of signals that includes data parity 2 and D 16 23 DMA Acknowledge 2 The DMA drives this output to acknowledge the DMA transaction on the bus External Data Bus Grant 22 The MSC8113 asserts this pin to grant data ...

Page 90: ... signals that includes data parity 5 and D 40 47 DMA Acknowledge 4 The DMA drives this output to acknowledge the DMA transaction on the bus External Bus Grant 32 The MSC8113 asserts this pin to grant bus ownership to an external bus IRQ6 DP6 DREQ3 Input Input Output Input Interrupt Request 6 One of fifteen external lines that can request a service routine via the internal interrupt controller from...

Page 91: ...erted with each data beat movement When TA is asserted PSDVAL is always asserted However when PSDVAL is asserted TA is not necessarily asserted For example if the DMA initiates a double word 2 64 bits transaction to a memory device with a 32 bit port size PSDVAL is asserted three times without TA and finally both pins are asserted to terminate the transfer IRQ7 INT_OUT Input Output Interrupt Reque...

Page 92: ...ls the external address latch used in an external master bus PWE 0 3 PSDDQM 0 3 PBS 0 3 Output Output Output System Bus Write Enable Outputs of the bus general purpose chip select machine GPCM These pins select byte lanes for write operations System Bus SDRAM DQM From the SDRAM control machine These pins select specific byte lanes of SDRAM devices System Bus UPM Byte Select From the UPM in the mem...

Page 93: ...Input Input Output Output System GPCM TA Terminates external transactions during GPCM operation Requires an external pull up resistor for proper operation System Bus UPM Wait An external device holds this pin low to force the UPM to wait until the device is ready to continue the operation System Bus UPM General Purpose Line 4 One of six general purpose output lines from the UPM The values and timi...

Page 94: ...chip ID of the MSC8113 DSI It is sampled on the rising edge of PORESET signal Interrupt Request 4 One of fifteen external lines that can request a service routine via the internal interrupt controller from the SC140 core Ethernet Transmit Data 0 For MII or RMII mode bit 0 of the Ethernet transmit data GPIO1 TIMER0 CHIP_ID1 IRQ5 ETHTXD1 Input Output Input Output Input Input Output General Purpose I...

Page 95: ... two dedicated outputs For details see Chapter 23 GPIO TDM3 Transmit Frame Sync Transmit frame sync for TDM 3 See Chapter 20 TDM Interface Interrupt Request 1 One of fifteen external lines that can request a service routine via the internal interrupt controller from the SC140 Ethernet Transmit Data 2 For MII mode only bit 2 of the Ethernet transmit data In RMII or SMII mode this signal is reserved...

Page 96: ...eive Frame Sync The receive sync signal for TDM 3 As an input this can be the DATA_B data signal for TDM 3 For configuration details see Chapter 20 TDM Interface Interrupt Request 4 One of fifteen external lines that can request a service routine via the internal interrupt controller from the SC140 Ethernet Receive Data 2 For MII mode only bit 2 of the Ethernet receive data For RMII or SMII mode t...

Page 97: ...r 23 GPIO TDM2 Transmit frame Sync Transmit Frame Sync for TDM 2 For configuration details see Chapter 20 TDM Interface Interrupt Request 7 One of fifteen external lines that can request a service routine via the internal interrupt controller from the SC140 Ethernet Management Data Station management data input output line in MII RMII and SMII modes GPIO10 TDM2TCLK IRQ8 ETHRX_DV ETHCRS_DV NC Input...

Page 98: ...ed outputs For details see Chapter 23 GPIO TDM2 Receive Frame Sync The receive sync signal for TDM 2 As an input this can be the DATA_B data signal for TDM 2 For configuration details see Chapter 20 TDM Interface Interrupt Request 10 One of fifteen external lines that can request a service routine via the internal interrupt controller from the SC140 Ethernet Receive Data 1 In MII or RMII mode bit ...

Page 99: ... TDM1TCLK DONE1 DRACK1 Input Output Input Input Output Output General Purpose Input Output 16 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs For details see Chapter 23 GPIO TDM1 Transmit Clock Transmit Clock for TDM 1 For configuration details see Chapter 20 TDM Interface DMA Done 1 Signifies that the channel must be terminated If the DMA generat...

Page 100: ... Chapter 23 GPIO TDM1 Serial Receiver Data The receive data signal for TDM 1 As an input this can be the DATA_A data signal for TDM 1 For configuration details see Chapter 20 TDM Interface GPIO21 TDM0TSYN Input Output Input Output General Purpose Input Output 21 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs For details see Chapter 23 GPIO TDM0 T...

Page 101: ...put Input Output Input General Purpose Input Output 25 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs For details see Chapter 23 GPIO TDM0 Receive Clock The receive clock signal for TDM 0 As an input this can be the DATA_C data signal for TDM 0 For configuration details see Chapter 20 TDM Interface Interrupt Request 15 One of fifteen external lin...

Page 102: ...o dedicated outputs For details see Chapter 23 GPIO Timer 2 Each signal is configured as either input to the counter or output from the counter For the configuration of the pin direction refer to the MSC8113 Reference Manual External TIMER Clock An external timer can connect directly to the SIU as the SIU Clock I2 C Bus Data Line This is the data line for the I2 C bus GPIO31 TIMER3 SCL Input Outpu...

Page 103: ...n MII mode Sync Input In SMII mode is the sync signal input line ETHTX_CLK ETHREF_CLK ETHCLOCK Input Input Input Transmit Clock In MII mode provides the timing reference for transmit signals Reference Clock In RMII mode provides the timing reference Ethernet Clock In SMII mode provides the Ethernet clock signal ETHCRS ETHRXD Input Input Carrier Sense In MII mode indicates that either the transmit ...

Page 104: ... on the rising edge of TCK and has an internal pull up resistor TRST Input Test Reset Asynchronously initializes the test controller must be asserted during power up Table 3 10 Reserved Signals Signal Name Type Signal Description TEST Input Test Used for manufacturing testing You must connect this pin to GND Table 3 9 JTAG TAP Signals Continued Signal Name Type Signal Description ...

Page 105: ...d generation Clock synthesizer Power management 60x compatible system bus interface Flexible high performance memory controller Figure 4 1 SIU Block Diagram System Bus 32 Bit Address Memory Controller Control Local Bus Control CS Local Bus 32 Bit Address Configuration Counters System Bus Interface DSP SRAMs DMA Pin Multiplex Peripherals Interface Bridge 64 32 System Bus DSI msbs Reset Configuratio...

Page 106: ...asserted if the TA AACK response limit is exceeded This function can be disabled See Section 4 1 1 Bus Monitors Local bus monitor Monitors transfers between local bus internal masters and local bus slaves An internal TEA assertion occurs if the transfer time limit is exceeded This function can be disabled See Section 4 1 1 Bus Monitors Software watchdog timer The SIU watchdog timer can be associat...

Page 107: ...mpleted Following the data tenure the bus monitor idles if there is no pending transaction otherwise it reloads the time out value and resumes counting For address only transactions the bus monitor counts until AACK is asserted If the monitor times out for a standard bus transaction transfer error acknowledge TEA is asserted If the monitor times out for an address only transaction the bus monitor ...

Page 108: ... zero on PORESET or a hard reset but is unaffected by a soft reset Software initializes the time counter you should set the TIMERSCLK frequency to 8 192 Hz as explained in Section 4 1 2 TMCNT can be programmed to generate a maskable interrupt when the time value matches the value programmed in its associated alarm register The interrupt is generated on the last TMCNT clock before it transitions to...

Page 109: ...counter begins counting Setting PISCR PS creates a pending interrupt that remains pending until PS is cleared If PS is set again before being cleared the interrupt remains pending until PS is cleared Any write to the PITC stops the current countdown and the count resumes with the new value in PITC If PISCR PTE 0 the PIT cannot count and retains the old count value The PIT is unaffected by reads Fi...

Page 110: ...isabled If the SWT is not needed but the SWTE bit is sampled high you must clear SYPCR SWE to disable the SWT before it times out If the SWT is used and the SWTE bit is sampled low you should set SYPCR SWE to re enable the SWT This option allows you to achieve an unlimited time out period for the boot sequence with no chance of hard reset caused by SWT time out When enabled the SWT requires a spec...

Page 111: ... the entire sequence must start over Although the writes must occur in the correct order before a time out any number of instructions can execute between the writes This allows interrupts and exceptions to occur between the two writes when necessary Figure 4 6 shows a state diagram used by the SIU watchdog timer Although most software disciplines permit or even encourage the watchdog concept some ...

Page 112: ...CR SWE has a value of zero 0 at power on reset the modulus counter does not count General timers used as watchdog timers should be configured to work in periodic mode and count on the system bus clock or its derivative The time out period is programmed in the timer period register The interrupt lines are routed to the appropriate SC140 LIC For details on timer programming refer to Section 22 1 Tim...

Page 113: ... HD 44 45 D 44 45 NC HD 46 D 46 ETHTXD0 HD 47 D 47 ETHTXD1 HD 48 D 48 ETHTXD2 NC HD 49 D 49 ETHTXD3 NC HD 50 53 D 50 53 NC HD 54 D 54 ETHTX_EN HD 55 D 55 ETHTX_ER HD 56 D 56 ETHRX_DV ETHCRS_DV HD 57 D 57 ETHRX_ER HD 58 D 58 ETHMDC HD 59 D 59 ETHMDIO HD 60 D 60 ETHCOL HD 61 63 D 61 63 NC The least significant 32 data lines on this shared bus are configured during the power on reset configuration se...

Page 114: ...Bus Arbitration Level Registers LCL_ALRH and LCL_ACRL page 4 17 SIU Module Configuration Register SIUMCR page 4 17 Internal Memory Map Register IMMR page 4 20 System Protection Control Register SYPCR page 4 21 Software Service Register SWSR page 4 22 System Bus Transfer Error Status and Control Register 1 TESCR1 page 4 22 System Transfer Error Status and Control Register 2 TESCR2 page 4 24 Local B...

Page 115: ...DSBI 9 Disable System Bus on Internal Access Determines which internal system bus lines are reflected on the external system bus Note Address attribute lines are always reflected on the external system bus 0 Data and address lines for internal system bus transfers are reflected on the external system bus 1 Depends on the value of EBM as follows If EBM 0 neither data nor address lines for internal ...

Page 116: ...NPQM0 designates the type of master connected to the set of BR BG and DBG NPQM1 designates the type of master connected to the set of EXT_BR2 EXT_BG2 and EXT_DBG2 NPQM2 designates the type of master that is connected to the set of EXT_BR3 EXT_BG3 and EXT_DBG3 0 The bus master connected to the arbitration lines is an MSC8113 1 The bus master connected to the arbitration lines is not an MSC8113 19 2...

Page 117: ...ure compatibility PPC_ACR System Bus Arbiter Configuration Register Bit 0 1 2 3 4 5 6 7 DBGD EARB PRKM Type R W Reset 0 0 0 EARB 0 0 1 0 Boot 0 0 0 EARB 0 1 0 1 Table 4 4 PPC_ACR Bit Descriptions Name Reset Description Settings 0 1 00 Reserved Write to zero for future compatibility DBGD 2 0 Data Bus Grant Delay Specifies the minimum number of data tenure wait states for system bus master initiated...

Page 118: ...eld 1 Priority Field 2 Priority Field 3 Type R W Reset 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 Boot 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Priority Field 4 Priority Field 5 Priority Field 6 Priority Field 7 Type R W Reset 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 1 Boot 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 Table 4 4 PPC_ACR Bit Descriptions Continued Name Reset Description Sett...

Page 119: ...iority Field 12 Priority Field 13 Priority Field 14 Priority Field 15 Type R W Reset 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Boot 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 LCL_ACR Local Bus Arbiter Configuration Register Bit 0 1 2 3 4 5 6 7 DBGD PRKM Type R W Reset 0 0 0 0 0 0 1 0 Boot 0 0 0 0 0 0 1 1 Table 4 5 LCL_ACR Bit Descriptions Name Reset Description Settings 0 1 00 Reserved Write to zero for future compati...

Page 120: ... 11 12 13 14 15 Priority Field 0 Priority Field 1 Priority Field 2 Priority Field 3 Type R W Reset 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 Boot 0 0 0 0 0 1 0 0 1 1 0 1 1 0 1 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Priority Field 4 Priority Field 5 Priority Field 6 Priority Field 7 Type R W Reset 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 1 Boot 1 1 1 0 0 0 1 1 1 0 1 1 0 0 1 0 Table 4 5 LCL_ACR Bit Descri...

Page 121: ...eld 11 Type R W Reset 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 Boot 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Priority Field 12 Priority Field 13 Priority Field 14 Priority Field 15 Type R W Reset 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Boot 1 0 0 1 0 0 0 1 0 1 0 1 0 1 1 0 SIUMCR SIU Module Configuration Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BBD ESE PBSE INTOU...

Page 122: ... part of the reset configuration sequence It reflects the selected boot mode For details on different boot mode options refer to Table 6 1Boot Mode Selection on page 6 1 000 MSC8113 boots from system external memory 001 MSC8113 boots from External host DSI or Power PC 010 MSC8113 boots from TDM 011MSC8113 boots from UART 100MSC8113 boots from I2 C 101Reserved 110Reserved 111 Reserved TCPC 10 11 Tr...

Page 123: ...nitializes system memories and devices and enables all other masters MMR facilitates such a boot scheme MMR is configured through the hard reset configuration sequence See Chapter 5 Reset Typically system configuration identifies only one master as the boot device It initializes the system and then enables all other devices by writing 00 to MMR Note Do not mask the request of a master that is defi...

Page 124: ...ngs ISB 0 14 Internal Space Base Defines the base address of the internal memory space The value of ISB is configured at reset to one of six addresses the software can then change it to any value The default configuration maps ISB to address 0xF0000000 when ISBSEL bits in the HRCW are zero ISB defines the 15 MSBs of the memory map register base address IMMR itself is mapped into the internal memor...

Page 125: ...s It is programmed in a commonly changed layer and should be changed for all mask set changes The MSC8113 initial mask number is 0x00 SYPCR System Protection Control Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SWTC Type R W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BMT PBME LBME SWE SWRI SWP Type R W Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 SWTE 1 1 Ta...

Page 126: ...em reset to disable the software watchdog timer 0 Watchdog timer disabled 1 Watchdog timer enabled SWRI 30 1 Software Watchdog Reset Interrupt Select 0 Software watchdog timer causes a machine check interrupt to the core 1 Software watchdog timer causes a hard reset this is the default value after hard reset SWP 31 1 Software Watchdog Prescale Controls the divide by 2048 software watchdog timer pr...

Page 127: ...SCR2 PB indicates which byte lane caused the error TESCR2 BNK indicates which memory controller bank was accessed 3 4 0 Reserved Write to zero for future compatibility WP 5 0 Write Protect Error Indicates an attempted write to a system bus memory region defined as read only in the memory controller Note that this alone does not cause TEA assertion TEA is asserted by bus monitor time out EXT 6 0 Ex...

Page 128: ...SEB1 Internal Registers Error Indicates that an error occurred in a transaction to the MSC8113 internal registers 2 6 0 Reserved Write to zero for future compatibility LCL 7 0 Local Bus Bridge Error An error occurred in a transaction from the MSC8113 system bus to the local bus bridge The bridge is non burstable PB 8 15 0 Parity Error on Byte There are eight parity error status bits one per 8 bit ...

Page 129: ...the local bus monitor time out 1 4 0 Reserved Write to zero for future compatibility WP 5 0 Write Protect Error Indicates that a write was attempted to a local bus memory region that was defined as read only in the memory controller Note that this alone does not cause TEA assertion Usually in this case the bus monitor times out 6 0 Reserved Write to zero for future compatibility TC 7 9 0 Transfer ...

Page 130: ... bit is set when the value of the TMCNT equals the TMCNTAL value on the clock when TMCNT counts to ALARM 1 10 11 0 Reserved Write to zero for future compatibility SIE 12 0 Second Interrupt Enable Specifies whether the time counter generates an interrupt when SEC is set 0 The time counter does not generate an interrupt 1 The time counter generates an interrupt ALE 13 0 Alarm Interrupt Enable Enable...

Page 131: ... page 4 29 TMCNT Time Counter Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TMCNT Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TMCNT Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMCNTAL Time Counter Alarm Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ALARM Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24...

Page 132: ... Enable Enables or disables a periodic interrupt 0 The period interrupt timer does not generate an interrupt 1 The periodic interrupt timer generates an interrupt when PS 1 PTF 14 0 Periodic Interrupt Frequency The input clock to the periodic interrupt timer may be either 4 MHz or 32 KHz You should set the PTF bit according to the frequency of this clock See Section 4 1 2 Timers Clock 0 The input ...

Page 133: ...FFF selects the maximum count period 16 31 0 Reserved Write to zero for future compatibility PITR Periodic Interrupt Timer Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIT Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 16 PITR Bit Descriptions Name Reset Description PIT 0 15 0 Periodic Inte...

Page 134: ...MSC8113 Reference Manual Rev 0 4 30 Freescale Semiconductor System Interface Unit SIU ...

Page 135: ...13 During HRESET SRESET is asserted HRESET is an open drain output Upon hard reset HRESET and SRESET are driven the SC140 extended cores are reset and system configuration is sampled The most configurable features are reconfigure These features are defined in the 32 bit HRCW described in Section 5 6 1 Hard Reset Configuration Word on page 5 13 External soft reset SRESET I O Initiates the soft rese...

Page 136: ...nfiguration write through the System Bus Yes Yes No No HRESET Driven Yes Yes No No SIU Registers Yes Yes No No IPBus Modules Reset ETH TDM UART Timers DSI IPBus Master GIC HS and GPIO Yes Yes Yes Yes SRESET Driven Yes Yes Yes Depend on JTAG SC140 Extended Cores Reset PC points to boot starting address Yes Yes Yes Yes MQBS Reset Yes Yes Yes Yes Table 5 3 PORESET External Configuration Signals Signa...

Page 137: ...hernet pin multiplexing configuration please refer to Table 5 4 on page 5 3 DSISYNC DSI Synchronous Mode Input line sampled at the rising edge of PORESET This bit defines whether the DSI works in Synchronous or Asynchronous Mode For details refer to Section 14 3 2 Synchronous Versus Asynchronous Access Mode 0 Asynchronous mode 1 Synchronous mode CHIP_ID 0 3 Chip ID Input line sampled at the rising...

Page 138: ...T until the host writes the HRCW The host must write 32 bits to the HRCW which is 32 bits wide For details see Section 14 4 DSI Configuration on page 14 27 Note The hard reset sequence that is initiated by asserting the external HRESET or internal source bus monitor or software watch dog does not restart the reset configuration sequence through the DSI In this case the previous HRCW is kept See Se...

Page 139: ...nal connected to the DSI HCS signal and connect all the HCID signals of the DSI to a hard wired value that is the same as the value sampled during PORESET flow on the CHIP_ID signals The host should finish its own wake up reset sequence before waking up the slave For example when the host is an MSC8113 the RESET_OUT signal is HRESET Connecting all the HRESET signals of all the slaves ensures that ...

Page 140: ...eset configuration sequence requires 1024 CLKIN cycles In a typical multi MSC8113 system one MSC8113 acts as the configuration master and all other MSC8113 devices act as configuration slaves The configuration master reads the various HRCWs from external memory and uses them to configure itself as well as the configuration slaves If the MSC8113 is a configuration slave and the HRCW is not written ...

Page 141: ...LL pre divider After the SPLL is locked all the clocks to the MSC8113 are enabled Note Because the MSC8113 does not support DLL operation make sure that the HRCW DLLDIS bit is set During SPLL locking HRESET and SRESET are asserted After the SPLL is locked HRESET remains asserted for another 512 bus clocks and is then released The SRESET is released three bus clocks later The timing diagram in Figu...

Page 142: ...ains unchanged After the MSC8113 asserts HRESET and SRESET for 512 bus clock cycles it releases both signals and exits the hard reset sequence An external pull up resistor should deassert the signals After deassertion is detected a 16 bus cycle period is taken before testing for an external hard soft reset 5 4 Soft Reset A soft reset sequence is initiated externally when SRESET is asserted or inte...

Page 143: ...size The configuration sequence read from EPROM occurs during a hard reset When HRESET is deasserted exited the devices is assumed to be configured according to the EPROM Note An EPROM that is accessed for system reset configuration should connect using one of the following methods Connect directly to the MSC8113 without external buffer or glue logic Use a data buffer that drives the MSC8113 signa...

Page 144: ...on In a typical multi MSC8113 system one MSC8113 device acts as the configuration master and all other MSC8113 devices act as configuration slaves The configuration master reads the various HRCWs from EPROM and uses them to configure itself as well as the configuration slaves The reset mode that determines the MSC8113 behavior during reset configuration write through the system bus is specified by...

Page 145: ...mber of MSC8113 devices in the system Figure 5 6 shows a multi device configuration In this system the configuration master initially reads its own HRCW It then reads other HRCWs and drives them to the configuration slaves by asserting RSTCONF As Figure 5 6 shows this complex configuration is done without additional glue logic The configuration master controls the whole process by asserting the EP...

Page 146: ... A0 HRESET HRESET HRESET HRESET VCC Configuration Master PORESET EPROM EPROM Control Signals D 0 31 D 0 7 A 0 31 A Address Bus Data Bus Configuration Slave 1 D 0 31 Configuration Slave 2 D 0 31 Configuration Slave 7 D 0 31 RSTCONF CNFGS RSTCONF CNFGS 0 Value During PORESET A1 RSTCONF CNFGS A6 RSTCONF CNFGS CS0 CS MSC8113 MSC8113 MSC8113 MSC8113 ...

Page 147: ...as described in Section 14 4 DSI Configuration on page 14 27 When reset configuration is written through the system bus the reset configuration mechanism programs this register via the system bus port This register is not directly accessible to the SC140 cores Some bits programmed in this register affect bits in various registers that are accessible to the SC140 cores SIUMCR ACR BR0 BCR IMMR and c...

Page 148: ...rnal space IRPC 8 0 Interrupt Pin Configuration Defines the initial value of SIUMCR IRPC and burst address pin functionality See Section 4 2 SIU Programming Model 0 IRQ5 IRQ2 IRQ3 1 BADDR29 BADDR30 BADDR31 9 0 Reserved Write to zero for future compatibility DPPC 10 11 00 Data Parity Pin Configuration Defines the initial value of SIUMCR DPPC and DMA channel request acknowledge pin functionality See...

Page 149: ...CS5 functionality See Section 4 2 SIU Programming Model 0 CS5 BCTL1 pin is CS5 1 CS5 BCTL1 pin is BCTL1 TCPC 22 23 00 Transfer Code Pin Configuration Defines the initial value of SIUMCR TCPC and TC pin functionality See Section 4 2 SIU Programming Model 00 TC 0 2 01 Reserved 10 BNKSEL 0 2 11 Reserved LTLEND 24 0 Little Endian Defines the host Endian mode of operation See Section 14 2 4 DSI Endian ...

Page 150: ...RS is set and remains set until software clears it 0 No host reset command through JTAG occurred 1 A host reset command through JTAG occurred 27 0 Reserved Write to zero for future compatibility SWRS 28 0 Software Watchdog Reset Status When a software watchdog expire event which causes a reset is detected the SWRS bit is set and remains set until the software clears it 0 No software watchdog reset...

Page 151: ...sing edge of PORESET Table 6 1 shows the mode options for BM 0 2 This chapter begins with booting basics including the default values programmed by the boot program and interrupt handling during the boot process Then it considers different ways to boot the MSC8113 from an external memory device on the system bus from an external host located on the DSI or on the system bus port from the time divis...

Page 152: ...d to support the MSC8113 M1 and M2 memories Section 12 7 Internal SRAM and IPBus Peripherals Support on page 12 92 Table 8 7Banks 9 and 11 Address Space on page 8 28 Memory Controller Option Registers OR 9 11 Table 12 8Memory Controller Programming Model on page 12 95 Memory Controller Base Registers BR 9 11 System Bus and Local Bus Arbiter Configuration Section 4 2 SIU Programming Model on page 4...

Page 153: ...ection 12 3 3 See also Section 5 6 1 Hard Reset Configuration Word The boot program accesses an address table that resides at address 0xFE000110 see Table 6 3 This address table holds the 32 bit address of the user program in big endian format The retrieved address is user programmable and the target user program can be placed in any address in the space controlled by the chip select The MSC8113 d...

Page 154: ...ode and data to the internal memory according to the memory map shown in Figure 8 2 Host on the System Bus Memory Map View Example on page 8 4 The external host should poll the Valid bit V of the BR10 register The valid bit is set when the MSC8113 boot code finishes the default initialization and the external host can access the internal resources including internal memory When the external host f...

Page 155: ...ures the size and type T1 or non T1 of the received and transmitted frame by synchronizing to the TDM Clock and Sync signals of the master boot device Figure 6 1 TDM Boot System MSC8113 TDM C0 Chip ID n1 TDM Cn1 Boot Master Device TDM C0 TDM Cn1 Rx Data Tx Data TDM Cn2 TDM Cn3 Tx Clock Rx Clock Tx Sync Rx Sync MSC8113 TDM C0 Chip ID n2 TDM Cn2 MSC8113 TDM C0 Chip ID n3 TDM Cn3 TDM3TSYN TDM3RDAT TD...

Page 156: ...rst to be received The number of channels at the receiver frame is limited to 128 For a T1 receive operation the TDM0RDAT is sampled for eight consecutive clock cycles starting two clocks after each first clock on which the TDM3RSYN is detected high See Figure 6 4 Figure 6 2 Receive Frame Non T1 Configuration Figure 6 3 16 bit Receive Frame Non T1 Configuration data sampled sync sample TDMxRCLK TD...

Page 157: ...o be sent For a T1 transmit operation 8 bit channels are transmitted on the TDM3TDAT signal in consecutive clock cycles starting on the negative edge of the second clock after which the Figure 6 4 Receive Frame T1 Configuration Figure 6 5 Transmit Frame Non T1 Configuration data sampled sync sample TDM0RCLK TDM0RSYN TDM0RDAT Channel number One Cycle Sync Delay DO D1 D2 D3 D4 D5 D6 D7 Dn FA FA Dn D...

Page 158: ...wledge message contains the fields described in Table 6 5 Figure 6 6 Transmit Frame T1 Configuration Table 6 4 Block Transfer Message Block Transfer Message Direction from Master Boot Chip Field Size Field Name Field Value Description 4 bytes PRM 0x44332211 Preamble Indicates the start of the message A value of 0x44332211 first byte sent is 0x11 is assigned to the block transfer message BTM and a ...

Page 159: ...he HCRC field is a CRC 16 calculation of the BTM headers fields PRM PLDS SN EB DCID and DA fields The CRC field is a CRC 16 calculation of the PLD field in the BTM message The ACRC field is a CRC 16 calculation of the APRM SCID and RN fields Table 6 5 Block Transfer Acknowledge Message Block Transfer Acknowledge Message Direction from MSC8113 Slave Chip Field Size Field Name Field value Descriptio...

Page 160: ... in the SCID field 5 If the CRC field is received with no error the RN value is correct and the end block EB field flag is set the MSC8113 slave device finishes the TDM boot session and all its SC140 cores jump to address 0x0 of their M1 memory Otherwise return to step 1 The TDM boot master device works in two modes Handshake mode Use the stop and wait technique to send the BTM messages and wait f...

Page 161: ...ximum rate available at the TDM port Figure 6 7 MSC8113 Logic Layer Algorithm Sync to PRM of BTM HCRC OK Write PLD data to CRC OK Y Y Send BTAM with RN End Block flag End TDM boot session RN SN RN RN 1 Y DCID Y Y N N N N my CHIP ID BroadCast or EB N Destination Address DA Send BTAM with RN and SCID with my CHIP ID Send BTAM with RN and SCID with my CHIP ID and SCID with my CHIP ID ...

Page 162: ...t Device First Block DCID 2 DA 0x02001000 EB 0 Second Block DCID 7 DA 0x02005000 EB 0 Third Block DCID 7 DA 0x02002000 EB 1 Fourth Block DCID 0xFF DA 0x02000760 EB 0 Fifth Block DCID 2 DA 0x02011000 EB 1 Sixth Block DCID 0xFF DA 0x02012000 EB 1 Data block is not written to device number 7 Data block is not written to device number 2 and 7 ...

Page 163: ... a UART physical layer and a UART logical layer handshake see Section 6 4 2 TDM Logical Layer Handshake on page 6 8 The broadcast message handshake capability of the TDM logical layer is not allowed in the UART logical layer The Valid bit of Bank 10 BR10 is asserted at the end of the UART session Figure 6 9 UART Boot System MSC8113 UART Rx Chip ID n1 UART Tx TxD RxD MSC8113 UART Rx Chip ID n3 UART...

Page 164: ...Chapter 24 I C Software Module that is implemented in the boot code The I2C slave device address is 1010A0A1A2b where the A0A1A2 bits are the high bits of the address being retrieved The address field is 19 bit 3 additional bits from the I2C slave device address thus enable accesses of up to 1 MB of memory array In a multi master environment the I2C SM allows concurrent starts of block retrieves s...

Page 165: ...ata up to 224 bytes Block_Address 0xc The PayLoad Data holds up to 224 bytes of data to be written to on device memory according to the DSS field in the Block Control field To write to the internal memory in Big Endian mode the most significant byte of the data structure must be stored at the lower address Checksum 2 bytes Block_Address Block_Size 0xc Checksum is a 2 byte field that holds the XOR ...

Page 166: ...ation lost Yes No Update HIGH_PERIOD from address 0x01076f00 Update HALF_LOW_PERIOD from address 0x01076f04 Wrong ACK bit Start Stop condition I2 C arbitration lost Wrong ACK bit Start Stop condition WaitFor_BusFreeTim WaitFor_StartCond_WakeUpTime CheckSum OK SCL 0 T Bit 0 Set GPIO SCL SDA to HIGH Init HIGH_PERIOD and HALF_LOW_PERIOD Yes No Yes Prepare Next Block Address Next Block Addr 0xFFFFFFFF...

Page 167: ...L is low does not equal the bit received on SDA when SCL is high Each I2 C master checks this only when it transmits a bit 3 The ACK bit is not as expected On read session ACK is low for all except the last byte 6 6 2 I2 C System Figure 6 11 shows the system connectivity for I2C devices Figure 6 11 I2 C Boot System Example SDA I2 C Master I2 C Master I2C Master SCL SDA SCL SCL SCL MSC8113 MSC8113 ...

Page 168: ...MSC8113 Reference Manual Rev 0 6 18 Freescale Semiconductor Boot Program ...

Page 169: ...Some MSC8113 subsystems are clocked by other special clocks as follows The direct slave interface DSI has two clearly separated clock zones It interfaces with the external host asynchronously or via a synchronous interface clocked by the HCLKIN signal It interfaces with the internal local bus via the BUSES_CLOCK Each TDM has three clock zones The receiver is clocked by RCLKx The transmitter is clo...

Page 170: ... factors as configured by the System Clock Mode Status Register SCMSR see Section 7 4 Clocks Programming Model The PLLPDF field divides the frequency by 1 or 2 The PLL VCO clock is generated by multiplying the PLL predivider clock by 2 PLLFDF PLLODF BUSDF The PLL output clock is generated by dividing the PLL VCO clock by 2 PLLODF The SCMSR BUSDF bit value controls the frequency ratio between the B...

Page 171: ...s for example With this method the CLKOUT of each MSC8113 device connects through a zero delay buffer to the clock input pin of its dedicated slave devices on the board Figure 7 3 illustrates a system in which each of three MSC8113 devices connects to a dedicated SDRAM memory device on the board through the zero delay buffers You must maintain the following guidelines for this mode Clocks marked w...

Page 172: ...CLKIN is provided by one or more on board oscillators and connects via the on board balanced clock tree to the CLKIN input of each MSC8113 device and clock input of the dedicated slave devices You must choose one of the clock configuration modes for which the BUSES_CLOCK CLKIN ratio is 1 1 modes 0 7 15 19 21 23 or 28 31 in Table 7 1 Figure 7 5 illustrates a system in which three MSC8113 devices an...

Page 173: ...le The CLKOUT of the master MSC8113 device connects through a zero delay buffer to the clock input pins of the shared slave devices on the board Figure 7 6 illustrates a system in which three MSC8113 devices connect to the one shared SDRAM memory device on the board Note Clocks marked with the same number of parallel lines should use an equivalent buffer and route on the board Figure 7 5 MSC8113 C...

Page 174: ...tes a system in which three MSC8113 devices and also three shared SDRAM memory devices connect on the board Note Clocks marked with the same number of parallel lines should use an equivalent buffer and route on the board Figure 7 6 MSC8113 Clock Distribution Using CLKOUT in Multi Master Mode Figure 7 7 MSC8113 Clock Distribution in Multi Master Mode Using CLKIN Example OSC Buffer SDRAM Res CLKOUT ...

Page 175: ...ized during the reset configuration sequence The clock configuration changes only after PORESET is asserted You can select a configuration to provide the required frequencies for an existing clock or define the clock setting to achieve the performance required The following five factors can be configured see Section 7 4 Clocks Programming Model on page 7 10 SPLL input clock division factor PLLRDF ...

Page 176: ...US CLKIN Ratio Core Bus Ratio 0 000 00 2 2 2 5 3 1x 3x 1 000 01 1 2 2 5 3 2x 3x 2 000 10 1 2 2 7 4 2x 4x 3 000 11 1 4 1 7 4 4x 4x 4 001 00 1 3 2 8 3 3x 3x 5 001 01 1 4 2 11 3 4x 3x 6 001 10 1 3 2 11 4 3x 4x 7 001 11 2 2 1 3 4 1x 4x 8 010 00 1 2 1 3 4 2x 4x 9 010 01 1 4 1 7 4 4x 4x 10 010 10 1 2 2 5 3 2x 3x 11 010 11 2 3 2 11 4 1 5x 4x 12 011 00 Reserved 13 011 01 1 2 2 7 4 2x 4x 14 011 10 1 2 2 9 ...

Page 177: ... 100 MHz 10 2x 3x 33 33 MHz 200 MHz 66 67 MHz 66 67 MHz 400 MHz 133 33 MHz 11 1 5x 4x 40 MHz 240 MHz 60 MHz 66 67 MHz 400 MHz 100 MHz 12 Reserved 13 2x 4x 25 MHz 200 MHz 50 MHz 50 MHz 400 MHz 100 MHz 14 2x 5x 20 MHz 200 MHz 40 MHz 40 MHz 400 MHz 80 MHz 15 1x 5x 80 MHz 400 MHz 80 MHz 100 MHz 500 MHz 100 MHz 16 2x 5x 40 MHz 400 MHz 80 MHz 17 3x 5x 26 67 MHz 400 MHz 80 MHz 18 2x 6x 20 MHz 240 MHz 40 ...

Page 178: ...PLLTP 8 11 Configuration Signal Unaffected SPLL Loop Bandwidth Tuning Field 0011 Tuning Factor 3 0010 Tuning Factor 4 0101 Tuning Factor 5 0111 Tuning Factor 7 1000 Tuning Factor 8 1001 Tuning Factor 9 1011 Tuning Factor 11 All other combinations are not used 12 16 0 Reserved PLLRDF 17 18 Configuration Signal Unaffected SPLL Input Clock Division Factor 00 SPLL RDF 1 01 SPLL RDF 2 All other combina...

Page 179: ... 0 Reserved BUSDF 28 31 Configuration Signal Unaffected 60x Bus Division Factor 0010 Bus DF 3 0011 Bus DF 4 0100 Bus DF 5 0101 Bus DF 6 0111 Bus DF 8 1001 Bus DF 10 All other combinations are not used Table 7 3 SCMR Bit Descriptions Continued Name Defaults Description Settings POR Hard Reset ...

Page 180: ...MSC8113 Reference Manual Rev 0 7 12 Freescale Semiconductor Clocks ...

Page 181: ...ddress space as described in Chapter 11 SQBus see Table 8 5 IPBus address space Each SC140 core or an external host on the system bus or DSI can access this space as well as boot from an I2C TDM or UART device It maps the TDMs timers UART DSI hardware semaphores Ethernet and GIC control registers see Table 8 6 System bus address space All three SC140 cores and an external host can access this addr...

Page 182: ...SBSEL field equals 0 This figure is an example only the ISBSEL field value is programmable Table 8 1 Address Spaces Master Device SC140 core Internal QBUS MQBUS SQBUS IPBus System Bus System Registers Local Bus Pseudo Command SC140 Core Host on System Bus Host on DSI TDM DMA Ethernet TDM boot UART boot I2 C Boot Note The UART boot TDM boot UART boot and I2 C boot view of the SC140 core internal sp...

Page 183: ...0000000 0xF001FFFF System Registers M1 Memory EOnCE modules M2 Memory Boot ROM LIC PIC ICache EQBS Note System bus internal accesses to addresses in the range 0x02000000 0x021BFFFF are controlled by the memory controller banks 9 or 11 as appropriate Internal accesses outside that range but controlled by the QBus Bank 3 above address 0x01800000 are See Table 8 8 for a detailed listing of the local ...

Page 184: ...2 Host on the System Bus Memory Map View Example Figure 8 3 Host Accessing through the DSI Memory Map 0xFFFFFFFF 0x02000000 0x021BFFFF System Bus Local Bus 0x02180000 Bank 11 M1 and M2 Bank 9 IPBus 0xF0000000 0xF001FFFF System Registers See Table 8 8 for a detailed listing of the local bus address map The initial addresses of this bus are set by the ISBSEL bits in the HRCW at reset 0x0217FFFF 0x00...

Page 185: ...5 shows the memory map as viewed by the DMA and the Ethernet controllers Figure 8 4 TDM View Memory Map Figure 8 5 DMA and Ethernet Controller Memory Map 0x00000000 Local Bus Bank 11 M1 and M2 See Table 8 8 for a detailed listing of the bank 11 in the local bus address map The initial addresses of this bus are set by the ISBSEL bits in the HRCW at reset 0x0017FFFF 0xFFFFFFFF 0x02000000 System Bus ...

Page 186: ...ory Map View 0x00000000 0x00EFFFFF 0x00F00000 0x00FFFFFF 0x01000000 0x017FFFFF 0x01800000 Internal Core QBus Bank 0 QBus Bank 1 QBus Bank 3 0xFFFFFFFF 0x01F80000 0x01FBFFFF 0x02000000 0x021BFFFF System Bus Local Bus 0x02180000 M1 and M2 IPBus IPBus M1 Memory EOnCE modules M2 Memory Boot ROM LIC PIC ICache EQBS See Table 8 4 See Table 8 3 See Table 8 2 0x0217FFFF 0x021C0000 0x021DFFFF System Regist...

Page 187: ...FFFF 0x01000000 0x017FFFFF 0x01800000 Internal Core QBus Bank 0 QBus Bank 1 QBus Bank 3 0xFFFFFFFF 0x01F80000 0x01FBFFFF 0x04000000 0x041BFFFF System Bus Local Bus 0x04180000 M1 and M2 IPBus IPBus M1 Memory EOnCE modules M2 Memory Boot ROM LIC PIC ICache EQBS See Table 8 4 See Table 8 3 See Table 8 2 0x0417FFFF 0x021C0000 0x021DFFFF System Registers Core 0 Core 0 at bank 11 256 KB starting at bank...

Page 188: ...smit Register MSBs 4 00EFFE18 EE_CTRL EE Signals Control Register 2 00EFFE1C PC_EXCP Exception PC Register 4 00EFFE20 PC_NEXT PC of next execution set 4 00EFFE24 PC_LAST PC of last execution set 4 00EFFE28 PC_DETECT PC Breakpoint Detection Register 4 00EFFE2C 00EFFE39 Reserved 00EFFE40 EDCA0_CTRL EDCA0 Control Register 2 00EFFE44 EDCA1_CTRL EDCA1 Control Register 2 00EFFE48 EDCA2_CTRL EDCA2 Contro...

Page 189: ... Reserved 00EFFEE0 EDCD_CTRL EDCD Control Register 2 00EFFEE4 EDCD_REF EDCD Reference Register 4 00EFFEE8 EDCD_MASK EDCD Mask Register 4 00EFFEEC 00EFFEFF Reserved 00EFFF00 ECNT_CTRL EOnCE Counter Control Register 2 00EFFF04 ECNT_VAL EOnCE Counter Value 4 00EFFF08 ECNT_EXT EOnCE Extension Counter Value 4 00EFFF0C 00EFFF1F Reserved 00EFFF20 ESEL_CTRL EOnCE Selector Control Register 1 00EFFF24 ESEL_...

Page 190: ... Edge Level Triggered Interrupt Register E 2 00F09C28 ELIRF Edge Level Triggered Interrupt Register F 2 00F09C30 IPRA Interrupt Pending Register A 2 00F09C38 IPRB Interrupt Pending Register B 2 00F09C40 00F0ABFF Reserved 00F0AC00 LICAICR0 LIC Group A Interrupt Configuration Register 0 2 00F0AC08 LICAICR1 LIC Group A Interrupt Configuration Register 1 2 00F0AC10 LICAICR2 LIC Group A Interrupt Confi...

Page 191: ... 00F0FF1F Reserved 00F0FF20 EQBSBR EQBS Bank Register 2 00F0FF22 00F0FF2F Reserved 00F0FF30 ICACR Instruction Cacheable Area Control Register 2 00F0FF32 ICABR Instruction Cacheable Area Base Register 2 00F0FF34 00F0FF3F Reserved 00F0FF60 IFUR Instruction FU Configuration Register 2 00F0FF62 00F0FF7F Reserved 00F0FF80 WBFR WB Flush Register 2 00F0FF82 WBCR WB Control Register 2 00F0FF84 00F0FF9F Re...

Page 192: ...ressing Table 8 4 QBus Bank 1 MQBus Memory Map 0x01000000 0x017FFFFF Address Acronym Name Size in KB 01000000 01076FFF M2MEM M2 Memory 476 01077000 01077FFF BOOTROM MSC8113 Boot ROM 4 01078000 017FFFFF Reserved Table 8 5 QBus Bank 3 Memory Map 0x01800000 0xFFFFFFFF Address Descriptor Name Size 01800000 01F7FFFF Reserved 01F80000 01FBFFFF IPBus IPBus Address Space 256 KB 01FC0000 01FEFFFF Reserved ...

Page 193: ...mit Control Register 4 01F83FA8 TDM0RCR TDM0 Receive Control Register 4 01F83FB0 TDM0ACR TDM0 Adaptation Control Register 4 01F83FB8 TDM0TGBA TDM0 Transmit Global Base Address 4 01F83FC0 TDM0RGBA TDM0 Receive Global Base Address 4 01F83FC8 TDM0TDBS TDM0 Transmit Data Buffer Size 4 01F83FD0 TDM0RDBS TDM0 Receive Data Buffer Size 4 01F83FD8 TDM0TFP TDM0 Transmit Frame Parameters 4 01F83FE0 TDM0RFP T...

Page 194: ...mit Global Base Address 4 01F87FC0 TDM1RGBA TDM1 Receive Global Base Address 4 01F87FC8 TDM1TDBS TDM1 Transmit Data Buffer Size 4 01F87FD0 TDM1RDBS TDM1 Receive Data Buffer Size 4 01F87FD8 TDM1TFP TDM1 Transmit Frame Parameters 4 01F87FE0 TDM1RFP TDM1 Receive Frame Parameters 4 01F87FE8 TDM1TIR TDM1 Transmit Interface Register 4 01F87FF0 TDM1RIR TDM1 Receive Interface Register 4 01F87FF8 TDM1GIR T...

Page 195: ...ata Buffer Size 4 01F8BFD8 TDM2TFP TDM2 Transmit Frame Parameters 4 01F8BFE0 TDM2RFP TDM2 Receive Frame Parameters 4 01F8BFE8 TDM2TIR TDM2 Transmit Interface Register 4 01F8BFF0 TDM2RIR TDM2 Receive Interface Register 4 01F8BFF8 TDM2GIR TDM2 General Interface Register 4 01F8C000 01F8C7FF TDM3 Receive Local Memory 2 K 01F8C800 01F8CFFF Reserved 01F8D000 01F8D3FC TDM3 RCPR 0 255 TDM3 Receive Channel...

Page 196: ...DM3 Transmit Interface Register 4 01F8FFF0 TDM3RIR TDM3 Receive Interface Register 4 01F8FFF8 TDM3GIR TDM3 General Interface Register 4 01F90000 01FB800F Reserved 01FB8010 IEVENT Interrupt Event Register 4 01FB8014 IMASK Interrupt Mask Register 4 01FB8018 01FB801F Reserved 01FB8020 ECNTRL Ethernet Control Register 4 01FB8024 MINFLR Minimum Frame Length Register 4 01FB8028 PTV Pause Time Value Regi...

Page 197: ...t of sequence 32 Bytes TxBD Reserved Register 4 01FB82C8 OS32IIL Out of sequence 32 Bytes TxBD Insert Index length Register 4 01FB82CC 01FB82FF Reserved 01FB8300 RCTRL Receive Control Register 4 01FB8304 RSTAT Receive Status Register 4 01FB8308 01FB830B Reserved 01FB830C RBDLEN RxBD Data Length 4 01FB8310 01FB8323 Reserved 01FB8324 CRBPTRL Current RxBD Pointer 4 01FB8328 01FB833F Reserved 01FB8340...

Page 198: ...1FB8544 MACSTADDR2R MAC Station Address Part 2 Register 4 01FB8548 01FB867F Reserved 01FB8680 TR64 Transmit And Receive 64 byte Frame Counter 4 01FB8684 TR127 Transmit and Receive 65 to 127 byte Frame Counter 4 01FB8688 TR255 Transmit and Receive 128 to 255 byte Frame Counter 4 01FB868C TR511 Transmit and Receive 256 to 511 byte Frame Counter 4 01FB8690 TR1K Transmit and Receive 512 to 1023 byte F...

Page 199: ... Transmit Total Collision Counter 4 01FB8714 01FB8717 Reserved 01FB8718 TJBR Transmit Jabber Frame Counter 4 01FB871c TFCS Transmit FCS Error Counter 4 01FB8720 TXCF Transmit Control Frame Counter 4 01FB8724 TOVR Transmit Oversize Frame Counter 4 01FB8728 TUND Transmit Undersize Frame Counter 4 01FB872c TFRG Transmit Fragments Frame Counter 4 01FB8730 CAR1 Carry Register One 4 01FB8734 CAR2 Carry ...

Page 200: ... 01FB8930 PCNTRL1 Pattern Control 1 Register 4 01FB8934 01FB8937 Reserved 01FB8938 PATTRB1 Pattern Attributes 1 Register 4 01FB8940 PMD2 Pattern Match Data 2 4 01FB8944 01FB8947 Reserved 01FB8948 PMASK2 Pattern Mask 2 Register 4 01FB894C 01FB894F Reserved 01FB8950 PCNTRL2 Pattern Control 2 Register 4 01FB8954 01FB8957 Reserved 01FB8958 PATTRB2 Pattern Attributes 2 Register 4 01FB8960 PMD3 Pattern ...

Page 201: ...01FB89EC 01FB89EF Reserved 01FB89F0 PCNTRL7 Pattern Control 7 Register 4 01FB89F4 01FB89F7 Reserved 01FB89F8 PATTRB7 Pattern Attributes 7 Register 4 01FB8A00 PMD8 Pattern Match Data 8 4 01FB8A04 01FB8A07 Reserved 01FB8A08 PMASK8 Pattern Mask 8 Register 4 01FB8A0C 01FB8A0F Reserved 01FB8A10 PCNTRL8 Pattern Control 8 Register 4 01FB8A14 01FB8A17 Reserved 01FB8A18 PATTRB8 Pattern Attributes 8 Registe...

Page 202: ...ttern Mask 13 Register 4 01FB8AAC 01FB8AAF Reserved 01FB8AB0 PCNTRL13 Pattern Control 13 Register 4 01FB8AB4 01FB8AB7 Reserved 01FB8AB8 PATTRB13 Pattern Attributes 13 Register 4 01FB8AC0 PMD14 Pattern Match Data 14 4 01FB8AC4 01FB8AC7 Reserved 01FB8AC8 PMASK14 Pattern Mask 14 Register 4 01FB8ACC 01FB8ACF Reserved 01FB8AD0 PCNTRL14 Pattern Control 14 Register 4 01FB8AD4 01FB8AD7 Reserved 01FB8AD8 P...

Page 203: ...nal Interrupt Enable Register 4 01FBC028 GCIER GIC Core Interrupt Enable Register 4 01FBC030 GISR GIC Interrupt Status Register 4 01FBC038 01FBC0FF Reserved 01FBC100 HSMPR0 Hardware Semaphore Register 0 4 01FBC108 HSMPR1 Hardware Semaphore Register 1 4 01FBC110 HSMPR2 Hardware Semaphore Register 2 4 01FBC118 HSMPR3 Hardware Semaphore Register 3 4 01FBC120 HSMPR4 Hardware Semaphore Register 4 4 01F...

Page 204: ...onfiguration Register of Timer A4 4 01FBF028 TCFRA5 Timer Configuration Register of Timer A5 4 01FBF030 TCFRA6 Timer Configuration Register of Timer A6 4 01FBF038 TCFRA7 Timer Configuration Register of Timer A7 4 01FBF040 TCFRA8 Timer Configuration Register of Timer A8 4 01FBF048 TCFRA9 Timer Configuration Register of Timer A9 4 01FBF050 TCFRA10 Timer Configuration Register of Timer A10 4 01FBF058...

Page 205: ...ontrol Register of Timer A10 4 01FBF158 TCRA11 Timer Control Register of Timer A11 4 01FBF160 TCRA12 Timer Control Register of Timer A12 4 01FBF168 TCRA13 Timer Control Register of Timer A13 4 01FBF170 TCRA14 Timer Control Register of Timer A14 4 01FBF178 TCRA15 Timer Control Register of Timer A15 4 01FBF180 TCNRA0 Timer Count Register of Timer A0 4 01FBF188 TCNRA1 Timer Count Register of Timer A1...

Page 206: ...13 Timer Configuration Register of Timer B13 4 01FBF470 TCFRB14 Timer Configuration Register of Timer B14 4 01FBF478 TCFRB15 Timer Configuration Register of Timer B15 4 01FBF480 TCMPB0 Timer Compare Register of Timer B0 4 01FBF488 TCMPB1 Timer Compare Register of Timer B1 4 01FBF490 TCMPB2 Timer Compare Register of Timer B2 4 01FBF498 TCMPB3 Timer Compare Register of Timer B3 4 01FBF4A0 TCMPB4 Tim...

Page 207: ...Register of Timer B0 4 01FBF588 TCNRB1 Timer Count Register of Timer B1 4 01FBF590 TCNRB2 Timer Count Register of Timer B2 4 01FBF598 TCNRB3 Timer Count Register of Timer B3 4 01FBF5A0 TCNRB4 Timer Count Register of Timer B4 4 01FBF5A8 TCNRB5 Timer Count Register of Timer B5 4 01FBF5B0 TCNRB6 Timer Count Register of Timer B6 4 01FBF5B8 TCNRB7 Timer Count Register of Timer B7 4 01FBF5C0 TCNRB8 Time...

Page 208: ...d 11 Address Space ISBSEL Bank 9 Base Address Bank 11 Base Address 0 02180000 021BFFFF 02000000 0217FFFF 1 02380000 023BFFFF 02200000 0237FFFF 2 02580000 025BFFFF 02400000 0257FFFF 3 02780000 027BFFFF 02600000 0277FFFF 6 02D80000 02DBFFFF 02C00000 02D7FFFF 7 02F80000 02FBFFFF 02E00000 02F7FFFF Table 8 8 Local Bus Banks 9 11 Memory Map Address for ISB Acronym Name Size in Bytes 000 001 010 011 110 ...

Page 209: ...02380800 02380FFF 02580800 02580FFF 02780800 02780FFF 02D80800 02D80FFF 02F80800 02F80FFF Reserved 02181000 021813FC 02381000 023813FC 02581000 025813FC 02781000 027813FC 02D81000 02D813FC 02F81000 02F813FC TDM0 RCPR 0 255 TDM0 Receive Channel Parameters Register 0 255 4 each 02181400 021817FF 02381400 023817FF 02581400 025817FF 02781400 027817FF 02D81400 02D817FF 02F81400 02F817FF Reserved 021818...

Page 210: ...83F88 02383F88 02583F88 02783F88 02D83F88 02F83F88 TDM0RDBST TDM0 Receive Data Buffer Second Threshold 4 02183F90 02383F90 02583F90 02783F90 02D83F90 02F83F90 TDM0TDBFT TDM0 Transmit Data Buffer First Threshold 4 02183F98 02383F98 02583F98 02783F98 02D83F98 02F83F98 TDM0RDBFT TDM0 Receive Data Buffer First Threshold 4 02183FA0 02383FA0 02583FA0 02783FA0 02D83FA0 02F83FA0 TDM0TCR TDM0 Transmit Cont...

Page 211: ... Transmit Local Memory 2 K 02186000 021867FF 02386000 023867FF 02586000 025867FF 02786000 027867FF 02D86000 02D867FF 02F86000 02F867FF Reserved 02186800 02186BFC 02386800 02386BFC 02586800 02586BFC 02786800 02786BFC 02D86800 02D86BFC 02F86800 02F86BFC TDM1 TCPR 0 255 TDM1 Transmit Channel Parameters Register 0 255 4 each 02186C00 02187F1F 02386C00 02387F1F 02586C00 02587F1F 02786C00 02787F1F 02D86...

Page 212: ... 02F87FA8 TDM1RCR TDM1 Receive Control Register 4 02187FB0 02387FB0 02587FB0 02787FB0 02D87FB0 02F87FB0 TDM1ACR TDM1 Adaptation Control Register 4 02187FB8 02387FB8 02587FB8 02787FB8 02D87FB8 02F87FB8 TDM1TGBA TDM1 Transmit Global Base Address 4 02187FC0 02387FC0 02587FC0 02787FC0 02D87FC0 02F87FC0 TDM1RGBA TDM1 Receive Global Base Address 4 02187FC8 02387FC8 02587FC8 02787FC8 02D87FC8 02F87FC8 TD...

Page 213: ...ter 4 0218BF28 0238BF28 0258BF28 0278BF28 02D8BF28 02F8BF28 TDM2RSR TDM2 Receive Status Register 4 0218BF30 0238BF30 0258BF30 0278BF30 02D8BF30 02F8BF30 TDM2ASR TDM2 Adaptation Status Register 4 0218BF38 0238BF38 0258BF38 0278BF38 02D8BF38 02F8BF38 TDM2TER TDM2 Transmit Event Register 4 0218BF40 0238BF40 0258BF40 0278BF40 02D8BF40 02F8BF40 TDM2RER TDM2 Receive Event Register 4 0218BF48 0238BF48 02...

Page 214: ... Transmit Frame Parameters 4 0218BFE0 0238BFE0 0258BFE0 0278BFE0 02D8BFE0 02F8BFE0 TDM2RFP TDM2 Receive Frame Parameters 4 0218BFE8 0238BFE8 0258BFE8 0278BFE8 02D8BFE8 02F8BFE8 TDM2TIR TDM2 Transmit Interface Register 4 0218BFF0 0238BFF0 0258BFF0 0278BFF0 02D8BFF0 02F8BFF0 TDM2RIR TDM2 Receive Interface Register 4 0218BFF8 0238BFF8 0258BFF8 0278BFF8 02D8BFF8 02F8BFF8 TDM2GIR TDM2 General Interface...

Page 215: ...258FF58 0278FF58 02D8FF58 02F8FF58 TDM3TDBDR TDM3 Transmit Data Buffer Displacement Register 4 0218FF60 0238FF60 0258FF60 0278FF60 02D8FF60 02F8FF60 TDM3RDBDR TDM3 Receive Data Buffer Displacement Register 4 0218FF68 0238FF68 0258FF68 0278FF68 02D8FF68 02F8FF68 TDM3ASDR TDM3 Adaptation Sync Distance Register 4 0218FF70 0238FF70 0258FF70 0278FF70 02D8FF70 02F8FF70 TDM3TIER TDM3 Transmit Interrupt E...

Page 216: ...00 025B800F 02790000 027B800F 02D90000 02DB800F 02F90000 02FB800F Reserved 021B8010 023B8010 025B8010 027B8010 02DB8010 02FB8010 IEVENT Interrupt Event Register 4 021B8014 023B8014 025B8014 027B8014 02DB8014 02FB8014 IMASK Interrupt Mask Register 4 021B8018 023B8018 025B8018 027B8018 02DB8018 02FB8018 Reserved 021B8020 023B8020 025B8020 027B8020 02DB8020 02FB8020 ECNTRL Ethernet Control Register 4...

Page 217: ...02DB8104 02FB8104 TSTAT Transmit Status Register 4 021B8108 023B8108 025B8108 027B8108 02DB8108 02FB8108 Reserved 021B810c 023B810c 025B810c 027B810c 02DB810c 02FB810c TBDLEN TxBD Data Length 4 021B8110 021B811C 023B8110 023B811C 025B8110 025B811C 027B8110 027B811C 02DB8110 02DB811C 02FB8110 02FB811C Reserved 021B8124 023B8124 025B8124 027B8124 02DB8124 02FB8124 CTBPTR Current TxBD Pointer 4 021B8...

Page 218: ...0 02DB8340 02FB8340 MRBLR0R1 Maximum Receive Buffer Length R0R1 Register 4 021B8344 023B8344 025B8344 027B8344 02DB8344 02FB8344 MRBLR2R3 Maximum Receive Buffer Length R2R3 Register 4 021B8348 021B8383 023B8348 023B8383 025B8348 025B8383 027B8348 027B8383 02DB8348 02DB8383 02FB8348 02FB8383 Reserved 021B8384 023B8384 025B8384 027B8384 02DB8384 02FB8384 RBPTR0 RxBD Pointer 0 4 021B8388 021B838B 023...

Page 219: ...23B8510 025B8510 027B8510 02DB8510 02FB8510 MAXFRMR Maximum Frame Register 4 021B8514 021B851F 023B8514 023B851F 025B8514 025B851F 027B8514 027B851F 02DB8514 02DB851F 02FB8514 02FB851F Reserved 021B8520 023B8520 025B8520 027B8520 02DB8520 02FB8520 MIIMCFGR MII Management Configuration Register 4 021B8524 023B8524 025B8524 027B8524 02DB8524 02FB8524 MIIMCOMR MII Management Command Register 4 021B85...

Page 220: ...25B869C 027B869C 02DB869C 02FB869C RBYT Receive Byte Counter 4 021B86A0 023B86A0 025B86A0 027B86A0 02DB86A0 02FB86A0 RPKT Receive Packet Counter 4 021B86A4 023B86A4 025B86A4 027B86A4 02DB86A4 02FB86A4 RFCS Receive FCS Error Counter 4 021B86A8 023B86A8 025B86A8 027B86A8 02DB86A8 02FB86A8 RMCA Receive Multicast Packet Counter 4 021B86AC 023B86AC 025B86AC 027B86AC 02DB86AC 02FB86AC RBCA Receive Broad...

Page 221: ...Counter 4 021B86F8 023B86F8 025B86F8 027B86F8 02DB86F8 02FB86F8 TEDF Transmit Excessive Deferral Packet Counter 4 021B86FC 023B86FC 025B86FC 027B86FC 02DB86FC 02FB86FC TSCL Transmit Single Collision Packet Counter 4 021B8700 023B8700 025B8700 027B8700 02DB8700 02FB8700 TMCL Transmit Multiple Collision Packet Counter 4 021B8704 023B8704 025B8704 027B8704 02DB8704 02FB8704 TLCL Transmit Late Collisi...

Page 222: ...18 IADDR6 Individual Address Register 6 4 021B881C 023B881C 025B881C 027B881C 02DB881C 02FB881C IADDR7 Individual Address Register 7 4 021B8820 021B887F 023B8820 023B887F 025B8820 025B887F 027B8820 027B887F 02DB8820 02DB887F 02FB8820 02FB887F Reserved 021B8880 023B8880 025B8880 027B8880 02DB8880 02FB8880 GADDR0 Group Address Register 0 4 021B8884 023B8884 025B8884 027B8884 02DB8884 02FB8884 GADDR1...

Page 223: ...023B8950 025B8950 027B8950 02DB8950 02FB8950 PCNTRL2 Pattern Control 2 Register 4 021B8954 023B8954 025B8954 027B8954 02DB8954 02FB8954 Reserved 021B8958 023B8958 025B8958 027B8958 02DB8958 02FB8958 PATTRB2 Pattern Attributes 2 Register 4 021B8960 023B8960 025B8960 027B8960 02DB8960 02FB8960 PMD3 Pattern Match Data 3 4 021B8964 023B8964 025B8964 027B8964 02DB8964 02FB8964 Reserved 021B8968 023B896...

Page 224: ...4 02DB89E4 02FB89E4 Reserved 021B89E8 023B89E8 025B89E8 027B89E8 02DB89E8 02FB89E8 PMASK7 Pattern Mask 7 Register 4 021B89EC 023B89EC 025B89EC 027B89EC 02DB89EC 02FB89EC Reserved 021B89F0 023B89F0 025B89F0 027B89F0 02DB89F0 02FB89F0 PCNTRL7 Pattern Control 7 Register 4 021B89F4 023B89F4 025B89F4 027B89F4 02DB89F4 02FB89F4 Reserved 021B89F8 023B89F8 025B89F8 027B89F8 02DB89F8 02FB89F8 PATTRB7 Patte...

Page 225: ...0 02FB8A70 PCNTRL11 Pattern Control 11 Register 4 021B8A74 023B8A74 025B8A74 027B8A74 02DB8A74 02FB8A74 Reserved 021B8A78 023B8A78 025B8A78 027B8A78 02DB8A78 02FB8A78 PATTRB11 Pattern Attributes 11 Register 4 021B8A80 023B8A80 025B8A80 027B8A80 02DB8A80 02FB8A80 PMD12 Pattern Match Data 12 4 021B8A84 023B8A84 025B8A84 027B8A84 02DB8A84 02FB8A84 Reserved 021B8A88 023B8A88 025B8A88 027B8A88 02DB8A88...

Page 226: ... 023B8AF8 025B8AF8 027B8AF8 02DB8AF8 02FB8AF8 PATTRB15 Pattern Attributes 15 Register 4 021B8B00 021B8BF4 023B8B00 023B8BF4 025B8B00 025B8BF4 027B8B00 027B8BF4 02DB8B00 02DB8BF4 02FB8B00 02FB8BF4 Reserved 021B8BF8 023B8BF8 025B8BF8 027B8BF8 02DB8BF8 02FB8BF8 DATTR Default Attribute Register 4 021B8C00 021B8FFF 023B8C00 023B8FFF 025B8C00 025B8FFF 027B8C00 027B8FFF 02DB8C00 02DB8FFF 02FB8C00 02FB8FF...

Page 227: ...21BC030 023BC030 025BC030 027BC030 02DBC030 02FBC030 GISR GIC Interrupt Status Register 4 021BC038 021BC0FF 023BC038 023BC0FF 025BC038 025BC0FF 027BC038 027BC0FF 02DBC038 02DBC0FF 02FBC038 02FBC0FF Reserved 021BC100 023BC100 025BC100 027BC100 02DBC100 02FBC100 HSMPR0 Hardware Semaphore Register 0 4 021BC108 023BC108 025BC108 027BC108 02DBC108 02FBC108 HSMPR1 Hardware Semaphore Register 1 4 021BC11...

Page 228: ...02FBE000 DCR DSI Control Register 4 021BE008 023BE008 025BE008 027BE008 02DBE008 02FBE008 DSWBAR DSI Sliding Window Base Address Register 4 021BE010 023BE010 025BE010 027BE010 02DBE010 02FBE010 DIBAR9 DSI Internal Base Address Register Bank 9 4 021BE018 021BE01F 023BE018 023BE01F 025BE018 025BE01F 027BE018 027BE01F 02DBE018 02DBE01F 02FBE018 02FBE01F Reserved 021BE020 023BE020 025BE020 027BE020 02...

Page 229: ... 02DBF038 02FBF038 TCFRA7 Timer Configuration Register of Timer A7 4 021BF040 023BF040 025BF040 027BF040 02DBF040 02FBF040 TCFRA8 Timer Configuration Register of Timer A8 4 021BF048 023BF048 025BF048 027BF048 02DBF048 02FBF048 TCFRA9 Timer Configuration Register of Timer A9 4 021BF050 023BF050 025BF050 027BF050 02DBF050 02FBF050 TCFRA10 Timer Configuration Register of Timer A10 4 021BF058 023BF058...

Page 230: ...Compare Register of Timer A12 4 021BF0E8 023BF0E8 025BF0E8 027BF0E8 02DBF0E8 02FBF0E8 TCMPA13 Timer Compare Register of Timer A13 4 021BF0F0 023BF0F0 025BF0F0 027BF0F0 02DBF0F0 02FBF0F0 TCMPA14 Timer Compare Register of Timer A14 4 021BF0F8 023BF0F8 025BF0F8 027BF0F8 02DBF0F8 02FBF0F8 TCMPA15 Timer Compare Register of Timer A15 4 021BF100 023BF100 025BF100 027BF100 02DBF100 02FBF100 TCRA0 Timer Co...

Page 231: ... TCNRA1 Timer Count Register of Timer A1 4 021BF190 023BF190 025BF190 027BF190 02DBF190 02FBF190 TCNRA2 Timer Count Register of Timer A2 4 021BF198 023BF198 025BF198 027BF198 02DBF198 02FBF198 TCNRA3 Timer Count Register of Timer A3 4 021BF1A0 023BF1A0 025BF1A0 027BF1A0 02DBF1A0 02FBF1A0 TCNRA4 Timer Count Register of Timer A4 4 021BF1A8 023BF1A8 025BF1A8 027BF1A8 02DBF1A8 02FBF1A8 TCNRA5 Timer Co...

Page 232: ...00 025BF400 027BF400 02DBF400 02FBF400 TCFRB0 Timer Configuration Register of Timer B0 4 021BF408 023BF408 025BF408 027BF408 02DBF408 02FBF408 TCFRB1 Timer Configuration Register of Timer B1 4 021BF410 023BF410 025BF410 027BF410 02DBF410 02FBF410 TCFRB2 Timer Configuration Register of Timer B2 4 021BF418 023BF418 025BF418 027BF418 02DBF418 02FBF418 TCFRB3 Timer Configuration Register of Timer B3 4...

Page 233: ...0 02FBF4A0 TCMPB4 Timer Compare Register of Timer B4 4 021BF4A8 023BF4A8 025BF4A8 027BF4A8 02DBF4A8 02FBF4A8 TCMPB5 Timer Compare Register of Timer B5 4 021BF40 023BF40 025BF40 027BF40 02DBF40 02FBF40 TCMPB6 Timer Compare Register of Timer B6 4 021BF48 023BF48 025BF48 027BF48 02DBF48 02FBF48 TCMPB7 Timer Compare Register of Timer B7 4 021BF4C0 023BF4C0 025BF4C0 027BF4C0 02DBF4C0 02FBF4C0 TCMPB8 Ti...

Page 234: ...l Register of Timer B9 4 021BF550 023BF550 025BF550 027BF550 02DBF550 02FBF550 TCRB10 Timer Control Register of Timer B10 4 021BF558 023BF558 025BF558 027BF558 02DBF558 02FBF558 TCRB11 Timer Control Register of Timer B11 4 021BF560 023BF560 025BF560 027BF560 02DBF560 02FBF560 TCRB12 Timer Control Register of Timer B12 4 021BF568 023BF568 025BF568 027BF568 02DBF568 02FBF568 TCRB13 Timer Control Reg...

Page 235: ...BF5E0 02FBF5E0 TCNRB12 Timer Count Register of Timer B12 4 021BF5E8 023BF5E8 025BF5E8 027BF5E8 02DBF5E8 02FBF5E8 TCNRB13 Timer Count Register of Timer B13 4 021BF5F0 023BF5F0 025BF5F0 027BF5F0 02DBF5F0 02FBF5F0 TCNRB14 Timer Count Register of Timer B14 4 021BF5F8 023BF5F8 025BF5F8 027BF5F8 02DBF5F8 02FBF5F8 TCNRB15 Timer Count Register of Timer B15 4 021BF600 021BF77F 023BF600 023BF77F 025BF600 02...

Page 236: ...004 0F010004 0FF10004 SYPCR System Protection Control Register 4 F0010008 F001000D F0F10008 F0F1000D FF010008 FF01000D FFF10008 FFF1000D 0F010008 0F01000D 0FF10008 0FF1000D Reserved F001000E F0F1000E FF01000E FFF1000E 0F01000E 0FF1000E SWSR Software Service Register 2 F0010010 F0010023 F0F10010 F0F10023 FF010010 FF010023 FFF10010 FFF10023 0F010010 0F010023 0FF10010 0FF10023 Reserved F0010024 F0F10...

Page 237: ...006C 0FF1006C LDMTER Local Bus DMA Transfer Error RQNUM 1 B F001006D F00100FF F0F1006D F0F100FF FF01006D FF0100FF FFF1006D FFF100FF 0F01006D 0F0100FF 0FF1006D 0FF100FF Reserved Memory Controller F0010100 F0F10100 FF010100 FFF10100 0F010100 0FF10100 BR0 Base Register Bank0 4 F0010104 F0F10104 FF010104 FFF10104 0F010104 0FF10104 OR0 Option Register Bank0 4 F0010108 F0F10108 FF010108 FFF10108 0F01010...

Page 238: ... 0FF10170 MAMR Machine A Mode Register 4 F0010174 F0F10174 FF010174 FFF10174 0F010174 0FF10174 MBMR Machine B Mode Register 4 F0010178 F0F10178 FF010178 FFF10178 0F010178 0FF10178 MCMR Machine C Mode Register 4 F001017C F0010183 F0F1017C F0F10183 FF01017C FF010183 FFF1017C FFF10183 0F01017C 0F010183 0FF1017C 0FF10183 Reserved F0010184 F0F10184 FF010184 FFF10184 0F010184 0FF10184 MPTPR Memory Refre...

Page 239: ...0248 PITR Periodic Interrupt Timer Register 4 F001024C F001029F F0F1024C F0F1029F FF01024C FF01029F FFF1024C FFF1029F 0F01024C 0F01029F 0FF1024C 0FF1029F Reserved F00102A0 F00106FF F0F102A0 F0F106FF FF0102A0 FF0106FF FFF102A0 FFF106FF 0F0102A0 0F0106FF 0FF102A0 0FF106FF Reserved DMA Channels 0 15 F0010700 F0F10700 FF010700 FFF10700 0F010700 0FF10700 DCHCR0 DMA Channel 0 Configuration Register 4 F0...

Page 240: ...784 0FF10784 DSTR DMA Status Register 4 F0010788 F0F10788 FF010788 FFF10788 0F010788 0FF10788 DTEAR DMA TEA Status Register 1 B F0010789 F001078B F0F10789 F0F1078B FF010789 FF01078B FFF10789 FFF1078B 0F010789 0F01078B 0FF10789 0FF1078B Reserved F001078C F0F1078C FF01078C FFF1078C 0F01078C 0FF1078C DPCR DMA Pin Configuration Register 1 B F0010790 F0F10790 FF010790 FFF10790 0F010790 0FF10790 DEMR DM...

Page 241: ...eserved 183F20 TDM0TSR TDM0 Transmit Status Register 4 183F28 TDM0RSR TDM0 Receive Status Register 4 183F30 TDM0ASR TDM0 Adaptation Status Register 4 183F38 TDM0TER TDM0 Transmit Event Register 4 183F40 TDM0RER TDM0 Receive Event Register 4 183F48 TDM0TNB TDM0 Transmit Number of Buffers 4 183F50 TDM0RNB TDM0 Receive Number of Buffers 4 183F58 TDM0TDBDR TDM0 Transmit Data Buffer Displacement Regist...

Page 242: ...RER TDM1 Receive Event Register 4 187F48 TDM1TNB TDM1 Transmit Number of Buffers 4 187F50 TDM1RNB TDM1 Receive Number of Buffers 4 187F58 TDM1TDBDR TDM1 Transmit Data Buffer Displacement Register 4 187F60 TDM1RDBDR TDM1 Receive Data Buffer Displacement Register 4 187F68 TDM1ASDR TDM1 Adaptation Sync Distance Register 4 187F70 TDM1TIER TDM1 Transmit Interrupt Enable Register 4 187F78 TDM1RIER TDM1 ...

Page 243: ... Data Buffer Displacement Register 4 18BF68 TDM1ASDR TDM2 Adaptation Sync Distance Register 4 18BF70 TDM2TIER TDM2 Transmit Interrupt Enable Register 4 18BF78 TDM2RIER TDM2 Receive Interrupt Enable Register 4 18BF80 TDM2TDBST TDM2 Transmit Data Buffer Second Threshold 4 18BF88 TDM2RDBST TDM2 Receive Data Buffer Second Threshold 4 18BF90 TDM2TDBFT TDM2 Transmit Data Buffer First Threshold 4 18BF98 ...

Page 244: ...FF80 TDM3TDBST TDM3 Transmit Data Buffer Second Threshold 4 18FF88 TDM3RDBST TDM3 Receive Data Buffer Second Threshold 4 18FF90 TDM3TDBFT TDM3 Transmit Data Buffer First Threshold 4 18FF98 TDM3RDBFT TDM3 Receive Data Buffer First Threshold 4 18FFA0 TDM3TCR TDM3 Transmit Control Register 4 18FFA8 TDM3RCR TDM3 Receive Control Register 4 18FFB0 TDM3ACR TDM3 Adaptation Control Register 4 18FFB8 TDM3TG...

Page 245: ...us Register 4 1B8108 1B810B Reserved 1B810C TBDLEN TxBD Data Length 4 1B8110 1B8123 Reserved 1B8124 CTBPTR Current TxBD Pointer 4 1B8128 1B8183 Reserved 1B8184 TBPTR TxBD Pointer 4 1B8188 1B8203 Reserved 1B8204 TBASE Transmit Descriptor Base Address 4 1B8208 1B82AF Reserved 1B82B0 OSTBD Out of sequence TxBD Register 4 1B82B4 OSTBDP Out of sequence Tx Data Buffer Pointer Register 4 1B82B8 OS32TBDP ...

Page 246: ... Gap Inter Frame Gap Register 4 1B850C HAFDUPR Half Duplex Register 4 1B8510 MAXFRMR Maximum Frame Register 4 1B8514 1B851F Reserved 1B8520 MIIMCFGR MII Management Configuration Register 4 1B8524 MIIMCOMR MII Management Command Register 4 1B8528 MIIMADDR MII Management Address Register 4 1B852C MIIMCONR MII Management Control Register 4 1B8530 MIIMSTATR MII Management Status Register 4 1B8534 MIIM...

Page 247: ...R Receive Jabber Counter 4 1B86DC RDRP Receive Drop 4 1B86E0 TBYT Transmit Byte Counter 4 1B86E4 TPKT Transmit Packet Counter 4 1B86E8 TMCA Transmit Multicast Packet Counter 4 1B86EC TBCA Transmit Broadcast Packet Counter 4 1B86F0 TXPF Transmit Pause Control Frame Counter 4 1B86F4 TDFR Transmit Deferral Packet Counter 4 1B86F8 TEDF Transmit Excessive Deferral Packet Counter 4 1B86FC TSCL Transmit ...

Page 248: ... GADDR4 Group Address Register 4 4 1B8894 GADDR5 Group Address Register 5 4 1B8898 GADDR6 Group Address Register 6 4 1B889C GADDR7 Group Address Register 7 4 1B88A0 1B88FF Reserved 1B8900 PMD0 Pattern Match Data 0 4 1B8904 1B8907 Reserved 1B8908 PMASK0 Pattern Mask 0 Register 4 1B890C 1B890F Reserved 1B8910 PCNTRL0 Pattern Control 0 Register 4 1B8914 1B8917 Reserved 1B8918 PATTRB0 Pattern Attribut...

Page 249: ... 5 Register 4 1B89AC 1B89AF Reserved 1B89B0 PCNTRL5 Pattern Control 5 Register 4 1B89B4 1B89B7 Reserved 1B89B8 PATTRB5 Pattern Attributes 5 Register 4 1B89C0 PMD6 Pattern Match Data 6 4 1B89C4 1B89C7 Reserved 1B89C8 PMASK6 Pattern Mask 6 Register 4 1B89CC 1B89CF Reserved 1B89D0 PCNTRL6 Pattern Control 6 Register 4 1B89D4 1B89D7 Reserved 1B89D8 PATTRB6 Pattern Attributes 6 Register 4 1B89E0 PMD7 Pa...

Page 250: ...8 PMASK11 Pattern Mask 11 Register 4 1B8A6C 1B8A6F Reserved 1B8A70 PCNTRL11 Pattern Control 11 Register 4 1B8A74 1B8A77 Reserved 1B8A78 PATTRB11 Pattern Attributes 11 Register 4 1B8A80 PMD12 Pattern Match Data 12 4 1B8A84 1B8A87 Reserved 1B8A88 PMASK12 Pattern Mask 12 Register 4 1B8A8C 1B8A8F Reserved 1B8A90 PCNTRL12 Pattern Control 12 Register 4 1B8A94 1B8A97 Reserved 4 1B8A98 PATTRB12 Pattern At...

Page 251: ...ected Receive Inter Frame Bits Register 4 1B901C MIIGSK_IEVENT MIIGSK SMII Interrupt Event Register 4 1B9020 MIIGSK_IMASK MIIGSK SMII Interrupt Mask Register 4 1B9024 1BAFFF Reserved 1BB000 SCR Stop Control Register 4 1BB008 SASR Stop Acknowledge Status Register 4 1BC000 VIGR Virtual Interrupt Generation Register 4 1BC008 VISR Virtual Interrupt Status Register 4 1BC010 VNMIGR Virtual NMI Generatio...

Page 252: ...1BE030 1BE037 Reserved 1BE038 DIAMR11 DSI Internal Address Mask Register Bank 11 4 1BE040 DCIR DSI Chip ID Register 4 1BE048 DDR DSI Disable Register 4 1BE050 HRCW Hard Reset Configuration Word 4 1BE058 1BE7FF Reserved 1BE050 1BE058 Reserved 1BE060 DEXTBAR DSI External Sliding Window Base Address Register 4 1BE068 1BE7FF Reserved 1BE800 DSR DSI Status Register 4 1BE808 DER DSI Error Register 4 1BE...

Page 253: ...MPA11 Timer Compare Register of Timer A11 4 1BF0E0 TCMPA12 Timer Compare Register of Timer A12 4 1BF0E8 TCMPA13 Timer Compare Register of Timer A13 4 1BF0F0 TCMPA14 Timer Compare Register of Timer A14 4 1BF0F8 TCMPA15 Timer Compare Register of Timer A15 4 1BF100 TCRA0 Timer Control Register of Timer A0 4 1BF108 TCRA1 Timer Control Register of Timer A1 4 1BF110 TCRA2 Timer Control Register of Timer...

Page 254: ...0 TCFRB0 Timer Configuration Register of Timer B0 4 1BF408 TCFRB1 Timer Configuration Register of Timer B1 4 1BF410 TCFRB2 Timer Configuration Register of Timer B2 4 1BF418 TCFRB3 Timer Configuration Register of Timer B3 4 1BF420 TCFRB4 Timer Configuration Register of Timer B4 4 1BF428 TCFRB5 Timer Configuration Register of Timer B5 4 1BF430 TCFRB6 Timer Configuration Register of Timer B6 4 1BF438...

Page 255: ... Register of Timer B7 4 1BF540 TCRB8 Timer Control Register of Timer B8 4 1BF548 TCRB9 Timer Control Register of Timer B9 4 1BF550 TCRB10 Timer Control Register of Timer B10 4 1BF558 TCRB11 Timer Control Register of Timer B11 4 1BF560 TCRB12 Timer Control Register of Timer B12 4 1BF568 TCRB13 Timer Control Register of Timer B13 4 1BF570 TCRB14 Timer Control Register of Timer B14 4 1BF578 TCRB15 Ti...

Page 256: ...L_ACR Local Arbiter Configuration Register 1 B 1D0035 1D0037 Reserved 1D0038 LCL_ALRH Local Arbitration Level Register bus masters 0 7 4 1D003C LCL_ALRL Local Arbitration Level Register bus masters 8 15 4 1D0040 TESCR1 System Bus Transfer Error Status Control Register 1 4 1D0044 TESCR2 System Bus Transfer Error Status Control Register 2 4 1D0048 L_TESCR1 Local Bus Transfer Error Status Control Reg...

Page 257: ... MAR Memory Address Register 4 1D016C 1D016F Reserved 1D0170 MAMR Machine A Mode Register 4 1D0174 MBMR Machine B Mode Register 4 1D0178 MCMR Machine C Mode Register 4 1D017C 1D0183 Reserved 1D0184 MPTPR Memory Refresh Timer Prescaler 2 1D0186 1D0187 Reserved 1D0188 MDR Memory Data Register 4 1D018C 1D018F Reserved 1D0190 PSDMR System Bus SDRAM Mode Register 4 1D0194 Reserved 1D0198 PURT System Bu...

Page 258: ... DCHCR9 DMA Channel 9 Configuration Register 4 1D0728 DCHCR10 DMA Channel 10 Configuration Register 4 1D072C DCHCR11 DMA Channel 11 Configuration Register 4 1D0730 DCHCR12 DMA Channel 12 Configuration Register 4 1D0734 DCHCR13 DMA Channel 13 Configuration Register 4 1D0738 DCHCR14 DMA Channel 14 Configuration Register 4 1D073C DCHCR15 DMA Channel 15 Configuration Register 4 1D0740 1D077F Reserved ...

Page 259: ...rved may have the following effects A time out error Refer to Section 4 1 5 SIU and General Software Watchdog Timers on page 4 6 Read data not valid Data stored in the internal memories is accessed by the extended core as big endian Bytes within registers can be accessed unless specified otherwise Table 8 11 Pseudo Command Memory Map 0x01FC0000 0x01FC00FF Address Acronym Name Size in Bytes 0x01FC0...

Page 260: ...MSC8113 Reference Manual Rev 0 8 80 Freescale Semiconductor Memory Map ...

Page 261: ...ler PIC Local interrupt controller LIC Extended core power saving modes The remainder of this chapter describes each of these extended core components Figure 9 1 Extended Core System Xa Xb P QBus IRQs IRQs MQBus SQBus Local Bus 128 128 64 64 64 LIC PIC 128 128 SC140 Core EOnCE QBus Interface Instruction Cache M1 RAM Notes 1 The arrows show the data transfer direction QBus Bank 1 QBus Bank 3 2 The ...

Page 262: ... This number of MAC units yields the performance needed for essential DSP tasks such as finite impulse response FIR and infinite impulse response IIR filters and fast Fourier transforms FFTs In addition to the four data execution units the core contains two address arithmetic units AAUs one bit manipulation unit BMU and one branch unit Overall the SC140 can issue and execute up to six instructions...

Page 263: ...ch 256 bit wide Complex interleaving in the modules minimizes contentions Each memory group has four ports three of which enable access from the SC140 core buses P bus and the two data buses Xa and Xb and one of which is the L port The L port connects directly to the local bus The four 24 bit address memory ports include P program 128 bit data read Xa data 64 bit read and write Xb data 64 bit read...

Page 264: ...eservation instructions to the SC140 core Protecting atomic instructions and internal memory Disabling the SC140 core in ABIST or Disable Core mode 9 2 1 Memory Organization All M1 memory groups are connected to the SC140 core main buses Xa bus Xb bus and P bus The L port of the memory is connected directly to the local bus 9 2 1 1 Memory Groups Each memory group contains an I O group buffer and e...

Page 265: ... 3 Memory Group Figure 9 4 Memory Interleaving Xa Bus Xb Bus L Port P Bus GROUP I O Module 0 Module 2 Module 3 Module 4 Module 5 Module 6 Module 7 Module 1 line 0 line 1 line 7 line 8 line 9 line 15 line 1023 line 1016 line 1017 Xa Bus Xb Bus L Port P Bus Group I O Module 0 Module 1 Module 7 ...

Page 266: ...tentions and errors on the internal core buses and outputs exception signals to the interrupt controller See Chapter 17 Interrupt Processing 9 2 2 1 Errors Errors generate interrupts using the NMI inputs to the interrupt controller as follows Bus Error When an address on the internal bus does not match any physical address in the internal memory space a bus error occurs and NMI4 is generated inter...

Page 267: ... SC140 core and the instruction cache requests bringing the data on the QBus As Figure 9 5 shows the EQBS consists of a bus switch a write buffer a fetch unit a control unit and the banks to handle the communication with the slaves and all EQBS registers The QBus masters are fetch unit write buffer and bus switch The CU is the arbiter for the QBus masters The QBus Controller QBC is the unit handli...

Page 268: ...data areas registers the user can set a data area to immediate or immediate no freeze see the Data Area Registers on page 9 22 The buffer transfers its content to the destination without further SC140 core intervention Exact timing of the transfer depends on the traffic on the QBus In the following cases the write buffer halts the SC140 core to protect data from running over Write buffer is full T...

Page 269: ...a write from the SC140 core 128 bit data reads from the SC140 core Pipeline between the address and data phases Supports slaves with different response times Holds four banks with different chip selects and 64 KB resolution Three of the banks are configurable and the fourth is a default bank supporting all non defined accesses 9 3 1 1 Fetch Unit The fetch unit handles all program accesses to exter...

Page 270: ...causes a fetch prefetch of a block at a minimum so setting a large block causes each miss to bring a lot of data into the cache The SC140 core may not necessarily need this data possibly delaying other operations for example a read that occur during a block However it can also bring data that the SC140 core needs without being delayed by other operations The fetch unit controls the cache updates a...

Page 271: ... The addresses are serviced on the QBus according to their priority However for a write buffer flush the write buffer gets the highest priority within accesses of the same core cycle 9 3 3 QBus Banks The bus has a single master EQBS and multiple slaves that are divided into four banks There can be more than one slave on each bank and the slaves are divided according to the address space Each of th...

Page 272: ...range for each bank is defined as a combination of the base address register and the mask register The functions of these two registers are interrelated in that the value entered into the base address register must be a multiple of the area size defined by the mask register The mask register defines the size of the bank address range as defined in Table 9 2 Table 9 1 Bank Configuration Bank Identi...

Page 273: ...f there is an overlap between banks the match occurs in the bank with the highest priority Table 9 3 shows examples of bank address and mask register values 0xFFC0 1111111111000000 4 MB 0xXXC0 0xFF80 1111111110000000 8 MB 0xXX80 0xFF00 1111111100000000 16 MB 0xXX00 0xFE00 1111111000000000 32 MB 0xXE00 0xFC00 1111110000000000 64 MB 0xXC00 0xF800 1111100000000000 128 MB 0xX800 0xF000 111100000000000...

Page 274: ... with atomic signal is accepted bit test on the Xa or Xb buses to the SRAM location The QBC tries to detect a write to a protected address before the SC140 core finishes the read modify write operation Reservation occurs when a write to a protected address is detected If the write operation fails the T bit in the SC140 core is set The resulting signal is optionally used in a lock mechanism When th...

Page 275: ...000 2 KB xxxxxxxxxxxxxxxxxxxxx100 0 5 xxxxxxxxxxxxxxxxxxxx0000 4 KB xxxxxxxxxxxxxxxxxxxx1000 0 6 xxxxxxxxxxxxxxxxxxx00000 8 KB xxxxxxxxxxxxxxxxxxx10000 0 7 xxxxxxxxxxxxxxxxxx000000 16 KB xxxxxxxxxxxxxxxxxx100000 0 8 xxxxxxxxxxxxxxxxx0000000 32 KB xxxxxxxxxxxxxxxxx1000000 0 9 xxxxxxxxxxxxxxxx00000000 64 KB xxxxxxxxxxxxxxxx10000000 0 10 xxxxxxxxxxxxxxx000000000 128 KB xxxxxxxxxxxxxxx100000000 0 11 x...

Page 276: ...n binary form 000000000001001000000000 The 8 non written lsb 0x00 After the area is sized the global and IMM bits determine whether this area is global immediate or immediate with no freeze The area can be global and immediate at the same time The area can be reversed so it does not have the value it was set to For example if the immediate bit is set and the reverse bit is set this area is not imm...

Page 277: ...ant For example an area with base address 32 MB size 256 KB supports the condition that the base be an integer multiple of the size The steps in defining this area are as follows 1 Write the base address in 32 bit representation 32 MB is written as 00000010000000000000000000000000 2 Based on the size 256 KB choose line 3 in the table The size_bit 0 Table 9 5 Cacheable Area Programming No Original ...

Page 278: ...fluence the new value is valid according to the unit that is affected by the register Changes in registers that affect the fetch unit ICACR ICABR IFUR are valid at the next fetch miss after the write to the register Changing the registers during prefetch does not affect the prefetch For example turning the prefetch off bit 4 in IFUR does not stop the current prefetch but disables prefetching after...

Page 279: ...0000 Bank Base The base address of the bank 1 Do not parallel an external read or write with a write to the register 2 Do not access external read or write one cycle after writing to the register QBUSMR 0 2 QBus Mask Register 0 2 QBUSMR0 0x00F0FF00 QBUSMR1 0x00F0FF04 QBUSMR2 0x00F0FF08 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 bank maskl 0 15 Type R W QBUSMR0 is read only Reset mask0 0xFFFF read o...

Page 280: ...s outside the area definition SIZE 7 0 Size Indication Sets the size to the 64 KB minimum or sets it to a different size 0 Size is other than 64 KB 1 Size is 64 KB 8 15 0 Reserved Write to zero for future compatibility ICABR Instruction Cacheable Area Base Register 0x00F0FF32 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Area Base 15 0 Type R W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Table 9 9 ICABR Bit...

Page 281: ...ush Register 0x00F0FF80 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset WBCR Write Buffer Control Register 0x00F0FF82 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WBOFF WD 9 0 Type R W Reset 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 Table 9 11 WBCR Bit Descriptions Name Reset Description Settings 0 2 0 Reserved Write to zero for future compatibility WBOFF 3 1 Disable Write Buffer Enables disables the wr...

Page 282: ... write can be with or without a freeze to the SC140 core 00 Regular write through write buffer 01 Write immediate 10 Write immediate with no freeze 11 Reserved 19 20 0 Reserved Write to zero for future compatibility EN 21 0 Enable Operation Enables disables this area register operation 0 Disable operation 1 Enable operation RV 22 0 Reverse Bit Defines a non immediate or non global memory slice wit...

Page 283: ...nt cores The reset values are SC140 core 0 0x00 SC140 core 1 0x01 SC140 core 2 0x02 VR Version Register 0x00F0FFF2 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PrVer ECVer Type R Reset 0x03 0x52 Table 9 14 VR Bit Descriptions Name Reset Description PrVer 0 7 0x03 Process Version Contains a different number for each process version ECVer 8 15 0x52 Extended Core Version Contains a different number for ...

Page 284: ...ctions thus taking advantage of the capabilities of the external memory and associated interfaces Figure 9 9 shows the ICache in the extended SC140 core system The MSC8113 ICache has the following features 16 KB of memory 16 way associativity 4 indexes so the ICache has a total of 64 lines 16 fetch sets for each line Each fetch set is 16 bytes Table 9 15 FLBACR0 Bit Descriptions Name Reset Descrip...

Page 285: ...ero wait state memory Each of the three extended cores in the MSC8113 has its own ICache Each of these ICache memories optimizes access to its instruction storage area by using a specialized indexing system When the SC140 core requests instruction code the first 22 bits of the requested address A 31 10 are used to identify a region in external memory and form the TAG value for that region The next...

Page 286: ...e addresses phase 2 to the end of the cache line or until a new cache miss begins the next fetch sequence Note Unlike a data cache the instruction cache depends on code not changing during run time If it does the cache contents should be cleared cache flush no coherency support When a cache miss occurs one of several events happens If the upper 22 bits of the address match the tag and index in a c...

Page 287: ...e LRU values for all other lines with the same INDEX number except for the line for which LRU 0 are decremented by 1 Replacement of the least recently used existing line with a new one is called thrashing Frequent thrashing indicates cache ineffectiveness Cache effectivity is based on locality Programs have two locality attributes Temporal locality The likelihood that the SC140 core will often req...

Page 288: ...d is compared to the current access address Valid Bit Each fetch block in the cache has a bit indicating whether it is found or not found in the cache This bit is called a valid bit Index and Way Set As Figure 9 10 shows each slow memory segment is divided into a fixed number of lines Each line is marked by a unique number called an index A line with a particular index can be mapped to any of sixt...

Page 289: ...rashes Debug mode is only for viewing the ICache status and breakpoint support The EOnCE module performs run time debugging which counts the hit and miss signals sent by the ICache Each time the ICache answers an external access a hit flag is raised for a counter in the EOnCE module If a new meaningful cacheable area access is not found in the ICache a miss flag goes up Note To use the run time de...

Page 290: ...U of a particular index again lsb to msb in sequential order The following tables describe a tag array and LRU machine reading sequences accordingly Table 9 16 Read Valid Bit Array Status Example SC140 Core Debug Register Status initialization command Initial load index0 position0 One execution set delay required Read valid bit status 1 16 bits line index 0 position 0 Reload index0 position 1 Read...

Page 291: ...s effect only in systems with the cache connected to the PIC Read tag array status 8 16 bits line way 0 index3 tag bits 21 16 padded Reload way1 index0 tag bits 15 0 Read tag array status 9 16 bits line way 1 index0 tag bits 15 0 Reload way1 index0 tag bits 21 16 padded More tag array status reads Read tag array status 128 16 bits line way 15 index3 tag bits 21 16 padded Reload way0 ind0 lsbs Tabl...

Page 292: ...nly one register which includes the lower and upper boundaries the OS determines which tasks need fixed allocation and which tasks can work with a flexible boundaries mechanism The boundary resolution is the size of one LRU priority level for all indexes that is one way Figure 9 12 describes the difference between flexible boundaries and fixed allocation With flexible boundaries the first task tas...

Page 293: ...s section summarizes the different accesses their functionality in the ICache and restrictions Notice that debug reads and commands are described in detail in Section 9 4 2 Debugging The cache is programmed and read through the QBus It acts as a zero wait state slave on QBus Bank 0 sharing it with other peripherals similarly connected for example the PIC Bank 0 always has an immediate attribute th...

Page 294: ...de including flushes The cache also enters lock mode if the upper boundary is set to be less than the lower boundary when there is an attempt to read the register the lock mode bit is on The ICache does not enter Lock mode if it is off or set to Debug mode mode bit is read as 0 In summary mode priority is as follows Off Debug mode Lock mode For a description of the ICCR bits see Table 9 19 on page...

Page 295: ...ss or equal to the upper boundary must be both preceded and followed by two no operation nop execution sets as illustrated in the following code example move l 0000f001 d1 nop nop move w d1 ICCR_ADDRESS nop nop In addition any program that enables disables the ICache must not be placed into the internal memory space accessible to the DMA controller Paralleling a run time command with a control reg...

Page 296: ... Bit Array Status Register VBASR page 9 38 ICCR ICache Control Register 0x00F0FC00 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 UB LB DM LM ON Type R W Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 Table 9 19 ICCR Bit Descriptions Name Reset Description Value UB 0 3 1 Upper Boundary Value Selects the upper boundary way number for LRU consideration LB 4 7 0 Lower Boundary Value Selects the lower boundary way ...

Page 297: ...5 6 7 8 9 10 11 12 13 14 15 LS 15 0 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 9 21 LRUSR Bit Descriptions Name Reset Description LS 0 15 0x0000 LRU Status Register Contents An LRU status bit for each line that shares an index number There is a register value stored for each index The individual values are accessed by a sequential read The first SC140 core read returns the value for Index ...

Page 298: ...ripherals It receives up to 64 interrupt sources and maps them to different PIC inputs Interrupt Table 9 22 TASR Bit Descriptions Name Reset Description TS 0 15 0x0000 Tag State Register A TAG status bit for each line that shares an index number A register value is stored for each index The individual values are accessed by a sequential read The first SC140 core read returns the value for Index 0x...

Page 299: ...tended core exits Wait mode when there is an interrupt or a reset or when the MSC8113 device enters Debug mode by either a JTAG DEBUG_REQUEST command or assertion of EE0 Note When multiple cores are in Wait mode issuing a simultaneous virtual interrupt to all these cores does not guarantee that the cores exit Wait mode on the same clock cycle To ensure that the SC140 core wakes up correctly from W...

Page 300: ...MSC8113 Reference Manual Rev 0 9 40 Freescale Semiconductor Extended Core ...

Page 301: ...he three SC140 cores to M2 memory Through a parked grant mechanism the arbitration winner holds the MQBus grant until another SC140 core initiates another request The 480 KB M2 memory contains 476 KB RAM and 4 KB ROM memory operating at the SC140 core frequency M2 is a unified memory that stores both data and program code The M2 memory can be accessed from either the MQBus or the Local bus ports A...

Page 302: ...d accesses that are not prefetched Immediate write accesses Middle priority Non immediate write accesses from the EQBS write buffer Low priority Prefetch read accesses During each clock cycle the access requests are handled as follows If there are high priority requests the MQBus arbiter performs the round robin algorithm between the high priority requesting SC140 cores If there are no high priori...

Page 303: ...irst M2 memory read access by an SC140 core without a parked grant requires seven wait states If no other SC140 core requests the bus the further consecutive accesses take six clock cycles If an SC140 core has a parked grant the first access requires six wait states An SC140 core read from M2 memory requires at least six or eight wait states Since the ICache hit ratio is high these six or eight wa...

Page 304: ...MSC8113 Reference Manual Rev 0 10 4 Freescale Semiconductor MQBus and M2 Memory ...

Page 305: ... and M2 memories of that device The SQBus is a multi master multi slave bus The three SC140 cores are the masters of this bus The slaves are the IP master for accesses to the IPBus and the system bus interface for accesses to the system bus The IP master forwards accesses from the SQBus and from the local bus to the IPBus When there are simultaneous requests from both the local bus and the SQBus t...

Page 306: ...cess latency is improved Using the global bit described in Section 9 3 9 EQBS Programming Model on page 9 18 the GBL signal on the system bus is asserted This signal typically indicates that the MSC8113 device is writing to a cacheable area The off device data cache uses this signal to flag a corrupted entry 11 2 Reservation Atomic Operation The reservation atomic operation bmtest instruction is p...

Page 307: ... However when another SC140 core performs a write operation to the address of the open atomic operation the atomic operation fails 11 2 2 Reservation Operation on the System Bus A snooper on the system bus attempts to detect a non atomic write to the address of an open atomic operation When the system bus interface receives either a read or write with an atomic signal a snooper starts to snoop the...

Page 308: ...MSC8113 Reference Manual Rev 0 11 4 Freescale Semiconductor SQBus ...

Page 309: ... to back read or write in page mode to achieve the highest performance The GPCM provides interfacing for simpler lower performance memory resources and memory mapped devices The GPCM has inherently lower performance because it does not support bursting For this reason GPCM controlled banks are used primarily for boot loading and access to low performance memory mapped peripherals The GPCM controls...

Page 310: ...dress Bus 0 31 Local Address 0 31 System Data Bus 0 63 Local Data 0 63 GPCM SDRAM Address Decoders System to Local Local Bus 60x Transactions System Data Bus Interface Master Slave System Bus Devices D 0 63 SC140 Cores GPCM UPM C Array 2 UPM Arrays System Bus Memory Controller Local Bus Memory Controller CS11 IPBus Peripherals SC140 Cores Memories CS9 System Bus Master System Interface CS 0 7 60x ...

Page 311: ...ress decode on each memory bank The block size of each memory bank varies between 32 KB 1 MB for SDRAM and 4 GB 128 MB for SDRAM using bank based interleaving Normal parity can be generated and checked for any external memory bank Read modify write parity can be generated and checked for any external memory bank with a 32 bit or 64 bit port size Using RMW parity on a bank with a 32 bit port size r...

Page 312: ...r Programmable Machine A B System Bus Chip Select Machine MxMR BSEL General Purpose Local Bus Chip Select Machine General Purpose User Programmable Machine C Bank 9 Bank 9 is used to access IPBus peripherals System bus SDRAM Machine Local Bus Local Bus System Bus System Bus BR1 MS BR2 MS BR7 MS BR9 MS BR11 MS System Bus Bank 10 is reserved for future expansion Address CE OE WE Data EPROM RAS CAS 0...

Page 313: ...terface to many types of memory devices Each UPM controls the address multiplexing for accessing DRAM devices and the timings of BS 0 7 and GPLx UPMs A and B can be assigned either to the system bus or to the local bus Each external memory bank CS 0 7 can be assigned to either UPMA or UPMB In the MSC8113 device one internal bank on the local bus uses the UPMC to access the internal memories CS11 E...

Page 314: ...sing the internal arbiter or more using an external arbiter Figure 12 5 shows an example of a typical system in which several devices can share the same system bus and memory controller In Single Master mode since there is only one bus master the address bus is fully driven using latches Therefore the memory controller can use the address for any manipulation that might needed for the current acce...

Page 315: ...ment For details see Section 12 1 11 to Section 12 1 14 and Section 12 6 Figure 12 7 shows a memory controller access in 60x compatible mode and demonstrates the validity period of each group of signals involved in the access as well as the relationships between the various groups Figure 12 6 Schematic Timing Diagram for MEMC Access In Non 60x Compatible Mode Figure 12 7 Timing Diagram for MEMC Ac...

Page 316: ...ority over regular memory bank hits 12 1 2 Page Hit Checking The SDRAM machine supports page mode operation Each time a page is activated on the SDRAM device the SDRAM machine stores its address in a page register The page information which you write to the ORx register is used along with the bank size to compare page bits of the address to the page register each time a bus cycle access is request...

Page 317: ...es two data buffer controls for the system bus BCTL0 and BCTL1 These controls are activated when a GPCM or UPM controlled bank is accessed and are disabled by setting ORx BCTLD Access to SDRAM machine controlled bank does not activate the BCTLx controls The BCTLx signals have programmable polarity and functionality that are controlled by SIUMCR BCTLC For details on possible polarity and functional...

Page 318: ...enerated Note This mechanism does not replace the 60x compatible reservation mechanism 12 1 8 Partial Data Valid Indication PSDVAL The system bus and the local bus have an internal 64 bit data bus According to the 60x bus specification TA is asserted when up to 64 bits 8 bytes of data is transferred Because the MSC8113 device memories can have port sizes smaller than 64 bits there is a need for a ...

Page 319: ...evices can output data every cycle and because the data checking requires additional data set up time the timing constraints are extremely hard to meet In such systems you can eliminate the additional data set up time requirement by setting the data pipelining bit BRx DR This creates data pipelining of one stage within the memory controller in which the data check calculations are done In systems ...

Page 320: ...ipelining as if the access were governed by it This feature allows multiple MSC8113 systems to be connected in 60x compatible mode without losing functionality and performance It also makes it easy to connect other 60x compatible slaves on the 60x bus 12 1 13 External Address Latch Enable Signal ALE The memory controller provides control for an external address latch needed on the system bus in 60...

Page 321: ... banks connect to the system bus The SDRAM memory clock must operate at the same frequency as the system clock and be phase aligned with it Table 12 2 BADDR Connections BADDRx 64 72 Bit Port Size 32 Bit Port Size Any 16 Bit Port Size Device Any 8 Bit Port Size Device SDRAM Non SDRAM SDRAM Non SDRAM BADDR27 Not connected Connected Not connected Connected Connected Connected BADDR28 Not connected Co...

Page 322: ...nks registers ORx BRx PSDMR After all memory parameters are configured system software should execute the following initialization sequence for each SDRAM device 1 Issue a PRECHARGE ALL BANKS command 2 Issue eight CBR REFRESH commands 3 Issue a MODE SET command to initialize the mode register The initial commands are executed by setting PSDMR OP and accessing the SDRAM with a single byte transacti...

Page 323: ...S CS RAS WE CKE CLK DQM1 MA 0 11 2 DQ 0 7 2 1M 8 SDRAM CAS CS RAS WE CKE CLK DQM1 MA 0 11 2 DQ 0 7 2 1M 8 SDRAM CAS CS RAS WE 12 bit CLKOUT Notes 1 The DQM signal is defined as the byte lane mask signal in some memory devices or the byte lane enable signal other devices As a mask signal it is asserted high and a value of 1 masks the byte lane As an enable signal it is asserted low and a 0 enables ...

Page 324: ...burst lengths of 1 2 and a page for SDRAMs The mode register data CAS latency burst length and burst type is programmed into the PSDMR register by initialization software at reset After the PSDMR is set the MSC8113 transfers the information to the SDRAM array by issuing a MODE SET command Section 12 2 12 SDRAM Signals mode set Command Timing on page 12 28 gives timing information precharge single ...

Page 325: ...k before deactivating the previous bank the memory controller will use this feature to active the new bank and deactivate the old bank at optimal timing for maximal data rate The address bits that select the bank are controlled by PSDMR PBI The following two methods are used for internal bank interleaving Page Based Interleaving For use when a long consecutive access to SDRAM is expected The acces...

Page 326: ...MSC8113 mode the lower bits of the address bus connect to the device address port and the memory controller multiplexes the row column and the internal banks select lines according to PSDMR SDAM and PSDMR BSMA Table 12 5 shows how PSDMR SDAM settings affect address multiplexing PSDMR BSMA selects which address lines from the multiplexed address serve as the device bank selects These bits are drive...

Page 327: ...oth on BNKSEL 0 2 and on A 16 18 The SDRAM device inputs BA In this case the lines can be connected either to A 16 18 or to BNKSEL 2 0 Table 12 5 SDRAM Address Multiplexing A 0 15 SDAM External Bus Address Lines A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 000 Signal driven on external lines when address multiplexing is enabled A5 A6 A7 001 A5 A6 010 A5 011 100 101 Table 12 6 SDRAM Addres...

Page 328: ...o CBR refreshes to SDRAM according to the interval specified in PSRT This represents the time period required between refreshes The value of PSRT depends on the specific SDRAM devices and the operating frequency of the MSC8113 bus This value should allow for a potential collision between memory accesses and refresh cycles The period of the refresh interval must be greater than the access time to e...

Page 329: ...o Read Write Interval Controlled by PSDMR ACTTORW defines the earliest timing for a READ WRITE command after an ACTIVATE command Figure 12 10 PRETOACT 2 2 Clock Cycles Figure 12 11 ACTTORW 2 2 Clock Cycles CLK ALE CS PSDRAS PSDCAS PWE PSDDQM PRECHARGE Command ACTIVATE Command MA11 MA10 MA 0 9 Bank A PRETOACT 2 Bank A Row Row CLK ALE CS PSDRAS PSDCAS PWE PSDDQM ACTIVATE MA 0 11 Command ACTTORW 2 Da...

Page 330: ...lled by PSDMR LFDOTOPRE defines the earliest timing for PRECHARGE command after the last data is read from the SDRAM It is always related to the CL parameter Figure 12 12 CL 2 2 Clock Cycles Figure 12 13 LDOTOPRE 2 2 Clock Cycles CLK ALE CS PSDRAS PSDCAS MA 0 11 Row Column PWE PSDDQM Data D0 D1 D2 D3 ACTIVATE READ First data out CL 2 CLK ALE CS PSDRAS PSDCAS MA 0 11 Row Column PWE Data D0 D1 D2 D3...

Page 331: ... Recovery Interval RFRC Controlled by PSDMR RFRC defines the earliest timing for an ACTIVATE command after a REFRESH command Figure 12 14 WRC 2 2 Clock Cycles Figure 12 15 RFRC 4 6 Clock Cycles CLK ALE CS PSDRAS PSDCAS MA 0 11 Row Column PWE Data D0 D1 D2 D3 ACTIVATE WRITE Last Data In DEACTIVATE WRC 2 PSDDQM CLK ALE CS PSDRAS PSDCAS MA 0 11 PWE PSDDQM A8 1 RFRC 4 6 clocks RAx PRETOACT 3 Precharge...

Page 332: ...any case of delays on the address lines such as address buffers External Address and Command Buffers BUFCMD In 60x compatible mode external buffers can be placed on the command strobes except CS as well as on the address lines If the additional delay of the buffers endangers the device set up time PSDMR BUFCMD should be set so the memory controller adds one cycle for each SDRAM command Figure 12 1...

Page 333: ...ious types of accesses Figure 12 18 SDRAM Single Beat Read Page Closed CL 3 Figure 12 19 SDRAM Single Beat Read Page Hit CL 3 Figure 12 20 SDRAM Two Beat Burst Read Page Closed CL 3 CLK ALE CS PSDRAS PSDCAS MA 0 11 Row Column PWE PSDDQM Data D0 CLK ALE CS PSDRAS PSDCAS MA 0 11 Column PWE PSDDQM Data D0 Z CLK ALE CS PSDRAS PSDCAS MA 0 11 Row Column PWE PSDDQM Data D0 D1 ...

Page 334: ... Figure 12 23 SDRAM Three Beat Burst Write Page Closed CLK ALE CS PSDRAS PSDCAS MA 0 11 PWE PSDDQM Data D0 Z A10 1 BS BS Bank select according to SDRAM organization A10 1 means all banks are precharged Row CAS Latency 3 Col D1 D2 D3 Deactivate Activate CLK ALE CS PSDRAS PSDCAS MA 0 11 Column PWE PSDDQM Data D0 CLK ALE CS PSDRAS PSDCAS MA 0 11 Row Column PWE PSDDQM Data D0 D1 D2 ...

Page 335: ...te Pipelined Page Hit Figure 12 26 SDRAM Read after Write Pipelined Page Hit CLK ALE CS PSDRAS PSDCAS MA 0 11 Column1 PWE PSDDQM Data D0 Z Column2 D0 D1 D1 DQM latency affects deassertion only 2 CLK ALE CS PSDRAS PSDCAS MA 0 11 Column1 PWE PSDDQM Data D0 D1 D2 D3 D1 D2 D3 D0 Column2 CLK ALE CS PSDRAS PSDCAS MA 0 11 Column1 PWE PSDDQM Data D0 D1 D1 D2 D3 D0 Column2 Z ...

Page 336: ... the refresh timer in one clock intervals After the last REFRESH command is issued the memory controller waits for the number of clocks written in the SDRAM machine mode register PSDMR RFRC The timing is shown in Figure 12 29 Figure 12 27 SDRAM MODE SET Command Timing Figure 12 28 Mode Data Bit Settings Note The mode data is the address value during a mode set cycle It is driven by the memory cont...

Page 337: ...32 bit port size organized as four 128 Mb devices each organized as 16 M 8 bits Each device has four internal banks 12 row address lines and 10 column address lines For page based interleaving the address bus is partitioned as shown in Table 12 7 Figure 12 29 SDRAM Bank Staggered CBR Refresh Timing Table 12 7 60x Address Bus Partition A 0 5 A 6 17 A 18 19 A 20 29 A 30 31 msb of start address Row B...

Page 338: ...DMR BSMA value Note In the preceding example address lines A 18 19 are output on BNKSEL 1 and BNKSEL 2 accordingly During a READ WRITE command the address port is as shown in Table 12 9 Because AP alternates with A 7 of the row lines set PSDMR SDA10 011 This value drives A7 on the PSDA10 line during execution of the ACTIVATE command and AP during execution of the READ WRITE and CBR commands Table ...

Page 339: ... that to multiplex A 8 19 over A 17 28 the PSDMR SDAM field must contain a value of 001 and because the internal bank selects are multiplexed over A 15 16 PSDMR BSMA must contain a value of 010 only the lower two bank select lines are used ORx SDAM LSDAM BPD ROWST 111111000000 00000 01 0110 NUMR PMSEL IBID 011 0 0 PSDMR PBI RFEN OP SDAM BSMA SDA10 RFRC PRETOACT 1 1 000 100 011 011 from device data...

Page 340: ...f the row lines set PSDMR SDA10 011 This setting drives A9 on the PSDA10 line when the ACTIVATE command executes and AP when the READ WRITE and CBR commands execute Table 12 14 shows the register configuration Not shown are PSRT and MPTPR which should be programmed according to the device refresh requirements Table 12 13 SDRAM Device Address Port During READ WRITE Command A 0 14 A 15 16 A 17 A 18 ...

Page 341: ...ors The BCTLx signals appear as R W in the timing diagrams See Section 12 1 6 Data Buffer Controls BCTL 0 1 on page 12 9 Additional control is available in 60x compatible mode system bus only via the external address latch enable ALE signal Figure 12 30 shows a simple connection between an SRAM device with a 32 bit port and the MSC8113 In the example the SRAM connects to the system bus Table 12 15...

Page 342: ...ernal address bus CS can be output in any of three configurations Simultaneous with the external address One quarter of a clock cycle later One half of a clock cycle later Table 12 16 GPCM Strobe Signal Behavior Option Register Attributes Signal Behavior TRLX Access ACS CSNT Address to CS Asserted CS Deasserted to Address Change PWE Deasserted to Address Data Invalid Total Cycles 0 Read 00 x 0 0 x...

Page 343: ...igure 12 31 shows a basic connection between the MSC8113 and an external peripheral device Here CS the strobe output for the memory access directly connects to the CE of the memory device and BCTL0 connects to the respective R W in the peripheral device Figure 12 32 shows CS as defined by the set up time required between the address lines and CE You can configure ORx ACS to specify CS to meet this...

Page 344: ...e same as for the address lines The strobes for the transaction are supplied by POE or PWE depending on the transaction direction read or write ORx CSNT controls the timing for the appropriate strobe deassertion in write cycles When this attribute is asserted the strobe is deasserted one quarter of a clock before the normal case For example when ORx ACS 00 and ORx CSNT 1 PWE is deasserted one quar...

Page 345: ...ory systems that require more relaxed timing between signals When ORx TRLX 1 and ORx ACS 00 an additional cycle between the address and strobes is inserted by the MSC8113 memory controller See Figure 12 36 and Figure 12 37 Figure 12 35 GPCM Memory Device Timing ACS 00 CSNT 1 TRLX 0 Figure 12 36 GPCM Relaxed Timing Read ACS 1x SCY 1 CSNT 0 TRLX 1 Clock Address PSDVAL CSx PWE Data CSNT 1 ACS 11 ACS ...

Page 346: ...l bus clock POE always asserts on the rising clock edge after CS is asserted and therefore its assertion can be delayed along with the assertion of CS by programming ORx TRLX 1 POE deasserts on the rising clock edge coinciding with or immediately after CS deassertion 12 3 1 5 Programmable Wait State Configuration The GPCM supports internal PSDVAL generation It allows fast accesses to external memo...

Page 347: ...ev 0 Freescale Semiconductor 12 39 Figure 12 38 GPCM Relaxed Timing Write ACS 10 SCY 0 CSNT 1 TRLX 1 Figure 12 39 GPCM Relaxed Timing Write ACS 00 SCY 0 CSNT 1 TRLX 1 Clock Address PSDVAL CSx BCTL0 PWE POE Data ACS 10 CSNT 1 Clock Address PSDVAL CSx BCTL0 PWE POE Data ...

Page 348: ...nation of ORx TRLX and ORx EHTR Any access following a read access to the slower memory bank is delayed by the number of clock cycles specified in Table 12 17 See Figure 12 40 through Figure 12 43 for timing examples Table 12 17 TRLX and EHTR Combinations ORx TRLX ORx EHTR Number of Hold Time Clock Cycles 0 0 0 0 1 1 1 0 4 1 1 8 Figure 12 40 GPCM Read Followed by Read ORx 29 30 00 Fastest Timing C...

Page 349: ...miconductor 12 41 Figure 12 41 GPCM Read Followed by Read ORx 29 30 01 Figure 12 42 GPCM Read Followed by Write ORx 29 30 01 Clock Address PSDVAL CSx CSy BCTL0 POE Data Hold Time 1 cycle hold time allowed Clock Address PSDVAL CSx CSy BCTL0 POE Data Hold Time Long hold time allowed PWE ...

Page 350: ...uld be asserted for one cycle Because PGTA is internally synchronized bus termination may occur up to three cycles after PGTA assertion so for a read cycle the device must still output data as long as POE is asserted You select whether PSDVAL is generated internally or externally by means of PGTA assertion by resetting setting ORx SETA Figure 12 44 shows how a GPCM access is terminated by PGTA ass...

Page 351: ... after the cycle length defined in the ORx SCY Assertion of PGTA before the defined cycle length will also terminate the access Figure 12 44 External Termination of GPCM Access Figure 12 45 Internal Termination of GPCM Access Clock Address BCTL0 CSx POE Data PGTA PSDVAL csnt 1 and scy 0 Clock Address BCTL0 CSx POE Data PGTA PSDVAL csnt 1 and scy 0 SCY clock cycle ...

Page 352: ...irst write to OR0 the boot chip select can be restarted only on hardware reset Table 12 18 describes the initial values of the boot bank in the memory controller 12 3 4 Differences Between MPC8xx GPCM and MSC8113 GPCM If you are familiar with the MPC8xx GPCM you should know about the following differences between the MPC8xx GPCM and the MSC8113 GPCM External termination In the MPC8xx the external ...

Page 353: ... be controlled with a resolution of up to one quarter of the external bus clock period on the byte select and chip select lines Figure 12 46 shows the basic operation of each UPM The following events initiate a UPM cycle Any internal or external device requests an external memory access to an address space mapped to a chip select serviced by the UPM A UPM refresh timer expires and requests a trans...

Page 354: ...itiates one of the following patterns MxMR OP 00 Read single beat pattern RSS Read burst cycle pattern RBS Write single beat pattern WSS Write burst cycle pattern WBS These patterns are described in Section 12 4 1 1 Memory Access Requests A UPM refresh timer request pattern initiates a refresh timer pattern PTS An exception caused by a soft reset or the assertion of TEA while another UPM pattern i...

Page 355: ...bits 32 bytes For 64 bit accesses the burst cycle starts with one transfer start and ends after four transfer acknowledges A 32 bit device requires 8 data acknowledges an 8 bit device requires 32 See Section 12 1 8 Partial Data Valid Indication PSDVAL on page 12 10 The MSC8113 device defines two additional transfer sizes bursts of 128 bits 16 bytes and 192 bits 24 bytes The UPM treats these access...

Page 356: ... to the UPM Some memory devices have their own signal handshaking protocol to put them into special modes such as self refresh mode Other memory devices require special commands to be issued on their control signals such as for SDRAM initialization For these special cycles you must create a special RAM pattern that can be stored in any unused areas in the UPM RAM Then the RUN command is used to ru...

Page 357: ...clock phases shown reflect timing windows during which generated signals can change state The state of the external signals may change if specified in the RAM array at any positive edge of T1 T2 T3 or T4 there is a propagation delay specified in Section 2 Hardware Specifications of the MSC8113 Data sheet However only the CS signal corresponding to the currently accessed bank is manipulated by the ...

Page 358: ... by the access Figure 12 50 UPM Signals Timing Example Figure 12 51 RAM Array and Signal Generation CSx PGPL1 PGPL2 CST1 CST2 CST3 CST4 CST1 CST2 CST3 CST4 G1T1 G1T3 Word 1 Word 2 Bus CLK T1 T2 T3 T4 G1T1 G1T3 G2T1 G2T3 G2T1 G2T3 T1 T2 External Signals Timing Generator RAM Array CS Line Selector Byte Select Packaging Current Bank TSZ A 29 31 32 Bits 64 PGPL0 PGPL2 PGPL3 PGPL4 PGPL5 CS 0 7 11 BS PG...

Page 359: ...uring clock phase 2 0 The value of the CS line at the rising edge of T2 is zero 1 The value of the CS line at the rising edge of T2 is one CST3 2 Chip Select Timing 3 Defines the state of CS during clock phase 3 0 The value of the CS line at the rising edge of T3 is zero 1 The value of the CS line at the rising edge of T3 is one CST4 3 Chip Select Timing 4 Defines the state of CS during clock phas...

Page 360: ...of the PGPL0 line at the rising edge of T3 is one G1T1 12 General Purpose Line 1 Timing 1 Defines the state of PGPL1 during phase 1 2 0 The value of the PGPL1 line at the rising edge of T1 is zero 1 The value of the PGPL1 line at the rising edge of T1 is one G1T3 13 General Purpose Line 1 Timing 3 Defines the state of PGPL1 during phase 3 4 0 The value of the PGPL1 line at the rising edge of T3 is...

Page 361: ...hanism on page 12 60 If MxMR GPL_x4DIS 0 G4T3 is selected 0 The value of the PGPL4 line at the rising edge of T3 is zero 1 The value of the PGPL4 line at the rising edge of T3 is one If MxMR GPL_x4DIS 1 WAEN is selected 0 The PUPMWAIT function is disabled 1 A freeze in the external signals logical value occurs if the external UPMWAIT signal is detected asserted This condition lasts until UPMWAIT i...

Page 362: ...d EXEN in the RAM word is set the UPM branches to the EXS and begins operating as the pattern defined there specifies See Table 12 20 You should provide an exception pattern to deassert signals controlled by the UPM in a controlled fashion For DRAM control a handler should deassert RAS and CAS to prevent data corruption If EXEN 0 exceptions are deferred and execution continues After the UPM branch...

Page 363: ...h UPM allows a minimum time to be guaranteed between two successive accesses to the same memory bank This feature is critical when DRAM requires a RAS precharge time TODT turns the timer on to prevent another UPM access to the same bank until the timer expires The disable timer period is determined in MxMR DSx The disable timer does not affect memory accesses to different banks Note TODT must be s...

Page 364: ...PM affects only the assertion and deassertion of the appropriate BS signals their timing is specified in the RAM word The BS signals are controlled by the port size of the accessed bank the transfer size of the transaction and the address accessed Figure 12 53 shows how UPMs control BS signals Table 12 22 shows how BS signals affect 64 32 16 and 8 bit accesses Note that for a refresh timer request...

Page 365: ...A A 0 0 1 A A A A A A 0 1 0 A A A A A A A 1 0 0 A A A A A A A 1 0 1 A A A A A A 1 1 0 A A A A A A A 24 bits 3 bytes TS 0011 0 0 0 A A A A A A A A A 0 0 1 A A A A A A A A 1 0 0 A A A A A A A A A 1 0 1 A A A A A A A A 32 bits 4 bytes TS 0100 0 0 0 A A A A A A A A A A A 1 0 0 A A A A A A A A A A A 64 bits 16 bytes TS 0000 0 0 0 A A A A A A A A A A A A A A A Notes 1 A dash denotes a byte select BS is ...

Page 366: ...cution depends on the loop counter If the counter value is not zero the next RAM word executed is the loop start word Otherwise the next RAM word executed is the one after the loop end word Loops can execute sequentially but cannot nest Repeat Execution of Current RAM Word REDO The REDO function is useful for wait state insertion in a long UPM routine that would otherwise need too many RAM words S...

Page 367: ... value of the DLT3 bit in the same RAM word indicates when the data input is sampled by the internal 60x compatible bus master assuming that MxMR GPL_x4DIS 1 If G4T4 DLT3 functions as DLT3 and DLT3 1 in the RAM word data is latched on the falling edge of the external bus clock instead of the rising edge The data is sampled by the internal master on the next rising edge as required by the MSC8113 b...

Page 368: ...with the WAEN bit set the external PUPMWAIT signal is sampled by the memory controller in the following cycle and the request is frozen The PUPMWAIT signal is sampled at the rising edge of CLKOUT If PUPMWAIT is asserted and WAEN 1 in the previous UPM word the UPM is frozen until PUPMWAIT is deasserted The value of the external signal lines driven by the UPM remains as indicated in the previous wor...

Page 369: ... Accesses after a read access to the slower memory bank is delayed by the number of clock cycles specified by Table 12 17 TRLX and EHTR Combinations on page 12 40 For details see Section 12 3 1 6 Extended Hold Time on Read Accesses on page 12 40 Figure 12 55 Wait Mechanism Timing for Internal and External Synchronous Masters CSx PGPL1 WAEN Word n Word n 1 c1 c2 c3 c4 c5 c6 c7 c8 PUPMWAIT c9 c10 c1...

Page 370: ... 8 19 over A 17 28 choose MxMR AMx 001 Table 12 27 shows the register configuration Not shown are PURT and MPTPR which should be programmed according to the device refresh requirements Table 12 25 System Address Bus Partition A 0 7 A 8 19 A 20 28 A 29 31 msb of start address Row Column lsb Table 12 26 DRAM Device Address Port During an ACTIVATE command A 8 16 A 17 28 A 29 31 Row A 8 19 n c Table 1...

Page 371: ...ample Using UPM After timings are created programming the UPM continues with translating these timings into tables representing the RAM array contents for each possible cycle When a table is completed the global parameters of the UPM must be defined for handling the disable timer precharge and the refresh timer relative to Figure 12 56 Figure 12 56 DRAM Interface Connection to the 60x bus 64 Bit P...

Page 372: ...e of the MxMR OP 01 Figure 12 47 shows the first locations addressed by the UPM according to the different services required by the DRAM Table 12 28 UPMs Attributes Example Explanation Field Value Machine select UPMA BRx MS 0b100 Port size 64 bit BRx PS 0b00 No write protect R W BRx WP 0b0 Refresh timer value 1024 refresh cycles PURT PURT 0x0C Refresh timer enable MAMR RFEN 0b1 Address multiplex s...

Page 373: ... Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 Bit 24 exen 0 0 0 Bit 25 amx0 1 0 0 Bit 26 amx1 0 0 0 Bit 27 na 0 0 0 Bit 28 uta 0 0 1 Bit 29 todt 0 0 1 Bit 30 last 0 0 1 Bit 31 RSS RSS 1 RSS 2 Figure 12 57 Single Beat Read Access to FPM DRAM CLKOUT A BCTL0 D ...

Page 374: ...g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 Bit 24 exen 0 0 0 Bit 25 amx0 1 0 0 Bit 26 amx1 0 0 0 Bit 27 na 0 0 0 Bit 28 uta 0 0 1 Bit 29 todt 0 0 1 Bit 30 last 0 0 1 Bit 31 WSS WSS 1 WSS 2 Figure 12 58 Single Beat Write Access to FPM DRAM CLKOUT A BCTL0 D PSDVAL...

Page 375: ...1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 0 0 0 0 0 0 Bit 24 exen 0 0 1 0 1 0 1 0 0 Bit 25 amx0 1 0 0 0 0 0 0 0 0 Bit 26 amx1 0 0 0 0 0 0 0 0 0 Bit 27 na 0 0 1 0 1 0 1 0 0 Bit 28 uta 0 0 1 0 1 0 1 0 1 Bit 29 todt 0 0 0 0 0 0 0 0 1 Bit 30 last 0 0 0 0 0 0 0 0 1 Bit 31 RBS RBS 1 RBS 2 RB...

Page 376: ...0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 1 1 Bit 24 exen 0 0 1 Bit 25 amx0 1 0 0 Bit 26 amx1 0 0 0 Bit 27 na 0 0 1 Bit 28 uta 0 0 1 Bit 29 todt 0 0 1 Bit 30 last 0 0 1 Bit 31 RBS RBS 1 RBS 2 Figure 12 60 Burst Read Access to FPM DRAM LOOP CLKOUT A BCTL0 D PSDVAL CS1 PBS Row Co...

Page 377: ...t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 0 0 0 0 0 0 Bit 24 exen 0 0 1 0 1 0 1 0 0 Bit 25 amx0 1 0 0 0 0 0 0 0 0 Bit 26 amx1 0 0 0 0 0 0 0 0 0 Bit 27 na 0 0 1 0 1 0 1 0 0 Bit 28 uta 0 0 1 0 1 0 1 0 1 Bit 29 todt 0 0 0 0 0 0 0 0 1 Bit 30 last 0 0 0 0 0 0 0 0 1 Bit 31 WBS WBS 1 wBS 2 WBS...

Page 378: ...0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 Bit 24 exen 0 0 0 Bit 25 amx0 0 0 0 Bit 26 amx1 0 0 0 Bit 27 na 0 0 0 Bit 28 uta 0 0 0 Bit 29 todt 0 0 1 Bit 30 last 0 0 1 Bit 31 PTS PTS 1 PTS 2 Figure 12 62 Refresh Cycle CBR to FPM DRAM CLKOUT A BCTL0 D PSD...

Page 379: ...1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 Bit 24 exen 0 Bit 25 amx0 0 Bit 26 amx1 0 Bit 27 na 0 Bit 28 uta 0 Bit 29 todt 1 Bit 30 last 1 Bit 31 EXS Figure 12 63 Exception Cycle CLKOUT A BCTL0 D PSDVAL CS1 PBS CAS RAS RD WR A D ...

Page 380: ... in Table 12 29 The timing diagram in Figure 12 64 shows how the burst read access in Figure 12 59 can be reduced Table 12 29 UPMs Attributes Example Explanation Field Value Machine select UPMA BRx MS 0b100 Port size 64 bit BRx PS 0b00 No write protect BRx WP 0b0 Refresh timer value 1024 refresh cycles PURT PURT 0x0C Refresh timer enable MAMR RFEN 0b1 Address multiplex size MAMR AMx 0b010 Disable ...

Page 381: ... Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 DLT3 1 1 1 1 1 Bit 18 g4t3 0 0 0 0 0 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 0 0 Bit 24 exen 0 0 0 0 0 Bit 25 amx0 1 0 0 0 0 Bit 26 amx1 0 0 0 0 0 Bit 27 na 0 1 1 1 0 Bit 28 uta 0 1 1 1 1 Bit 29 todt 0 0 0 0 1 Bit 30 last 0 0 0 0 1 Bit 31 RBS RBS 1 RBS 2 RBS 3 RBS 4 Figure 12 64 FPM DRAM Burst Read Access Data...

Page 382: ...terface Connection to the System Bus 64 Bit Port Size Table 12 30 EDO Connection Field Value Example Explanation Field Value Machine select UPMA BRx MS 0b100 Port size 64 bit BRx PS 0b00 No write protect BRx WP 0b0 Refresh timer prescaler MPTPR 0x04 Refresh timer value 1024 refresh cycles PURT PURT 0x07 Refresh timer enable MAMR RFEN 0b1 Address multiplex size MAMR AMx 0b001 Disable timer period M...

Page 383: ...0h1 Bit 11 g1t1 0 0 0 0 0 Bit 12 g1t3 0 0 0 0 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 0 0 Bit 24 exen 0 0 0 0 0 Bit 25 amx0 1 0 0 0 0 Bit 26 amx1 0 0 0 0 0 Bit 27 na 0 0 0 0 0 Bit 28 uta 0 0 0 0 1 Bit 29 todt 0 0 0 0 1 Bit 30 last 0 0 0 0 1 Bit 31 RSS RSS 1 RSS 2 RSS 3 RSS 4 Figure 12 66 Single Be...

Page 384: ... Bit 11 g1t1 1 1 1 1 Bit 12 g1t3 1 1 1 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 0 Bit 24 exen 0 0 0 0 Bit 25 amx0 1 0 0 0 Bit 26 amx1 0 0 0 0 Bit 27 na 0 0 0 0 Bit 28 uta 0 0 0 1 Bit 29 todt 0 0 0 1 Bit 30 last 0 0 0 1 Bit 31 WSS WSS 1 WSS 2 WSS 3 Figure 12 67 Single Beat Write Access to EDO DRAM C...

Page 385: ...it 12 g1t3 1 1 1 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 0 0 1 0 Bit 22 redo1 0 0 1 0 Bit 23 loop 0 0 0 0 Bit 24 exen 0 0 0 0 Bit 25 amx0 1 0 0 0 Bit 26 amx1 0 0 0 0 Bit 27 na 0 0 0 0 Bit 28 uta 0 0 0 1 Bit 29 todt 0 0 0 1 Bit 30 last 0 0 0 1 Bit 31 WSS WSS 1 WSS 2 REDO1 REDO2 REDO3 WSS 3 Figure 12 68 Single Beat Write to EDO D...

Page 386: ...3 0 0 0 0 0 0 0 0 0 0 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 0 0 0 0 0 0 0 0 Bit 24 exen 0 0 0 1 0 1 0 1 0 0 0 Bit 25 amx0 1 0 0 0 0 0 0 0 0 0 0 Bit 26 amx1 0 0 0 0 0 0 0 0 0 0 0 Bit 27 na 0 0 1 0 0 1 0 1 0 0 0 Bit 28 uta 0 0 0 0 1 0 1 0 1 0 1 Bit 29 todt 0 0 0 0 0 0 0 0 0 0 1 Bit 30 last 0 0 0 0...

Page 387: ...Bit 12 g1t3 1 1 1 1 1 1 1 1 1 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 0 0 0 0 0 0 0 Bit 24 exen 0 0 0 1 0 1 0 1 0 0 Bit 25 amx0 1 0 0 0 0 0 0 0 0 0 Bit 26 amx1 0 0 0 0 0 0 0 0 0 0 Bit 27 na 0 0 0 1 0 1 0 1 0 0 Bit 28 uta 0 0 1 0 0 1 0 1 0 1 Bit 29 todt 0 0 0 0 0 0 0 0 0 1 Bit 30 last 0 0 0 0 0 0 0...

Page 388: ... g0h1 Bit 11 g1t1 1 1 1 1 1 Bit 12 g1t3 1 1 1 1 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 0 0 0 0 Bit 24 exen 0 0 0 0 0 Bit 25 amx0 0 0 0 0 0 Bit 26 amx1 0 0 0 0 0 Bit 27 na 0 0 0 0 0 Bit 28 uta 0 0 0 0 0 Bit 29 todt 0 0 0 0 1 Bit 30 last 0 0 0 0 1 Bit 31 PTS PTS 1 PTS 2 PTS 3 PTS 4 Figure 12 71 Refresh...

Page 389: ...Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 1 Bit 12 g1t3 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo0 Bit 22 redo1 Bit 23 loop 0 Bit 24 exen 0 Bit 25 amx0 0 Bit 26 amx1 0 Bit 27 na 0 Bit 28 uta 0 Bit 29 todt 1 Bit 30 last 1 Bit 31 EXS Figure 12 72 Exception Cycle for EDO DRAM CLKOUT A BCTL0 D PSDVAL CS1 PBS CAS RAS PGPL1 OE A RD ...

Page 390: ...ible and preferable to assert both UTA and LAST MCR is eliminated In the MSC8113 MCR is eliminated The function of RAM read write and RUN occurs via the MxMR UTA polarity is reversed In the MSC8113 UTA is active high TODT signal The disable timer control TODT and LAST bit in the RAM array word must be set together Otherwise TODT is ignored Refresh timer value is in a separate register In the MSC81...

Page 391: ...GTA to the memory controller when it can sample data Note that PGTA is also synchronized 12 5 2 Slow Devices Example When an SC140 core initiates a read cycle from a device with an access time that exceeds the maximum allowed by the user programming model there are two solutions The wait solution UPM The SC140 core generates a read access from the slow device The device in turn asserts the wait si...

Page 392: ...nal master is a 60x compatible master with additional functionality It has fewer restrictions than other 60x compatible masters Any port size 64 32 16 8 ECC and RMW parity Data pipelining 12 6 3 Extended Controls in 60x Compatible Mode In 60x compatible mode the memory controller provides extended controls for the glue logic The extended controls consist of the following Memory address latch ALE t...

Page 393: ... increments as programmed in the UPM or after each data beat is sampled in the GPCM or after each READ WRITE command in the SDRAM machine the SDRAM machine uses BADDR only for port sizes of 16 or 8 bits Note BADDR 27 31 signals are multiplexed with other signals see Section 3 4 Direct Slave Interface System Bus Ethernet and Interrupt Signals on page 3 4 In cases where BADDR 27 31 are not valid ext...

Page 394: ...frequency the one cycle delay for external masters can be eliminated by setting BCR EXDD The memory controller asserts PSDVAL for each data beat as to indicate data beat termination on write transactions and data valid on read transactions Figure 12 73 External Master Access GPCM CLKOUT A 0 28 A 27 31 TT TBST TSZ TS TA CS PWE OE Data Address Match and Compare Memory Device Access AACK ALE ...

Page 395: ... latch is controlled by ALE Also because the 64 bit port SDRAM has burst address increment logic BADDR is not needed Example Figure 12 74 External Master Configuration With SDRAM Device Example PSDAMUX TT 0 4 A 0 31 PSDDQM 0 7 CS1 TS TBST TA Arbitration signals D 0 63 SDRAM Multiplexer External Master Latch MA ALE BNKSEL 64 Bit Port Size TSZ 1 3 TSZ 0 2 pull down pull up TSZ0 PSDVAL MSC8113 LA 60x...

Page 396: ... of a 60x compatible mode write access to the shared SDRAM using the memory controllers SDRAM machine Figure 12 75 60x Compatible Mode SDRAM Access Clock A TS ALE AACK LA PSDAMUX MA DATA PSDVAL TA CS SDRAS SDCAS WE DQM D0 D1 addr 1 addr 1 column addr 2 column Page Miss Page Hit row addr 1 addr 2 addr 1 addr 2 ...

Page 397: ... UPM memory controller machines Note that while the address latch controlled by ALE latches A 0 26 the lsb of the address are driven by the BADDR 27 31 Figure 12 76 External Master Configuration With UPM Example TT 0 4 A 0 31 BCTL 0 1 CS1 TS TBST TA Arbitration signals D 0 63 External Master Latch ALE PGPL PBS 0 7 TSZ 1 3 TSZ 0 2 pull down pull up TSZ0 PSDVAL MSC8113 LA 60x Bus Signals MEMC signal...

Page 398: ...s to a SRAM like device with write latency 0 cycles and read latency 3 cycles using the memory controller UPM machine Figure 12 77 60x Compatible Mode UPM Access Clock A addr 1 addr 2 TS ALE AACK LA addr 1 addr 2 BADDR 0x0 0x8 0x10 0x18 DATA D0 D1_0 D1_1 D1_2 D1_3 PSDVAL TA CS PBS PGPL0 BCTL0 BCTL1 Note PGPL0 is a general purpose line using as an indicator for burst accesses ...

Page 399: ...bit port device using the GPCM memory controller machines Note that the address latch controlled by ALE latches A 0 31 Figure 12 78 External Master Configuration With GPCM Example TT 0 4 A 0 31 BCTL 0 1 CS1 TS TBST TA Arbitration Signals D 0 63 External Master Latch ALE PWE 3 0 POE TSZ 1 3 TSZ 0 2 pull down pull up TSZ0 PSDVAL MSC8113 LA 60x Bus Signals MEMC Signals 60x and MEMC Signals 64 bit Por...

Page 400: ...andles the IPBus peripherals and internal memories exactly like any other devices or memories The internal SRAM is accessed by the UPMC and mapped to CS11 The IPBus peripherals are accessed by the GPCM and mapped to CS9 12 7 1 UPM Programming Example Internal SRAM The SRAM is accessed via the UPMC on the local bus The code below is an example of UPM programming In this example the notation is base...

Page 401: ...to UPMC READ SINGLE move l 90051240 d7 move l d7 MCMR move l 00030040 d7 move l d7 MDR move w 0 r5 move l 00030045 d7 move l d7 MDR move w 0 r5 READ BURST move l 90051248 d7 move l d7 MCMR move l 00030c48 d7 move l d7 MDR move w 0 r5 move l 00030c4c d7 move l d7 MDR move w 0 r5 move l 00030c4c d7 move l d7 MDR move w 0 r5 move l 00030044 d7 move l d7 MDR move w 0 r5 move l 00030045 d7 move l d7 MD...

Page 402: ... the internal interface to the IPBus peripherals can occur in only a single access The following example shows how to program the GPCM for data transfer to the IPBus peripherals In this example the notation is based on the following You can change the base address BR9 and OR9 are the addresses of the GPCM registers move l 02181821 d0 base address for IPBus peripherals is 0x02180000 move l fffc0008...

Page 403: ...em Bus Assigned UPM Refresh Timer PURT page 12 111 System Bus Assigned SDRAM Refresh Timer PSRT page 12 111 Memory Refresh Timer Prescaler Register MPTPR page 12 112 System Bus Error Status and Control Registers TESCRx page 12 112 Local bus Error Status and Control Register L_TESCR1 page 12 112 BR 0 7 Base Registers 0 7 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BA Type R W Reset 0 0 0 0 0 0 0 0 0 ...

Page 404: ...ss Space on page 8 28 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BA PS DECC WP MS EMEMC ATOM DR V Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 BR11 Base Register 11 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot See Table 8 7 Banks 9 and 11 Address Space on page 8 28 Bit 16 17 18 19 20 21 22 23 24 25 ...

Page 405: ...write protection and the other does not 2 Due to the existing overlap between Banks 9 and 11 the value of BR9 WP should equal the value of BR11 WP when Bank 11 is valid that is when BR11 V 1 0 Read and write accesses are allowed 1 Only read access is allowed MS 24 26 000 Machine Select Specifies machine select for the memory operations handling and assigns the bank to the system bus or local bus i...

Page 406: ... not used for atomic operations 01 Read after write atomic RAWA 10 Write after read atomic WARA 11 Reserved DR 30 0 Data Pipelining See Section 12 1 Basic Architecture page 12 11 This feature is for memory regions that use parity checks and need to improve data set up time 0 No data pipelining is done 1 Data beats of accesses to the address space controlled by the memory controller bank are delaye...

Page 407: ...e maximum size of the memory bank should not exceed 128 MB 000000000000 4 GB 100000000000 2 GB 110000000000 1 GB 111000000000 512 MB 111100000000 256 MB 111110000000 128 MB 111111000000 64 MB 111111100000 32 MB 111111110000 16 MB 111111111000 8 MB 111111111100 4 MB 111111111110 2 MB 111111111111 1 MB LSDAM 12 16 Lower SDRAM Address Mask Note Reset LSDAM to 0x0 to implement a minimum size of 1 MB w...

Page 408: ...nected to the memory controller bank 0 Back to back page mode normal operation Page is closed when the bus becomes idle 1 Page is kept open until a page miss or refresh occurs IBID 27 Internal Bank Interleaving within Same Device Disable Disables bank interleaving between internal banks of a SDRAM device connected to the chip select line IBID should be set in 60x compatible mode if the SDRAM devic...

Page 409: ... The corresponding address bits are used in the comparison with address lines 17 18 Reserved Write to zero for future compatibility BCTLD 19 Data Buffer Control Disable Disables the assertion of BCTLx during access to the current memory bank See Section 12 1 Basic Architecture on page 12 9 Note After system reset OR0 BCTLD is cleared The boot sequence clears OR9 BCTLD 0 BCTLx is asserted upon acce...

Page 410: ...s selected to handle the memory access initiated to this memory region the access is terminated externally by asserting the external PGTA signal In this case PSDVAL is asserted one or two clocks later on the bus depending on the synchronization of PGTA See Section 12 3 2 Note After a system reset the OR0 SETA is cleared The boot sequence sets OR9 SETA 0 PSDVAL is generated internally by the memory...

Page 411: ...g a resource to reside in more than one area of the address map AM can be read or written at any time Note The boot sequence sets OR11 AM to 0b11111111111000000 0 Corresponding address bits are masked 1 The corresponding address bits are used in the comparison with address lines 17 18 Reserved Write to zero for future compatibility BCTLD 19 Data Buffer Control Disable Disables the assertion of BCT...

Page 412: ...0 Page Based Interleaving Selects the address multiplexing method PSDMR PBI works in conjunction with PSDMR SDA10 Note See Section 12 2 5 Bank Interleaving on page 12 17 0 Bank based interleaving 1 Page based interleaving normal operation RFEN 1 0 Refresh Enable Indicates that the SDRAM needs refresh services Note See the discussion of PSRT on page 12 111 0 Refresh services are not required 1 Refr...

Page 413: ...2 18 for details 000 A 12 14 001 A 13 15 010 A 14 16 011 A 15 17 100 A 16 18 101 A 17 19 110 A 18 20 111 A 19 21 SDA10 11 13 000 A10 Control With PSDMR PBI determines which address line can be output to PSDA10 during an ACTIVATE command when SDRAM is selected to control the memory access Note See Section 12 2 14 1 SDRAM Configuration Example Page Based Interleaving on page 12 29 for details For PS...

Page 414: ... or 8 LDOTOP RE 24 25 00 Last Data Out to Precharge Defines the earliest timing for PRECHARGE command after the last data was read from the SDRAM 00 0 clock cycles 01 1 clock cycle 10 2 clock cycles 11 Reserved WRC 26 27 00 Write Recovery Time Defines the earliest timing for PRECHARGE command after the last data was written to the SDRAM 01 1 clock cycle 10 2 clock cycles 11 3 clock cycles 00 4 clo...

Page 415: ... add a cycle for each SDRAM command 0 Normal timing for the control lines 1 All control lines except CS are asserted for two cycles CL 30 31 00 CAS Latency Defines the timing for first read data after SDRAM samples a column address 00 Reserved 01 1 10 2 11 3 Note See Section 12 2 10 SDRAM Signals Device Specific Parameters for additional recommendations for configuring this register MxMR Machine A...

Page 416: ...on pointed by MAD After the access the MAD field is automatically incremented For Read from array on the next memory access to a UPM assigned bank read the contents of the RAM location pointed by MAD into the MDR After the access the MAD field is automatically incremented For Run pattern on the next memory access to a UPM assigned bank run the pattern written in the RAM array The pattern run start...

Page 417: ...01 A7 110 A6 111 A5 GPL_x4DI S 13 0 GPL_A4 Output Line Disable Determines if the PUPMWAIT PGTA PGPL4 behaves as an output line controlled by the corresponding bits in the UPMx array GPL4x 0 PUPMWAIT PGTA PGPL4 behaves as PGPL4 UPMx G4T4 DLT3 is interpreted as G4T4 The UPMx G4T3 WAEN is interpreted as G4T3 1 PUPMWAIT PGTA PGPL4 behaves as PUPMWAIT UPMx G4T4 DLT3 is interpreted as DLT3 UPMx G4T3 WAE...

Page 418: ...d This field is incremented by one each time the UPM is accessed and the OP field is set to WRITE or READ MDR Memory Data Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MD Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MD Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 37 MDR Bit Descriptions Name Reset Description MD 0 31 0x0 Memory ...

Page 419: ...r period Compute the value of PURT according to the following equation This timer generates a refresh request for all valid banks that selected a UPM machine assigned to the system bus MxMR BSEL 0 and is refresh enabled MxMR RFEN 1 Each time the timer expires a qualified bank generates a refresh request using the selected UPM The qualified banks are rotating their requests Example For a 25 MHz bus...

Page 420: ...timer generates refresh requests for all valid banks that selected a SDRAM machine assigned to the system bus and is refresh enabled PSDMR RFEN 1 Each time the timer expires all banks that qualify generate a bank staggering auto refresh request using the SDRAM machine See Section 12 2 9 SDRAM Refresh on page 12 20 Example For a 25 MHz bus clock FBUS and a required refresh rate RefreshRate of 15 6 ...

Page 421: ... can be configured to support both external and internal masters or internal masters only This chapter describes the system bus signals and the operational protocols 13 1 System Bus Signals This section describes the external signals of the MSC8113 system bus It describes the individual signals showing behavior when a signal is asserted and deasserted when the signal is an input and an output and ...

Page 422: ...e repeated Table 13 6 on page 13 11 Data Arbitration The MSC8113 device uses these signals in external arbiter mode to arbitrate for data bus mastership The MSC8113 arbiter uses these signals to enable an external device to arbitrate for data bus mastership Table 13 7 on page 13 12 Data Transfer Transfer the data and ensure its integrity This signal group consists of the data bus and data parity s...

Page 423: ...ted Deassertion Occurs for at least one cycle following a qualified BG even if another transaction is pending Deassertion also occurs for at least one cycle following any qualified ARTRY on the bus It may also occur if the MSC8113 device cancels the bus request internally before receiving a qualified BG High Impedance Occurs during a hard reset or checkstop condition State Meaning Asserted Indicat...

Page 424: ...ertion Can occur on any cycle Once the external device assumes address bus ownership it does not begin checking for BG again until the cycle after AACK Deassertion Can occur when an external device must be kept from using the address bus The external device may still assume address bus ownership on the cycle that BG is deasserted if it was asserted the previous cycle with other bus grant qualifica...

Page 425: ...another device has begun a bus transaction and that the address bus and transfer attribute signals are valid for snooping Deasserted Has no special meaning Timing Comments Assertion Deassertion Must be asserted for one cycle only and then immediately deasserted Assertion may occur at any time during assertion of ABB Table 13 4 Address Bus Signals Name Type Description A 0 31 Input Output Output In...

Page 426: ...coding See Section n Transfer Code signals TC 0 2 The transfer code signals give supplemental information about the corresponding address mainly the source of the transaction as listed in Table 13 11 State Meaning Asserted Deasserted Gives supplemental information about the corresponding address mainly the source of the transaction Timing Comments Assertion Deassertion Same as A 0 31 High Impedanc...

Page 427: ...che blocks For these transactions TSIZ 0 3 are encoded as 0b0010 TBST is asserted and address bits A 27 28 determine which 32 bits are sent first The MSC8113 supports critical first burst transactions 32 bit aligned from the processor The MSC8113 transfers the critical 32 bits of data first followed by 32 bits from increasing addresses wrapping back to the beginning of the 8 level block as require...

Page 428: ...s the address tenure related signals to the high impedance state and samples ARTRY Deasserted Indicates that the address tenure must remain active and the address tenure related signals driven Timing Comments Assertion Occurs during the 60x compatible system bus slave access at least two clocks after TS Deassertion Occurs one clock after assertion ARTRY Input Address Retry Use in external master m...

Page 429: ...at the external device can with the proper qualification assume mastership of the data bus A qualified data bus grant is defined as the assertion of DBG deassertion of DBB and deassertion of ARTRY The requirement for the ARTRY signal is only for the address bus tenure associated with the data bus tenure about to be granted that is not for another address tenure available because of address pipelin...

Page 430: ...imes the data bus is driven depends on the transfer size port size and whether the transfer is a single beat or burst operation State Meaning Asserted Deasserted Represents the state of data during a data write Byte lanes not selected for data transfer do not supply valid data MSC8113 duplicates data to enable valid data to be sent to different port sizes Timing Comments Assertion Deassertion Init...

Page 431: ... odd number of bits including the parity bit are driven high The signal assignments are listed in the following table Timing Comments Assertion Deassertion The same as the data bus High Impedance The same as the data bus State Meaning Asserted Deasserted Represents odd parity for each byte of read data Parity is checked on all data byte lanes regardless of the size of the transfer Timing Comments ...

Page 432: ...ust wait to sample the data for reads Timing Comments Assertion Must not occur before the cycle after the assertion of AACK for the current transaction if the address retry mechanism is to be used to prevent invalid data from being used by the MSC8113 otherwise assertion can occur at any time during the assertion of DBB The system can withhold assertion of PSDVAL to indicate that the MSC8113 shoul...

Page 433: ...es the data tenure Deasserted Indicates that master must extend the current data beat insert wait states until data can be provided or accepted by the MSC8113 device Timing Comments Assertion Occurs on the clock in which the current data transfer can be completed Deassertion Occurs after the clock cycle of the final or only data beat of the transfer For a burst transfer TA may be deasserted betwee...

Page 434: ...3 local bus supports only internal masters with an internal arbiter and functions as a single master on the local memory bus 13 2 1 System Bus Operating Modes The system bus supports separate bus configurations for internal and external 60x compatible bus masters Single MSC8113 bus mode connects external devices by using only the memory controller The 60x compatible bus mode enables connections to...

Page 435: ... Rev 0 Freescale Semiconductor 13 15 Figure 13 2 Single MSC8113 Bus Mode A 0 31 TT 0 4 TSIZ 0 3 TBST GBL AACK ARTRY D 0 63 DP 0 7 TA TEA I O MEM Data Attributes Address Attributes Latch and Memory Controller Signals DRAM Mux Memory Control Signals MSC8113 ...

Page 436: ...controllers high end PowerQUICC II devices and or additional MSC81XXs Figure 13 3 shows how an external processor attaches to the MSC8113 Figure 13 3 60x Compatible Bus Mode BR BG TS A 0 31 TT 0 4 TSIZ 0 3 TBST GBL AACK ARTRY DBG D 0 63 DP 0 7 TA TEA I O Memory Data Attributes Address Attributes Memory Controller Signals External Device BR BG DBG Latch Latch and DRAM Mux Memory Control Signals MSC...

Page 437: ...ansfer After a device is granted address bus mastership it transfers the address The address signals and the transfer attribute signals control the address transfer Termination After the address transfer the system acknowledges that the address tenure is complete or that it must be repeated signalled by the assertion of the address retry signal ARTRY Data tenure Arbitration After address tenure be...

Page 438: ...serted while ABB and address retry ARTRY are deasserted ABB address bus busy A device asserts ABB to indicate it is the current address bus master Note that if all devices assert AACK with TS and would normally deassert ABB after AACK is asserted the devices can ignore ABB because the MSC8113 can internally generate ABB The MSC8113 ABB if enabled must be tied to a pull up resistor The following si...

Page 439: ...current data bus tenure completes Two address tenures can occur before the current data bus tenure completes The MSC8113 device also supports non pipelined accesses see Section 13 2 3 12 Pipeline Control 13 2 2 3 Memory Coherency Asserting the global GBL output signal indicates whether the current transaction must be snooped by other snooping devices on the bus Address bus masters assert GBL to in...

Page 440: ...t requested the bus Therefore when the parked device needs to perform a bus transaction it skips the bus request delay and assumes address bus mastership on the next cycle BR is not asserted and the access latency is shortened by one cycle The MSC8113 and external device bus devices qualify BG by sampling ARTRY in the deasserted state prior to taking address bus mastership The deassertion of ARTRY...

Page 441: ...ng the memory control hardware to decode a new set of address and control signals while the current data transaction finishes The MSC8113 pipelines data bus operations in strict order with the associated address operations Figure 13 6 shows how address pipelining allows address tenures to overlap the associated data tenures Figure 13 5 Address Bus Arbitration With External 60x Compatible Bus Maste...

Page 442: ... Bus Specification3 MSC8113 as Bus Master MSC8113 as Snooper MSC8113 as Slave Command Transaction Bus Transaction Transaction Source Action on Hit Action on Slave Hit 00010 Write Single beator burst write Single beator burst write Master Cancel reservation Write assert AACK and TA 01010 Read Single beator burst read Single beator burst read Master Not applicable to MSC8113 Read assert AACK and TA ...

Page 443: ...herency size of the bus is 32 bytes for the processor Data transfers that cross an aligned 32 byte boundary must present a new address to the bus at that boundary for proper snoop operation or must operate as non coherent with respect to the MSC8113 Note In case of a 60x compatible bus error or a local bus error the TC and TT fields are captured in the SIU TESCR1 or L_TESRC1 registers respectively...

Page 444: ...an address that is a multiple of four to be aligned Table 13 13 Burst Ordering Data Transfer 8 Byte Starting Address A 27 28 002 A 27 28 01 A 27 28 10 A 27 28 11 First data beat1 8B03 8B1 8B2 8B3 Second data beat 8B1 8B2 8B3 8B0 Third data beat 8B2 8B3 8B0 8B1 Fourth data beat 8B3 8B0 8B1 8B2 Notes 1 Each data beat terminates with one valid assertion of TA 2 A 27 28 specifies the first 8 bytes of ...

Page 445: ... you align code and data through software where possible 2 Bytes 0 0 1 0 0 0 0 OP0 OP1 0 0 1 0 0 1 0 OP2 OP3 0 0 1 0 1 0 0 OP4 OP5 0 0 1 0 1 1 0 OP6 OP7 4 Bytes 0 1 0 0 0 0 0 OP0 OP1 OP2 OP3 0 1 0 0 1 0 0 OP4 OP5 OP6 OP7 8 Bytes 0 0 0 0 0 0 0 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 Notes 1 OPx These lanes are read or written during that bus transaction OP0 is the most significant byte of a 2 byte operand ...

Page 446: ...side on bits D 0 7 The MSC8113 always tries to transfer the maximum amount of data on all bus cycles for a 2 byte operation it always assumes that the port is 64 bits wide when beginning the bus cycle for burst and extended byte cycles a 64 bit bus is assumed In Figure 13 7 Table 13 16 and Table 13 17 OP0 is the MSB of a 2 byte operand and OP7 is the LSB Figure 13 7 shows the device connections on...

Page 447: ... 40 47 48 55 56 63 0 7 8 15 16 23 24 31 0 7 8 15 0 7 Byte 0001 000 OP02 3 OP0 OP0 OP0 001 OP1 OP1 OP1 OP1 010 OP2 OP2 OP2 OP2 011 OP3 OP3 OP3 OP3 100 OP4 OP4 OP4 OP4 101 OP5 OP5 OP5 OP5 110 OP6 OP6 OP6 OP6 111 OP7 OP7 OP7 OP7 0 31 63 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 D 0 7 D 8 15 D 16 23 D 24 31 D 32 39 D 40 47 D 48 55 D 56 63 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 O...

Page 448: ...000 OP0 OP1 OP2 OP3 OP0 OP1 OP2 OP3 OP0 OP1 OP0 100 OP4 OP5 OP6 OP7 OP4 OP5 OP6 OP7 OP4 OP5 OP4 8 Bytes 0000 000 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 OP2 OP3 OP0 OP1 OP0 Notes 1 Address state is the calculated address for port size 2 OPx These lanes are read or written during that bus transaction OP0 is the MSB of a 2 byte operand and OP7 is the LSB 3 Denotes a byte not required during that rea...

Page 449: ...00 OP0 OP1 001 OP1 OP1 OP2 010 OP2 OP3 OP2 OP3 100 OP4 OP5 OP4 OP5 101 OP5 OP5 OP6 OP5 OP6 110 OP6 OP7 OP6 OP7 OP6 OP7 3 Bytes 0011 000 OP0 OP1 OP2 001 OP1 OP1 OP2 OP3 100 OP4 OP5 OP6 OP4 OP5 OP6 101 OP5 OP5 OP6 OP7 OP5 OP6 OP7 4 Bytes 0100 000 OP0 OP1 OP2 OP3 100 OP4 OP5 OP6 OP7 OP4 OP5 OP6 OP7 8 Bytes 0000 000 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 Notes 1 Address state is the calculated address for po...

Page 450: ...table for 9 byte 10 byte 16 byte 23 byte and 24 byte transactions Table 13 18 Address and Size State Calculations Size State Address State 0 4 Port Size Next Size State Next Address State 0 4 Byte x x x x x x Stop 2 Bytes x x x x 0 Byte Byte x x x x 1 x x 0 0 1 Byte x x 0 1 0 x x 1 0 1 Byte x x 1 1 0 x x x 0 1 2 Bytes Byte x x x 1 0 x x x x 0 Stop 3 Bytes x x 0 0 0 Byte 2 Bytes x x 0 0 1 x x 0 0 1...

Page 451: ...for write cycles when the MSC8113 initiates an access The 16 byte and 24 byte transfers are always 8 byte aligned and use a maximum 64 bit port size Table 13 19 Data Bus Requirements for Extended Read Cycles Transfer Size TSIZ 0 3 Address State A 29 31 Port Size Data Bus Assignments 64 Bit 32 Bit 16 Bit 8 Bit 0 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 0 7 8 15 16 23 24 31 0 7 8 15 0 7 5 Bytes 01...

Page 452: ...yte Stop 3 Bytes x x 0 1 0 Byte Byte x x 0 1 1 x x 1 0 0 x x 1 0 1 x x 0 1 0 Byte Byte x x 1 0 0 x x 1 0 0 x x 1 1 0 2 bytes x x 0 0 1 Byte 3 Bytes x x 0 1 0 x x 0 1 1 x x 1 0 0 5 Bytes x x 0 0 0 Byte 2 Bytes x x 0 0 1 x x 0 0 1 x x 0 1 0 x x 0 1 0 x x 0 1 1 x x 0 1 1 x x 1 0 0 x x 0 0 0 Byte 3 Bytes x x 0 1 0 x x 0 1 0 x x 1 0 0 x x 0 1 1 2 Bytes x x 1 0 0 x x 0 0 0 2 Bytes Byte x x 1 0 0 x x 0 1...

Page 453: ...n in Figure 13 8 Note that after recognizing an assertion of ARTRY and aborting the current transaction the MSC8113 cannot run the same transaction until the next time the bus is granted As a bus master the MSC8113 recognizes either an early or qualified ARTRY and prevents the data tenure associated with the retried address tenure If the data tenure has begun the MSC8113 terminates the data tenure...

Page 454: ...orm a new arbitration 13 2 3 11 Address Tenure Timing Configuration During address tenures initiated by 60x compatible bus devices the timing of the MSC8113 assertion of AACK is determined by the BCR APD bit and the pipeline status of the system bus Because the MSC8113 device can support one level of pipelining it uses AACK to control the system bus pipeline condition To maintain the one level pip...

Page 455: ...n occur for example when an external 60x bus slave does not support one level pipelining When the internal arbiter counts a pipeline depth of two two assertions of AACK before the assertion of the current data tenure it deasserts all address BG signals No pipeline mode The MSC8113 does not assert AACK until the corresponding data tenure ends The pipeline mode of operation is determined by the BCR ...

Page 456: ...serted after the data tenure is finished Assertion of DBB after the last TA causes improper operation of the bus MSC8113 internal masters do not assert DBB after the last TA If the data bus is not busy with the data of a previous transaction on the bus the external arbiter must assert DBG in the same cycle in which TS is asserted by a master that was granted the bus or in the following cycle If th...

Page 457: ...inates normally when TA is asserted The TA TEA and ARTRY signals terminate the individual data beats of the data tenure and the data tenure itself TA indicates normal termination of data transactions It must always be asserted on the bus cycle coincident with the data that it is qualifying The slave can withhold it for any number of clocks until valid data is ready to be supplied or accepted Asser...

Page 458: ...s Transfer Attribute Signals on page 13 22 Single beat transaction sizes can be 8 16 32 64 128 and 192 bits burst transactions are 256 bits Single beat and burst transactions are divided into a number of intermediate beats depending on the port size The MSC8113 asserts PSDVAL to mark the cycle in which data is accepted Assertion of PSDVAL in conjunction with TA marks the end of the transfer in sin...

Page 459: ...8 byte burst beat is divided into two port sized beats so that the four 8 byte sets are transferred in eight beats Figure 13 10 128 Bit Extended Transfer to 32 Bit Port Size Figure 13 11 Burst Transfer to 32 Bit Port Size CLKOUT ADDR ATTR TS AACK DBG PSDVAL D 0 31 TA D0 D1 D2 D3 CLKOUT ADDR ATTR TS AACK DBG PSDVAL D 0 31 TA D0 D1 D2 D3 D4 D5 D6 D7 ...

Page 460: ...re asserting TEA The data tenure is terminated by a single assertion of TEA regardless of the port size or whether the data tenure is a single beat or burst transaction This sequence is shown in Figure 13 12 where the data bus is busy at the beginning of the transaction and thus delays the assertion of DBG Note Data errors parity and ECC are reported by assertion of MCP rather than by assertion of...

Page 461: ...s 16 64 bits 1 K bits and can read up to four bursts A Host Transfer Acknowledge HTA extends accesses that the DSI is not ready to complete DSI read accesses from the MSC8113 internal or external address space are performed through buses shared by other internal clients For example to access one of the M1 memories the DSI must gain ownership of the internal local bus that it shares with the TDM th...

Page 462: ...egisters Overflow can occur only during broadcast accesses because there is no HTA signal to validate the write access See Section 14 3 5 To preserve data coherency a read access to the DSI stalls until all previous write accesses in the write buffer are complete When a host writes memory buffers to the device internal or external memory from the DSI port and then generates a Buffer Ready interrup...

Page 463: ... Lanes HD 0 7 HD 8 15 HD 16 23 HD 24 31 HD 32 39 HD 40 47 HD 48 55 HD 56 63 Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 8 bit 0 1 1 1 1 1 1 1 8 bit data 1 0 1 1 1 1 1 1 8 bit data 1 1 0 1 1 1 1 1 8 bit data 1 1 1 0 1 1 1 1 8 bit data 1 1 1 1 0 1 1 1 8 bit data 1 1 1 1 1 0 1 1 8 bit data 1 1 1 1 1 1 0 1 8 bit data 1 1 1 1 1 1 1 0 8 bit data 16 bit 0 0 1 1 1 1 1 1 16 bit data 1 1 0 0 1 1 1 1 16 ...

Page 464: ...R BEM bit is cleared When the MSC8113 memory space Bank 11 or external memory or one of the register spaces Bank9 or the system registers is accessed address bit HA29 is decoded During write accesses all four data lanes are written and are valid During read accesses all four data lanes are driven are valid and are read Table 14 2 Data Transfers for Single Accesses in 32 bit Data Bus Mode Transfer ...

Page 465: ...rom HD 32 63 according to the state of Byte Enables 4 7 in Little Endian mode HD 0 31 and Byte Enables 0 3 A read access to the MSC8113 registers reads the 32 bits indicated by HA29 The DSI drives all 64 bits HD 0 64 but only the 32 bits indicated by HA29 carry meaningful data If HA29 0 data is read to HD 0 31 in Little Endian mode HD 32 63 If HA29 1 data is read to HD 32 63 in Little Endian mode ...

Page 466: ...e internal and external available MSC8113 address space In Sliding Window Addressing mode the addresses used in the accesses to the memory space are formed by concatenating a window addressed by the 15 least significant DSI address signals HA 15 29 up to 15 base address bits DSWBAR BAVAL_H BAVAL_L The window size is 128 KB while the whole Internal address space is 2 MB and the External is of 2 GB ...

Page 467: ...A 11 31 A 11 14 DSWBAR BAVAL_L A 15 28 Host Address bits HA 15 28 A 29 31 2 MB Internal address space A 11 31 from Figure 14 1 yes no Access to Internal address space A 0 10 DSWBAR BAVAL_H A 11 14 DSWBAR BAVAL_L A 15 28 Host Address bits HA 15 28 A 29 31 External 32 address A 0 31 Access to External Memory address space Control Bits Status DCR SLDWA 1 DCR ADREN 0b0000 See page 14 4 and page 14 5 S...

Page 468: ...en external and internal access If the address MSB is 0 then the access is to the internal chip address space if the address MSB is 1 the access is to the external address space See Figure 14 4 and Table 14 3 for more information Figure 14 3 Full Address Mode Address Construction DCR ADREN 0b0000 yes no Access to External Memory Space yes no window slot 64 KB slot A 11 29 Host Address bits HA 11 2...

Page 469: ...DEXTBAR EXTBAVAL 9 DEXTBAR EXTBAVAL 10 HA 11 28 See Section 14 1 2 0b0010 4 MB HA 10 0b0011 8 MB HA 9 0b0100 16 MB HA 8 from Figure 14 3 Full Address Mode Address Construction on page Control Bits Status Access to External Memory address Space HA 11 DCR ADREN 1 yes no A 11 28 Host Address bits HA 11 29 A 29 31 2 MB Internal address space A 11 31 Access to Internal address space Access to External ...

Page 470: ...LE bit in the HRCW see Section 5 6 1 Hard Reset Configuration Word on page 5 13 and Section 3 1 4 in The Programming Environments for 32 Bit Processors that Implement the PowerPC Architecture MPCFPE32B AD MSC8113 internal memory is structured as big endian so the DSI reorganizes data structures written by little endian hosts When bit LTLEND is set the DSI translates all host accesses to the big en...

Page 471: ...nal selects the direction of the access read or write The HDBS 0 3 7 HDBE 0 3 7 signals are data byte strobes enables Dual Strobe mode DCR SNGLM 0 The HRDS HRDE signal is a read strobe enable The HWBS 0 3 7 HWBE 0 3 7 signals are write byte strobes enables Figure 14 5 and Figure 14 6 demonstrate the different access modes during read write cycles Figure 14 5 DSI Access Modes Write Access Figure 14...

Page 472: ... signal The DSI samples HBRST only at the beginning of an access and determines whether it is a burst access or a single access For a burst access the DSI ignores HBRST during the burst A host that uses LAST can tie it to the HBRST signal In a single access LAST is asserted on the first access in a burst access LAST is deasserted on the first access If the host performs a burst access the assertio...

Page 473: ...CHIPID value the DSI is accessed Assertion of the Host Transfer Acknowledge HTA signal indicates that the DSI is ready to sample the host data bus HD 0 63 and the host can terminate the access by deasserting HWBS The DCR HTAAD and DCR HTADT fields determine which of the following actions the DSI takes at end of an access the rising edge of HWBS Stop driving HTA DCR HTAAD 0 and DCR HTADT 00 no driv...

Page 474: ...ust wait until the previous DSI stops driving the HTA signal before it accesses the next device When the DCR HTAAD bit is set and the next access is to the same MSC8113 device the host must not start a consecutive access before the HTA signal is actively driven high by the previous access Figure 14 7 Asynchronous Write Using Dual Strobe Mode HCS HCID 0 3 HD 0 63 HWBS 0 7 HRDS HTA output HA 11 29 T...

Page 475: ...s without deasserting HCS between accesses When the DCR HTAAD and DCR HTADT are both cleared the host must ignore the HTA value from the start of the access until the DSI drives it to its correct value The required delay is defined in the AC characteristics section of the MSC8113 Technical Data sheet When the DCR HTAAD bit is set and the DCR HTADT bits do not equal 00 and if the next access is not...

Page 476: ...igh DCR HTAAD 1 and DCR HTADT 00 The DCR HTADT value indicates the amount of time to drive HTA This mode requires a pull up resistor on HTA In either case the host can start a back to back access without deasserting HCS between accesses When DCR HTAAD and DCR HTADT are both cleared the host must ignore the HTA value from the start of the access until the DSI drives it to its correct value The requ...

Page 477: ...dicates the amount of time to drive HTA This mode requires a pull up resistor on HTA In either case the host can start a back to back access without deasserting HCS between accesses When DCR HTAAD and DCR HTADT are both cleared the host must ignore the HTA value from the start of the access until the DSI drives it to its correct value The required delay period is defined in the AC characteristics ...

Page 478: ...ed immediately If the write buffer is full HTA assertion is delayed HTA is asserted for one HCLKIN cycle deasserted in the next cycle and stops being driven on the next rising edge of HCLKIN The host can start its next access to the same MSC8113 immediately in the next HCLKIN rising edge without deasserting HCS between accesses If the next access is not to the same MSC8113 then to prevent contenti...

Page 479: ... logic 1 in the next cycle and stops being driven on the next rising edge of HCLKIN The host can start its next access to the same MSC8113 immediately in the next HCLKIN rising edge without deasserting HCS between accesses If the next access is not to the same MSC8113 then to prevent contention on HTA the host must wait to access the next device until the previous DSI stops driving HTA There is no...

Page 480: ...ta lines and terminate the access The HTA is asserted earlier when the data for this access is already prefetched to the read buffer HTA is asserted for one HCLKIN cycle and driven to logic 1 in the next cycle It stops being driven on the next rising edge of HCLKIN The host can start its next access to the same MSC8113 device immediately in the next HCLKIN rising edge without deasserting HCS betwe...

Page 481: ...access The HTA is asserted earlier when the data for this access is already prefetched to the read buffer HTA is asserted for one HCLKIN cycle and driven to logic 1 in the next cycle It stops being driven on the next rising edge of HCLKIN The host can start its next access to the same MSC8113 immediately in the next HCLKIN rising edge without deasserting HCS between accesses If the next access is ...

Page 482: ...rite buffer is full HTA assertion is delayed After the last beat of the access HTA is driven to logic 1 and stops being driven on the next rising edge of HCLKIN The host can start its next access to the same MSC8113 immediately in the next HCLKIN rising edge without deasserting HCS between accesses If the next access is not to the same MSC8113 to prevent contention on HTA the host must wait to acc...

Page 483: ... write buffer is full HTA assertion is delayed After the last beat of the access HTA is driven to logic 1 and stops being driven on the next rising edge of HCLKIN The host can start its next access to the same MSC8113 immediately in the next HCLKIN rising edge without deasserting HCS between accesses If the next access is not to the same MSC8113 to prevent contention on HTA the host must wait to a...

Page 484: ...s access is already prefetched to the read buffer Typically after the first beat of the burst access HTA remains asserted until the end of the access After the last beat of the access HTA is driven to 1 and stops being driven in the next rising edge of HCLKIN The host can start its next access to the same MSC8113 device immediately in the next HCLKIN rising edge without deasserting HCS between acc...

Page 485: ...his access is already prefetched to the read buffer Typically after the first beat of the burst access HTA remains asserted until the end of the access After the last beat of the access HTA is driven to 1 and stops being driven in the next rising edge of HCLKIN The host can start its next access to the same MSC8113 device immediately in the next HCLKIN rising edge without deasserting HCS between a...

Page 486: ...corruption when the DER OVF bit is set any broadcast access is not written until the bit is reset Therefore after the last broadcast access and before any regular write access you must first read the DER OVF bit and reset it if it is set Note In Asynchronous mode write data from a previous access even if it is from a previous normal write access may be lost due to overflow during broadcast accesse...

Page 487: ...a bus mode is defined during the PORESET sequence by sampling the DSI64 signal when PORESET is deasserted see Chapter 5 Reset The HRCW source is defined during the PORESET sequence by sampling the CNFGS and RSTCONF signals when PORESET is deasserted see Chapter 5 Reset DSI endian modes are defined in the HRCW during the PORESET sequence see Chapter 5 Reset Note All other DSI configuration settings...

Page 488: ...base address so the host can reach the DCR to set SLDWA The default value of the DCR ADREN bits after the reset sequence ends is logic 0 which specifies that access to external memory space can be done only by the internal slot or sliding window DCR SLDWA bit is set If you do not use the DSI you can leave all the DSI pads floating except for the HCS and HBCS pads which must connect to the Vcc valu...

Page 489: ...ister DSR page 14 35 DSI Error Register DER page 14 36 14 5 1 Control Registers The control registers control the DSI operation and can be read and written during operation Note In asynchronous mode the first host access to the DSI after PORESET flow end must be a write access to the DCR to set the DSI to the correct mode of operation according to the host This action must be taken even if the def...

Page 490: ...resistor this results in a long delay for access termination 0 HTA is released in logic 0 1 1 HTA is released in logic 1 2 LEDS 5 6 0 Little Endian Data Structure When bit LTLEND in the HRCW see Chapter 5 Reset and bit DSRFA are set LEDS defines the data structure of the host DSI accesses For details see Section 14 2 4 00 8 bit data structure 01 16 bit data structure 10 32 bit data structure 11 64...

Page 491: ...AVAL_L Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EXTACC Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 8 DSWBAR Bit Descriptions Name Reset Description Settings BAVAL_H 0 10 0 Base Address Value High Stores the High bits of the External Access sliding window base address value See Figure 14 2 Sliding Window Mode Address Construction...

Page 492: ...t 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot See Table 8 7Banks 9 and 11 Address Space on page 8 28 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 BA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 10 DIBAR Bit Descriptions Name Reset Description BA 0 16 0 Base Address Must contain the same value as...

Page 493: ... host on the DSI updates these registers all registers must be written one after the other without any access to a different memory region in between DIAMR11 DSI Internal Address Mask Register 11 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AM Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 AM Type R W Reset 0 0 0...

Page 494: ...case of DCR ADREN set to 0b0011 or 0b0100 Any value between 0b0000 to 0b1111 4 31 0 Reserved Write to zero for future compatibility Notes 1 The reset value depends on the value of CHIP_ID 0 3 during PORESET signal deassertion 2 In asynchronous mode after a host write access to the DCIR the host must allow a period of 5 internal clock cycles between the end of the write access and the beginning of ...

Page 495: ...t allowed 0 DSI pads are enabled 1 DSI pads are disabled 2 31 0 Reserved Write to zero for future compatibility DSR DSI Status Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DSI64 DSISYNC LTLEND PPCLE RCWSRC Type R Reset X X X X X 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 14 15 DSR Bit Descriptions Name Reset De...

Page 496: ...64 during PORESET signal deassertion 2 The reset value depends on the value of DSISYNC during PORESET signal deassertion 3 The reset value depends on the value of bit LTLEND in the HRCW 4 The reset value depends on the value of bit PPCLE in the HRCW 5 The reset value depends on the value of CNFGS and RSTCONF during PORESET signal deassertion DER DSI Error Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 ...

Page 497: ...ion A write of a non zero value lock code is successful only if the current value of the semaphore is zero free This write is defined as a successful lock operation and the written value is the lock code A write of a non zero value lock code is ignored if the current value of the semaphore is non zero locked This write is defined as a failed lock operation since the coded semaphore is considered l...

Page 498: ...resented in Section 8 8 DSI Address Map on page 8 61 Figure 15 1 Hardware Semaphore Block Diagram HSMPR 0 7 Hardware Semaphore Register 0 7 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SMPVAL Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 1 HSMPRx Bit Descriptions Name Reset Description Setting...

Page 499: ... two different requestors A requestor can be any one of four external peripherals or sixteen internal requests generated by the DMA FIFO itself plus eight M1 flyby counters Using all the bus features the DMA controller accommodates a total of seven different issued bus transactions on both the system bus and the local bus For example each bus handles one transaction in the data phase one transacti...

Page 500: ...r Figure 16 1 DMA System Diagram Local Bus DREQ 1 4 DACK 1 4 DONE DRACK 1 2 External Peripherals Request Arbiter DMA FIFO External Memory M2 4 M1 8 M1 Counters Memory Memories Parameter RAM Channels Channel Group Flyby Bus System Local Bus Interrupt System GIC LIC System Bus Interface Interface ...

Page 501: ... acknowledge DACK Asserted by the DMA controller Qualification with the PSDVAL signal means that the data phase on the bus is generated by the DMA controller for the peripheral connected to this DACK It is asserted during the entire data phase The transaction is as follows Write transaction The peripheral samples the data during DACK with the qualifying PSDVAL signal Read transaction The periphera...

Page 502: ... peripheral request enabling an advanced peripheral to assert a new edge triggered request if needed DMA FIFO Handshake The internal FIFO signals the DMA logic that service is needed in the same way that a peripheral requests DMA service When a channel is enabled and the FIFO has space for at least one burst a hungry request is generated If at least one burst is valid in the FIFO a watermark reque...

Page 503: ...Semiconductor 16 5 Figure 16 2 Level Triggered Request and Expiration Timer CLOCK DREQ EXP_TIMER 2 1 0 QUAL_DREQ Expiration timer starts counting when peripheral receives DACK WR ADDR DATA TA TS DMA samples level DREQ as a new request when expiration time ends 2 DACK PSDVAL ...

Page 504: ...equest asynchronous DREQ input and the use of the DRACK protocol Figure 16 3 Edge Triggered Request Synchronous DREQ DRACK Signals Figure 16 4 Level Triggered Request Asynchronous DREQ DRACK Signals CLOCK DREQ DRACK QUAL_DREQ WR ADDR DATA TA TS DACK PSDVAL CLOCK DREQ QUAL_DREQ DRACK DACK TS WR ADDR PSDVAL DATA TA The DMA controller synchronizes the DREQ input To achieve the shortest latency betwee...

Page 505: ...ipheral of DACK and DONE Figure 16 5 Simultaneous Assertion of DACK and DONE Signals Figure 16 6 Sequential Assertion of DACK and DONE Signals CLOCK DREQ QUAL_DREQ DACK DONE DMA controller asserts DONE at the same time as DACK CLOCK DREQ QUAL_DREQ DACK DONE A peripheral should assert the DONE signal only after the DACK signal is asserted for this peripheral s last request It should deassert the DO...

Page 506: ... the peripheral PS is 32 bits and the DMA controller issues a 64 bit transaction the memory controller divides the 64 bit transaction into two 32 bit transactions See Section 12 8 Memory Controller Programming Model on page 12 95 The transfer size parameter TSZ determines the size of the transaction issued by the DMA controller after each peripheral request DREQ The size of the TSZ parameter range...

Page 507: ... one of the M1 memories operates as a peripheral This memory ignores the address phase It has an associated flyby counter which receives a DACK signal from the DMA controller The flyby counter should be programmed with the initial M1 memory address When the counter receives the asserted DACK qualified with PSDVAL it replaces the local bus address to the M1 memory by its own value The other memory ...

Page 508: ...n the system bus Two accesses are executed external memory to DMA FIFO and DMA FIFO to external peripheral Figure 16 7 External Memory to an External Peripheral on the System Bus Memory Controller System Bus Control Control 32 Bit Address 64 Bit Data Bridge Internal DMA Memory Peripheral Read Channel Write Channel Memory Memory Controller Local Bus 24 Bit Address 32 Bit Address 64 Bit Data 32 Bit ...

Page 509: ...esses are executed external peripheral to DMA FIFO and DMA FIFO to internal memory Figure 16 8 External Peripheral to Internal Memory Memory Controller System Bus Control Control 32 Bit Address 64 Bit Data Bridge Internal DMA Memory Peripheral Read Channel Write Channel Memory Memory Controller Local Bus 24 Bit Address 32 Bit Address 64 Bit Data 32 Bit Address Local Bus Local Bus System Bus System...

Page 510: ...es are executed external peripheral to DMA FIFO and DMA FIFO to external peripheral Figure 16 9 External Peripheral to an External Peripheral Memory Controller System Bus Control Control 32 Bit Address 64 Bit Data Bridge Internal DMA Peripheral Peripheral Read Channel Write Channel Memory Memory Controller Local Bus 24 Bit Address 32 Bit Address 64 Bit Data 32 Bit Address Local Bus Local Bus Syste...

Page 511: ...he system bus Two accesses are executed external memory to DMA FIFO and DMA FIFO to external memory Figure 16 10 External Memory to External Memory System Memory Controller System Bus Control Control 32 Bit Address 64 Bit Data Bridge Internal DMA Memory Memory Read Channel Write Channel Memory Memory Controller Local Bus 24 Bit Address 32 Bit Address 64 Bit Data 32 Bit Address Local Bus Local Bus ...

Page 512: ...al memory Two accesses are executed external memory to DMA FIFO and DMA FIFO to internal memory Figure 16 11 External Memory to Internal Memory Memory Controller System Bus Control Control 32 Bit Address 64 Bit Data Bridge Internal DMA Memory Peripheral Read Channel Write Channel Memory Memory Controller Local Bus 24 Bit Address 32 Bit Address 64 Bit Data 32 Bit Address Local Bus Local Bus System ...

Page 513: ...s are executed internal memory to DMA FIFO and DMA FIFO to internal memory Figure 16 12 Internal Memory to Internal Memory Memory Controller System Bus Control Control 32 Bit Address 64 Bit Data Bridge Internal DMA Memory Peripheral Read Channel Write Channel Memory Memory Controller Local Bus 32 Bit Address 64 Bit Data 32 Bit Address Local Bus Local Bus System Bus System Bus 24 Bit Address 64 Bit...

Page 514: ... The DMA controller only signals the peripheral and the transfer is performed directly between the external memory and the external peripheral Figure 16 13 Flyby Transfer From External Peripheral to External Memory Memory Controller System Bus Control Control 32 Bit Address 64 Bit Data Bridge Internal DMA Memory Peripheral Read Write Channel Memory Memory Controller Local Bus 24 Bit Address 32 Bit...

Page 515: ...K signal to the M1 flyby counter while M2 receives a real address The transfer executes directly between M1 and M2 Figure 16 14 Flyby Transfer Between Internal Memories M2 and M1 Memory Controller System Bus Control Control 32 Bit Address 64 Bit Data Bridge M1 M2 DMA Memory Peripheral Read Write Channel Memory Memory Controller Local Bus 24 Bit Address 32 Bit Address 64 Bit Data 32 Bit Address Loc...

Page 516: ...ine buffer descriptor BD composed of four 32 bit parameters The buffer is activated by a DMA channel when the channel wins DMA internal arbitration When the buffer is activated the DMA generates a bus transaction with the size described in the Buffer Descriptor Attributes Transfer Size field BD_ATTR TSZ and decrements the Buffer Descriptor Size DCPRAM BD_SIZE accordingly The address can be increme...

Page 517: ...y the fields that do not contain zero values Example 16 1 Behavior of DCPRAM Parameters if handle channel bdptr Any buffer type in steady state if BD_SIZE bdptr transfer_size BD_SIZE bdptr BD_SIZE bdptr transfer_size if NO_INC increment address mode BD_ADDR bdptr BD_ADDR bdptr transfer_size Any buffer type before last transaction elsif BD_SIZE bdptr 0 if NO_INC increment address mode BD_ADDR bdptr...

Page 518: ...ng 2 Program the DMA controller to use an additional small buffer and trigger the interrupt at the end of that dummy buffer The larger buffer transfer should be completed by the time the interrupt occurs Example 16 3 Double Interrupt Generation Scenario If the INTRPT bit is set in the BD_ATTR of the last buffer in a non continuous DMA transfer the DMA channel issues two interrupts one when the las...

Page 519: ...rupt is generated Burst transactions are used on the bus Figure 16 16 Simple Buffer Table 16 1 DCPRAM Values for a Simple Buffer BD DCPRAM Parameters Value Description 8 BD_ADDR BA 0x1000 External memory buffer current address BD_SIZE 0x200 Size of transfer left for this buffer BD_ATTR INTRPT 0x0 Do not generate an interrupt when buffer ends CYC 0x0 Increment BD_ADDR when the size reaches zero CON...

Page 520: ...s from base address 0x1000 Figure 16 17 Cyclic Buffer Table 16 2 DCPRAM Values for a Cyclic Buffer BD DCPRAM Parameters Value Description 4 BD_ADDR 0x1000 External memory buffer current address BD_SIZE 0x200 Size of transfer left for this buffer BD_ATTR INTRPT 0x1 Generate an interrupt when the buffer ends CYC 0x1 Reinitialize BD_ADDR to original value when the size reaches zero CONT 0x1 Continuou...

Page 521: ... at address 0x1000 and an interrupt is generated every 0x100 bytes The mode is continuous and addressing is sequential Note With an incremental buffer memory can be corrupted because of overwriting Figure 16 18 Incremental Buffer Table 16 3 DCPRAM Values for an Incremental Buffer BD DCPRAM Parameters Value Description 0 BD_ADDR 0x1000 External memory buffer current address BD_SIZE 0x100 Size of tr...

Page 522: ...reaches zero and an interrupt is generated when 0x200 byte blocks are read Figure 16 19 Chained Buffer Table 16 4 DCPRAM Values for a Chained Buffer and a Simple Buffer BD DCPRAM Parameters Value Description 0 BD_ADDR 0x1000 External memory buffer current address BD_ATTR INTRPT 0x0 Do not generate an interrupt when buffer ends CONT 0x1 Continuous mode Do not shut down the channel when size reaches...

Page 523: ...urce BDs must all be on the same bus 5 The destination BDs must all be on the same bus Using these steps prevents the need for switching between buses and using flushing 16 2 4 5 Complex Buffers Dual Cyclic Buffers A dual cyclic buffer scheme uses two buffers which can be any combination of the previously described buffers Two areas in memory are used to store data While one area is processed the ...

Page 524: ...D DCPRAM Parameters Value Description 0 BD_ADDR 0x1000 External memory buffer current address BD_SIZE 0x200 Size of transfer left for this buffer BD_ATTR INTRPT 0x1 Generate interrupt when buffer ends CYC 0x1 Reinitialize BD_ADDRESS to original value when size reaches zero CONT 0x1 Continuous mode Do not shut down the channel when size reaches zero NO_INC 0x0 Increment address after request is ser...

Page 525: ... 0x0 Do not generate an interrupt when the buffer ends CYC 0x0 Sequential address Increment BD_ADDR when the size reaches zero CONT 0x0 Non continuous mode the channel is closed when the size reaches zero NO_INC 0x1 Do not increment address after request is serviced TSZ 0x2 Maximum transfer size is two bytes RD 0x0 Write buffer BD_BSIZE Buffer base size of cyclic buffer 0x000000 0x000002 Internal ...

Page 526: ...0x2 Maximum transfer is two bytes RD 0x1 Read buffer BD_BSIZE 0x2 Buffer base size of cyclic buffer 3 BD_ADDR 0x08000 External memory buffer current address BD_SIZE 0x2 Size of transfer left for this buffer BD_ATTR INTRPT 0x0 Do not generate interrupt when buffer ends CYC 0x0 Sequential address Increment BD_ADDR when the size reaches zero CONT 0x1 Continuous mode Do not shut down the channel when ...

Page 527: ...hannel must be configured to perform the read from requestor memory into the DMA FIFO and the odd channel performs the write DMA FIFO to the other memory requestor Figure 16 22 DMA Configuration Flow Yes Peripheral is Is requestor an external peripheral No Set DCHCR ACTV bit of empty channel odd DCHCRx Configure DCPRAM for each buffer Configure DPCR SIUMCR GPIO Registers Set DCHCR ACTV bit of fill...

Page 528: ... register This priority is not changed by the DMA If two channels have the same priority the channel with the lower channel number has the higher priority Figure 16 23 illustrates the fixed priority flow 16 3 1 2 Round Robin Priority Mode The round robin algorithm can be described as two analog clocks One clock is for the channels associated with the system bus and the other clock is for the chann...

Page 529: ...The channel is non active The channel is not requesting service when the hand selects the channel The channel is not associated with the specific bus that is if a channel is associated with the system bus the local bus round robin clock always skips that channel If a channel requests service but the hand already passed it in the current round it is served during the next round Figure 16 24 Round R...

Page 530: ...es to ensure correct operation of the transfers The hierarcical arbitration may cause a high priority task to delay a low priority task pending in the bus arbiter Example 16 5 Multiple Device Arbitration Scenario Two DMA tasks DMA_1 and DMA_2 are activated to use the device local bus In addition the TDM interface uses the local bus The DMA controller uses fixed priority mode with the following set...

Page 531: ...quests Because the DMA controller uses pipelining up to 96 bytes can remain in the channel FIFO and not be delivered to the destination This data is transferred when the channel is enabled A DMA channel is terminated externally either when the peripheral asserts the DONE signal or you clear the DCHCR ACTV bit Either source channel or destination channel can be terminated Termination of the source ...

Page 532: ...TEA LDMTEA and PDMTER LDMTER respectively All other parameters such as DCPRAM BD_ADDR and DCPRAM BD_SIZE are undefined Channels on the other bus close normally as if you deasserted their corresponding DCHCR ACTV bit Note If the FLS bit in the BD_ATTR is set the DMA controller flushes the FIFO at the end of a transfer and issues an interrupt See the description of the FLS bit in Table 16 10 for det...

Page 533: ...n between a DMA requestor and the corresponding DMA channel You should program all the channel properties including the relevant line in DCPRAM before enabling the channel by asserting the ACTV bit The DMA logic can modify some fields in this register while the channel is active Note You can change the INT PRIO FRZ PPC and ACTV bits in the DCHCR while the channel is active The DMA controller can a...

Page 534: ...triggered DPL 9 0 User DREQ Polarity Indicates the polarity of the DREQ signal 0 DREQ is active high or rising edge triggered according to the DRS value 1 DREQ is active low or falling edge triggered according to the DRS value BDPTR 10 15 0 User DMA Buffer Pointer Value can be changed by the DMA logic in case of multi buffer channel Pointer to the line in DCPRAM which is assigned to this channel D...

Page 535: ...s not issue any transactions to this channel Data can be left in the FIFO store However upon unfreezing the channel no data or requests are lost 0 Channel operates normally 1 Channel is frozen INT 25 0 User Internal Requestor Indicates if requestor assigned to this channel is a peripheral 0 External request Transaction is initiated by a peripheral 1 Internal request Transaction between memory and ...

Page 536: ... Pin Configuration Register Bit 0 1 2 3 4 5 6 7 AM SDN0 SDN1 Type R W Reset 0 0 0 0 0 0 0 0 Table 16 8 DPCR Bit Descriptions Name Reset Description Settings 0 2 0 Reserved Write to zero for future compatibility AM 3 0 Arbitration Mode Selects the arbitration mode to use Note If Round Robin Priority mode is selected AM 1 then DCHCRx PRIO must be cleared for all channels 0 Fixed priority 1 Round Rob...

Page 537: ...rementing BD_BSIZE from BD_ADDR See Section 16 2 4 2 Cyclic Buffer on page 16 22 32 63 BD_SIZE Size of transfer left for the current buffer Contains the remaining size of the buffer This value decrements by the transfer block size each time the DMA controller issues a transaction until it reaches zero When BD_SIZE reaches zero the original value is restored to the value of BD_BSIZE Program BD_SIZE...

Page 538: ...m BD_ADDR CONT 2 Undefined Continuous Buffer Mode Indicates whether the buffer is to be closed when BD_SIZE reaches zero 0 Buffer closes when BD_SIZE reaches zero 1 Buffer continues operating when BD_SIZE reaches zero 3 Undefined Reserved Write to zero for future compatibility NO_INC 4 Undefined Increments Address Indicates the behavior of the buffer address 0 Increment address after request is se...

Page 539: ...n continuous buffers the FIFO is not flushed Note FLS is useful when buses change from one BD to the next FLS is also useful for continuous buffers in which the data must be flushed after the end of each buffer Whenever a flush occurs the DMA controller issues a flush interrupt The interrupt is necessary because it is the only indication that a flush occurs However this feature may not be desirabl...

Page 540: ...d when the transfer error address TEA is indicated on one of the buses In DSTR each of the 16 MSBs corresponds to an interrupt request from the corresponding channel If set a bit associated with a channel indicates that interrupt service is required A bit is cleared by writing a one to it Writing zero does not affect a bit value It is possible to clear several bits at a time DSTR is cleared at res...

Page 541: ...nsfer Error Address Register PDMTEA for the system bus or LDMTEA for the local bus to determine the address on the bus where the error occurred The channel that caused the bus error can be identified by reading the request number from the DMA Transfer Error Requestor Number Register PDMTER for the system bus or LDMTER for the local bus When a bus error occurs on a DMA transaction all DMA activity ...

Page 542: ...iption Settings DBER_P 0 0 DMA Channel System Bus Error Indicates that the DMA channel on the system bus has terminated with an error during a read or write transaction The DMA transfer error address is read from PDMTEA The channel number is read from PDMTER DBER_L 1 0 DMA Channel Local Bus Error Indicates that the DMA channel on the local bus has terminated with an error during a read or write tr...

Page 543: ...r error on the system bus The LDMTEA holds the system address accessed during a DMA transfer error on the local bus Both registers are undefined at reset xDMTEA DMA Transfer Error Address Registers Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDRESS Type R Reset Undefined Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Type R Reset Undefined ...

Page 544: ...MSC8113 Reference Manual Rev 0 16 46 Freescale Semiconductor Direct Memory Access DMA Controller ...

Page 545: ...IC and a local interrupt controller LIC The SC140 core interfaces directly to the PIC which handles interrupts from internal interrupt sources as well as some external interrupts The PIC also receives nine interrupts from the LIC which handles interrupts from the MSC8113 peripherals A Global Interrupt Controller GIC handles interrupts from the SIU internal signals and external signals and it also ...

Page 546: ...t request either to the SC140 cores or to an external signal line It receives interrupts from internal sources such as the periodic interrupt timer PIT or the Time Counter TMCNT and from external sources such as interrupt request lines IRQ For internal interrupt service it samples the requests and routes them globally to the LICs and the PICs of all SC140s Each SC140 core can separately enable the...

Page 547: ... IRQ SC140 Core Timers 32 DMA Controller TDMs GIC IRQ NMI 2 System Local Interrupt Controller LIC Group B Group A 8 8 8 8 8 8 24 15 GIC Virtual System 32 9 8 INT_OUT Generation 2 24 Interrupt Controller 2 8 8 Extended Core 0 1 2 15 IRQ 1 4 7 0 7 Global Channels Error Global 8 15 24 IRQ 2 3 5 8 2 2 1 8 8 8 2 Interface TEA Virtual Interrupts 1 1 1 4 Virtual NMI s Ethernet 6 5 PIC Controller General ...

Page 548: ...efined data The virtual interrupts are divided into three groups of eight interrupts each group routed to the LIC of one SC140 core Generates four virtual NMI pulses to the SC140 cores by a write access to a special NMI virtual address One SC140 core can assert the NMI of another SC140 core Collects interrupt sources from the UART SIU interrupt sources DMA system 15 external sources IRQ 1 15 and f...

Page 549: ...VISR Virtual Status Register LIC PIC Ex CORE 0 VNMIGR Virtual NMI Generator 8 1 32 32 4 IRQ GICR GEIER INT_OUT 24 PIT TCMNT UART DMA Level Edge Enable Disable GCIER Enable Disable IRQ 8 15 Ethernet 15 4 4 9 OR 1 4 SIU NMIs NMI Input 1 NMI_OUT Multiplex NMI OUT Select bit and Sample IRQ16 NMI0 NMI7 reset configuration 32 0 8 16 24 9 GISR Status 23 23 1 1 Ethernet 1 15 all except Ethernet Ctlr ...

Page 550: ...Each source can be internally enabled in the DMA controller see Chapter 16 Direct Memory Access DMA Controller One UART interrupt source which is a sum of five internal sources see Chapter 21 UART Table 17 1 lists the INT_OUT sources For details on GIC interrupt out source programming see GICR on page 17 26 and GEIER on page 17 27 Table 17 1 GIC INT_OUT Sources No Source Description 0 Reserved 1 R...

Page 551: ...operates as an edge source The boot program initializes the appropriate LIC inputs to Edge mode The Virtual Interrupt System also has a status register to indicate whether a virtual interrupt has been generated at least once while not preventing the generation of another interrupt The SC140 core that services the interrupt may clear this status bit by writing a value of one to it or it may ignore ...

Page 552: ...ts down most of its internal clocks as described in the following paragraphs The GIC has the following functionality in Low Power Stop mode Registers GCIER GEIER and GISR are write protected All the rest of the registers are accessible for both read and write The GISR read value is meaningless Regular Interrupts No new regular interrupts are captured Output interrupt lines to the SC140 cores and I...

Page 553: ...their polarity is hardwired to the actual source polarity Each interrupt source has a primary interrupt status bit for both level and edge modes and a second edge error status only in Dual Edge mode All status bits can be polled without actually generating an interrupt request All interrupt sources can be programmed to Level Edge or Dual Edge mode In Level mode the primary status register continuo...

Page 554: ... channel interrupt and one DMA error interrupt see Section 16 4 2 DMA Status and Interrupt Registers Typically the interrupt mapping is divided among the interrupt sources as DMA TDM Tx TDM Rx and TDM Error but any other combination is valid depending on the application Figure 17 3 LIC Block Diagram 2 24 to PIC0 IRQOUTA 0 3 8 8 Virtual Interrupts Timers DMA PIT TMCNT UART IRQ 1 4 7 4 to PIC0 IRQOU...

Page 555: ...ngle second edge error detection interrupt output line to the PIC For details on LIC interrupts received at the PIC see Table 17 8 17 1 2 1 Resolving LIC Interrupts by the SC140 Cores The SC140 cores support counting of leading bits using the CLB instruction This feature can be used to achieve fast priority resolution between interrupts having the same priority level that is mapped to the same PIC...

Page 556: ... must wait until the deasserted interrupt line propagates all the way though the LIC and the PIC to the SC140 core interrupt line The fastest way to work with LIC interrupt sources is programming the LIC to edge mode which enables fast propagation to the core interrupt input 17 1 2 2 Level Interrupt Mode When an interrupt is programmed to be handled in level mode the LIC continuously reflects the ...

Page 557: ...e sum of all EMA channel interrupts is routed globally to LIC group A of each SC140 enabling all channels be serviced by any SC140 core Typically each SC140 core gets DMA channel interrupts that are related to its own activity Following is an example of channel association to specific core interrupt lines One interrupt related to the local M1 flyby address counter One interrupt associated with an ...

Page 558: ...rror sum of TDM receive error detections 19 TDM3RSTE TDM3 Receive Second Threshold Event 20 TDM3RFTE TDM3 Receive First Threshold Event 21 TDM3TXER TDM3 Transmit Error sum of TDM transmit error detections 22 TDM3TSTE TDM3 Transmit Second Threshold Event 23 TDM3TFTE TDM3 Transmit First Threshold Event 24 DMA DMA global interrupt sum of all channel interrupts 25 DMA_ERROR DMA error 26 Reserved 27 Re...

Page 559: ...r 7 28 IRQ4 IRQ4 signal global 29 IRQ5 IRQ5 signal global 30 IRQ6 IRQ6 signal global 31 IRQ7 IRQ7 signal global Table 17 5 LIC Interrupt Group B Source for Core 1 No Source Description 0 DMA0 DMA channel 0 interrupt 1 DMA1 DMA channel 1 interrupt 2 DMA2 DMA channel 2 interrupt 3 DMA3 DMA channel 3 interrupt 4 DMA4 DMA channel 4 interrupt 5 DMA5 DMA channel 5 interrupt 6 DMA6 DMA channel 6 interrup...

Page 560: ...terrupt 3 DMA11 DMA channel 11 interrupt 4 DMA12 DMA channel 12 interrupt 5 DMA13 DMA channel 13 interrupt 6 DMA14 DMA channel 14 interrupt 7 DMA15 DMA channel 15 interrupt 8 TIMER0B Timer Block B Timer 0 Compare Flag 9 TIMER1B Timer Block B Timer 1 Compare Flag 10 TIMER2B Timer Block B Timer 2 Compare Flag 11 TIMER3B Timer Block B Timer 3 Compare Flag 12 TIMER8B Timer Block B Timer 8 Compare Flag...

Page 561: ...ht priority levels 25 VIRQ21 Virtual Interrupt Number 21 26 VIRQ22 Virtual Interrupt Number 22 27 VIRQ23 Virtual Interrupt Number 23 28 IRQ4 IRQ4 signal global 29 IRQ5 IRQ5 signal global 30 IRQ6 IRQ6 signal global 31 IRQ7 IRQ7 signal global Figure 17 4 PIC Block Diagram Table 17 6 LIC Interrupt Group B Source for Core 2 Continued No Source Description QBus 64 IPL 0 2 NMIR IR VAB 0 5 VAB_EN IRQ0 IR...

Page 562: ... edge triggered or level triggered and can be assigned a priority in the range 0 through 7 where priority 0 masks the interrupt On reset all IRQ signals are masked set to priority 0 and configured as level triggered On bootstrap IRQ20 see Table 17 8 is configured as edge triggered The NMI relative priority is fixed with NMI0 assigned the lowest priority and NMI7 the highest NMI signals are always ...

Page 563: ... instructions can be held in the allocated memory area To further extend the code size the use of service routines is recommended as shown in the example in Section 17 2 3 Clearing Pending Requests The address calculation is based on the VBA Register and the VAB vector as shown in Figure 17 5 Table 17 8 summarizes the routing of MSC8113 interrupts Unless stated otherwise all IRQ signals are level ...

Page 564: ...tual NMI of this core 0xE00 0x39 NMI1 Reserved 0xE40 0x3A NMI2 QBus controller memory write error 0xE80 0x3B NMI3 QBus controller misaligned program error 0xEC0 0x3C NMI4 QBus Controller bus error unmapped memory space 3 0xF00 0x3D NMI5 System interface block TEA on System bus 0xF40 0x3E NMI6 Reserved 0xF80 0x3F NMI7 SIU NMI from GIC for example Software watchdog external NMI parity error bus moni...

Page 565: ... this register must be cleared At bootstrap the VBA is initialized to the ROM base address 0x01077000 and the stack pointers of the cores are initialized to 0x01076f80 core 0 0x01076fa0 core 1 and 0x01076fc0 core 2 You can change these values before issuing a call to any subroutine since this address may not be available for the stack depending on the application At reset the SC140 cores disable a...

Page 566: ...pt Priorities BASE0 is 0x00f00000 ELIRE equ 00f09c20 PIC Edge Level Triggered Interrupt Priority Register E LICBICR1 equ 00f0ac48 LIC Group B Interrupt Configuration Register 1 LICBIER equ 00f0ac60 LIC Group B Interrupt Enable Register IRQ16 equ 30c00 GIC global interrupt routine IRQ18 equ 30c80 LICBICR1 interrupt routine VBA is set to 0x30000 offset 192KB move l 30000 vba assign priority 5 to GIC...

Page 567: ...ource To override write buffer delay read back the status register in which the bit had been cleared The PIC pending bit IPRB 0 is cleared by the interrupt propagation to IPRB 0 service routine to handle GIC move w 1 IPRB interrupt service routine to handle GIC rts 17 3 Interrupts Programming Model The interrupt registers are divided into three groups GIC LIC and PIC 17 3 1 GIC Programming Model T...

Page 568: ... one of eight interrupt pulses to the LIC of the selected SC140 both fields must be written in the same access The generated interrupt pulse also sets an interrupt status bit in the VISR selected by the concatenation of CORENUM VIRQNUM For example if virtual interrupt number 5 101 is generated to core number 2 10 VS number 21 10101 is set in the VISR A set status bit in the VISR does not block gen...

Page 569: ...ppropriate value to the CORENUM field generates an NMI pulse to the selected core The generated NMI pulse sets the NMI0 status bit in the selected SC140 PIC IPRB register See Table 17 8 CORENUM 22 23 Core Number Selection Set an interrupt to the selected SC140 00 Set an interrupt to core number 0 01 Set an interrupt to core number 1 10 Set an interrupt to core number 2 11 Reserved 24 28 Reserved W...

Page 570: ...ister Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VS24 VS16 VS8 VS0 ETHAE UART TMCNT PIT DMA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17...

Page 571: ... 0 3 0 Reserved Write to zero for future compatibility VS 24 16 8 0 4 7 0 Virtual Source 24 16 8 or 0 Interrupt 0 Disable interrupt 1 Enable interrupt and route the interrupt line to output INT_OUT 8 11 0 Reserved Write to zero for future compatibility UART 12 0 UART Interrupt 0 Disable interrupt 1 Enable interrupt and route the interrupt line to output INT_OUT TMCNT 13 0 TMCNT Interrupt 0 Disable...

Page 572: ...y GCIER GIC Core Interrupt Enable Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ETHAE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 13 GCIER Bit Descriptions Name Reset Description Settings 0 7 0 Reserved Write to zero for future compatibil...

Page 573: ... register and two status registers LIC Group A Interrupt Configuration Register LICAICR 0 3 page 17 30 LIC Group A Interrupt Enable Register LICAIER page 17 37 LIC Group A Interrupt Status Register LICAISR page 17 38 LIC Group A Interrupt Error Status Register LICAIESR page 17 39 LIC Group B Interrupt Configuration Register LICBICR 0 3 page 17 33 LIC Group B Interrupt Enable Register LICBIER page ...

Page 574: ...e mode selection for interrupt source 31 24 00 Level Mode The corresponding interrupt status bit in LICAISR continuously reflects the interrupt source read only 01 Single Edge Mode The interrupt second edge is ignored and the corresponding second edge status bit in LICAIESR is constantly cleared 10 Second Edge Detection Mode When the interrupt generates a second edge while the corresponding bit in...

Page 575: ... 00 Level Mode The corresponding interrupt status bit in LICAISR continuously reflects the interrupt source read only 01 Single Edge Mode The interrupt second edge is ignored and the corresponding second edge status bit in LICAIESR is constantly cleared 10 Second Edge Detection Mode When the interrupt generates a second edge while the corresponding bit in LICAISR is set the interrupt is captured b...

Page 576: ...dge status bit in LICAIESR is constantly cleared 10 Second Edge Detection Mode When the interrupt generates a second edge while the corresponding bit in LICAISR is set the interrupt is captured by the corresponding bit in the LICAIESR and the LICSEIRQ global interrupt line is asserted towards the PIC 11 Reserved IMAP 15 8 2 3 6 7 10 11 14 15 18 19 22 23 26 27 30 31 0 Map selection of interrupt sou...

Page 577: ...led interrupt line through IRQOUTA1 into the PIC 10 Route an enabled interrupt line through IRQOUTA2 into the PIC 11 Route an enabled interrupt line through IRQOUTA3 into the PIC LICBICR0 LIC Group B Interrupt Configuration Register 0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EM31 IMAP31 EM30 IMAP30 EM29 IMAP29 EM28 IMAP28 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Boot 0 0 0 0 0 0 0 0 0 0 0 0...

Page 578: ... Name Reset Description Settings EM 23 16 0 1 4 5 8 9 12 13 16 17 20 21 24 25 28 29 0 Edge mode selection for interrupt source 23 16 00 Level Mode The corresponding interrupt status bit in LICBISR continuously reflects the interrupt source read only 01 Single Edge Mode The interrupt second edge is ignored and the corresponding second edge status bit in LICBIESR is constantly cleared 10 Second Edge...

Page 579: ...0 Level Mode The corresponding interrupt status bit in LICBISR continuously reflects the interrupt source read only 01 Single Edge Mode The interrupt second edge is ignored and the corresponding second edge status bit in LICBIESR is constantly cleared 10 Second Edge Detection Mode When the interrupt generates a second edge while the corresponding bit in LICBISR is set the interrupt is captured by ...

Page 580: ... bit in LICBISR continuously reflects the interrupt source read only 01 Single Edge Mode The interrupt second edge is ignored and the corresponding second edge status bit in LICBIESR is constantly cleared 10 Second Edge Detection Mode When the interrupt generates a second edge while the corresponding bit in LICBISR is set the interrupt is captured by the corresponding bit in the LICBIESR and the L...

Page 581: ...3 4 5 6 7 8 9 10 11 12 13 14 15 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 22 LICAIER LICBIER Bit Descriptions Name Reset Description Settings E 31 0 31 0 0 Enable Disabl...

Page 582: ... edge interrupt is asserted at the PIC input Note If a status bit in LICAIESR or LICBIESR is set it blocks the reassertion of the corresponding status bit in LICAISR or LICBISR in second edge mode LICAISR LIC Group A Interrupt Status Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit ...

Page 583: ...LICAIESR or LICBIESR is set it blocks the reassertion of the corresponding status bit in LICAISR or LICBISR in second edge mode LICAIESR LIC Group A Interrupt Error Status Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ES31 ES30 ES29 ES28 ES27 ES26 ES25 ES24 ES23 ES22 ES21 ES20 ES19 ES18 ES17 ES16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3...

Page 584: ... interrupt 17 3 3 2 Interrupt Priority Structure and Mode Eight of the 32 PIC inputs are NMIs that cannot be programmed The NMIs are always assigned the highest priority regardless of their source Each of the remaining 24 inputs can be programmed to one of seven maskable priority levels IPL 0 through IPL 6 with a corresponding numeric value of 1 through 7 The highest maskable priority is IPL 6 Tab...

Page 585: ...terrupt Trigger Mode Bit PEDxx Trigger Mode 0 Negative Level Triggered 1 Negative Edge Triggered ELIRA Edge Level Triggered Interrupt Priority Register A Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PED3 PIL30 PIL31 PIL32 PED2 PIL20 PIL21 PIL22 PED1 PIL10 PIL11 PIL12 PED0 PIL00 PIL01 PIL02 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELIRB Edge Level Triggered Interrupt Priority Register B Bit 0 1 ...

Page 586: ... Level Triggered Interrupt Priority Register E Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PED19 PIL190 PIL191 PIL192 PED18 PIL180 PIL181 PIL182 PED17 PIL170 PIL171 PIL172 PED16 PIL160 PIL161 PIL162 Type R W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELIRF Edge Level Triggered Interrupt Priority Register F Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PED23 PIL230 PIL231 PIL232 PED22 PIL220 PIL221 PIL222 PED...

Page 587: ...ponding IRQ is acknowledged This feature is used for both IRQ and NMI signals to indicate to the PIC that the SC140 core has acknowledged the corresponding edge triggered interrupt source and that the PIC should ignore any request from the corresponding interrupt source until its next negative edge Each bit in the interrupt pending registers corresponds to an interrupt source as shown in Table 17 ...

Page 588: ...4 15 IP31 IP30 IP29 IP28 IP27 IP26 IP25 IP24 IP23 IP22 IP21 IP20 IP19 IP18 IP17 IP16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 29 IPRB Bit Descriptions Name Reset Description Settings IP31 0 0 Status of NMI Input 31 edge triggered only When this bit is set The PIC ignores any request from the interrupt source for this input until its next negative edge 0 No NMI pending 1 NMI acknowle...

Page 589: ...errupt programming model The VBA register allows you to determine the base address for the interrupt vector table by writing it to the VBA Register At reset the value of the 20 bit wide VBA Register is set to zero The offset for each exception vector is predefined There are 64 possible exception vector locations The spacing between two exception vectors is 32 words four full execution sets ...

Page 590: ...MSC8113 Reference Manual Rev 0 17 46 Freescale Semiconductor Interrupt Processing ...

Page 591: ...ccess to the Enhanced On Chip Emulator EOnCE module a dedicated block for debugging applications Therefore this chapter includes information on registers and functionality of the EOnCE module that are specific to the MSC8113 For details on the EOnCE module functionality see the SC140 DSP Core Reference Manual The SC140 core EOnCE module interfaces with the SC140 core and its peripherals non intrus...

Page 592: ... a target system Give entry to Debug mode Query identification information manufacturer part number and version from an MSC8113 based device Force test data onto the outputs of an MSC8113 based device while replacing its BSR in the serial data path with a single bit register Note Precautions must be taken to ensure that the IEEE Std 1149 1 like test logic does not interfere with non test operation...

Page 593: ...or that is sampled on the rising edge of TCK TDO A data output that can be tri stated and actively driven in the SHIFT IR and SHIFT DR controller states TDO changes on the falling edge of TCK TRST An asynchronous reset with an internal pull up resistor that provides initialization of the TAP controller and other logic required by the standard 5 Bit Instruction Register TDO TDI TMS TCK TRST 1 2 TAP...

Page 594: ...arc in Figure 18 2 represents the value of the TMS signal sampled on the rising edge of the TCK signal For a description of the TAP controller states refer to the IEEE Std 1149 1 documentation Figure 18 2 TAP Controller State Machine Test Logic Reset Run Test Idle Select DR_SCAN Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select IR_SCAN Capture IR Shift IR Exit1 IR Pause IR Exit2 IR U...

Page 595: ...ure enhancements and is decoded as BYPASS The parallel output of the Instruction Register is reset to 0b00010 in the test logic reset controller state which is equivalent to the IDCODE instruction During the CAPTURE IR controller state the parallel inputs to the instruction shift register are loaded with the code 01 in the least significant bits as required by the standard The most significant bit...

Page 596: ...rt number and version of a component to be determined through the TAP The ID Register configuration is as follows Bits 31 28 Version Information Bits 27 12 Customer Part Number Bits 11 1 Manufacturer Identity One application of the ID Register is to distinguish the manufacturer s of components on a board when multiple sourcing is used As more components emerge that conform to the IEEE Std 1149 1 i...

Page 597: ... directly to the EOnCE registers The EOnCE controller selects the specific EOnCE register connected between TDI and TDO depending on the EOnCE instruction being executed All communication with the EOnCE controller is through the SELECT DR SCAN path of the JTAG TAP Controller Before the ENABLE_EONCE instruction is selected the CHOOSE_EONCE instruction should be executed to define which EOnCE is to ...

Page 598: ...Note Use only the bits specified in Table 18 7 Other bits should be disregarded 11110 PRIVATE Manufacturer s private instruction Note Selecting this instruction many cause unpredictable operation of the device 11111 BYPASS Selects the single bit Bypass Register This creates a shift register path from TDI to the Bypass Register and finally to TDO circumventing the 573 bit BSR register This instruct...

Page 599: ...Reads and writes to internal EOnCE registers DEBUG_REQUEST or ENABLE_EOnCE instruction 18 4 1 Enabling the EOnCE Module The CHOOSE_EOnCE mechanism integrates multiple cores and thus multiple EOnCE modules on the same device Using the CHOOSE_EOnCE instruction you can selectively activate one or more of the EOnCE modules on the MSC8113 The EOnCE modules selected by the CHOOSE_EOnCE instruction are c...

Page 600: ..._EOnCE instructions More than one such instruction can execute and other instructions can be placed between them as well as between them and the CHOOSE_EOnCE instruction The EOnCE modules selected in the CHOOSE_EOnCE instruction remain selected until the next CHOOSE_EOnCE instruction The DEBUG_REQUEST or ENABLE_EOnCE instruction is shifted in during the SHIFT IR state as are all JTAG instructions ...

Page 601: ...gnal can be masked internally Monitor the core status by shifting out the contents of PIREG or by issuing an instruction and observing the TDO value shifted out Figure 18 6 Reading and Writing EOnCE Registers Via the JTAG TAP EOnCE module is connected to the TDO EOnCE module is ready to get command in ECR Write command into ECR register via shift dr or update dr Execute choose_eonce instruction in...

Page 602: ... you want some SC140 cores running and others in Debug mode you must disable either the inputs of the running SC140 cores or the outputs of the stopped SC140 cores To block EE0 set it as an input and mask the EE0 event in the event selector mask register see the next section on programming the ESEL_DM Register The EE1DEF bits program EE1 The signal can be programmed as an output of the EOnCE modul...

Page 603: ... MSC8113 bits 11 14 should always be written to 0 If EE0 is to be blocked bit 10 is cleared If bit 10 is cleared and the JTAG TAP controller does not issue a debug request the SC140 core can enter Debug mode only via events that relate to execution of instructions in the SC140 core for example EDCA events instructions or counter values This may create problems in synchronized entry to Debug mode i...

Page 604: ...C140 cores and the external EE0 signal see Figure 18 7 Therefore if any one SC140 core sets its EE1 output that is enters Debug mode or EE0 is asserted the debug request input on all SC140 cores is asserted EE1 is activated when at least one of the SC140 cores enters Debug mode Note The EE0 input initiates Debug mode and the EE1 output is the debug acknowledge indication Figure 18 7 Selected SC140...

Page 605: ...core is executing instructions that is not in Debug mode the access may not be serviced if the core is frozen After performing such an access the user or the driver software should wait for the update acknowledge indication If the update acknowledge upd_ack bit is not set see page 18 22 the debug software should retry the access Update acknowledge can be checked by using one of the two following m...

Page 606: ...he following steps before reading the buffer 1 Ensure that the program reading the trace buffer is in internal memory 2 Ensure that the local bus to M1 memory interface is not active 3 Flush the write buffer before reading the trace buffer If you read the trace buffer through the JTAG interface you must perform the following steps before reading the buffer 1 Ensure that the EOnCE module is in Debu...

Page 607: ...are two methods to ensure that the JTAG test logic does not conflict with the system logic by forcing TAP into the test logic reset controller state During power up TRST must be externally asserted to force the TAP controller into this state After power up TMS must be sampled as a logic one for five consecutive TCK rising edges If TMS either remains unconnected or is connected to VCC then the TAP ...

Page 608: ...number Refer to the website listed on the back cover of this manual for the information about the contents of this register for current device revisions 18 8 2 Boundary Scan Register BSR The MSC8113 BSR contains bits for most device signals and control signals All MSC8113 bidirectional signals have two registers for boundary scan data and are controlled by an associated control bit in the BSR The ...

Page 609: ...put Signal Cell O PIN Figure 18 9 Observe Only Input Signal Cell I OBS 1 1 MUX 1 1 MUX G1 C D C D From Last Cell Clock DR Update DR Shift DR 1 EXTEST or CLAMP Data from To Output Buffer 0 Otherwise Logic System To Next Cell G1 1 1 MUX G1 C D From Last Cell Clock DR Data to System Logic Input Pin Shift DR To Next Cell ...

Page 610: ...are associated with them The BSDL file on the product website describes the boundary scan serial string The three MSC8113 cell types described in this file are depicted in Figure 18 8 through Figure 18 10 which describe the cell structure for each type Figure 18 10 Output Control Cell IO CTL Figure 18 11 General Arrangement of Bidirectional Signal Cells 1 1 MUX G1 1 1 MUX G1 C D C D From Last Cell...

Page 611: ...pass Register is selected the shift register stage is set to a logic zero on the rising edge of TCK in the CAPTURE DR controller state 18 8 3 2 Identification Register When the Identification Register is selected the shift register stage is set to a logic value equal to IDCODE on the rising edge of TCK in the CAPTURE DR controller state It can then be shifted out in the SHIFT DR controller state S...

Page 612: ... Register GPR JTAG General Purpose Register JTAG port access only Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISRSEL 1 ISRSEL 0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 18 6 GPR Bit Descriptions Name Reset Description Settings ISRSEL 0 1 0 Instruction Status Core Select Defines the SC140 co...

Page 613: ...odule has executed the last instruction dispatched to it 0 EOnCE module has executed the last instruction dispatched to it 1 EOnCE module has not executed the last instruction dispatched to it core 1 cores 21 20 0 Core 1 Core Status Reflects the status of core 1 00 Core is executing instructions 01 Core is in Wait or Stop mode 10 Core is waiting for bus 11 Core is in debug mode core 1 upd_ack 19 0...

Page 614: ...MSC8113 Reference Manual Rev 0 18 24 Freescale Semiconductor Debugging ...

Page 615: ...each supporting 256 channels running at up to 66 Mbps with 2 4 8 and 16 bit data sizes The TDM bus connects gluelessly to most T1 E1frames as well as to common buses such as the ST BUS Each TDM module operates in independent or shared mode when receiving or transmitting data In independent mode there are different sync clock and data links for receive and transmit modules In shared sync and clock ...

Page 616: ... In addition fifteen of the signal lines can generate interrupts to the global interrupt controller Each signal is configured as an input or output with a register for data output that is read or written at any time All output signals can also be configured as open drain that is configured in an active low wired OR configuration on the board In this mode the signal drives a zero voltage but goes t...

Page 617: ...des the following slave interfaces to an external host Asynchronous interface giving the host single accesses with no external clock Synchronous interface giving the host single or burst accesses of 256 bits eight beats of 32 bits or four beats of 64 bits with its external clock decoupled from the MSC8113 internal bus clock Note For details see Chapter 14 Direct Slave Interface DSI 19 8 Ethernet C...

Page 618: ... local bus operates on the BUSES_CLOCK clock and the SQBus operates on CORES_CLOCK clock When a simultaneous request occurs from both the local bus and the SQBus the SQBus receives higher priority and wins the arbitration 19 10 Stop Options A Stop option is provided for power management It disables clocks for different modules and it functions differently for each slave module TDMs and timers ente...

Page 619: ...DSISTP bit and an empty write buffer no pending accesses Upon receiving a request from a stop request bit it continues to perform all the accesses waiting in the write buffer and does not perform prefetches into the read buffer see Chapter 14 Direct Slave Interface DSI Stop for Ethernet Controller The Ethernet Controller uses the stop bit for the clock stop Its stop acknowledge is conditioned by s...

Page 620: ...9 1 SCR Bit Descriptions Name Reset Description Settings 0 28 0 Reserved Write to zero for future compatibility ETH_STC 29 0 Ethernet Controller Stop Determines whether the Ethernet module is requested to enter Stop mode 0 Ethernet Controller is not requested to enter Stop mode 1 Ethernet Controller is requested to enter Stop mode GIC_STC 29 0 GIC Stop Determines whether the GIC module is requeste...

Page 621: ... Stop Ack Determines whether the Timer B module is in Stop mode 0 Timer B is not in Stop mode 1 Timer B is in Stop mode TimerA_STA 24 1 Timer A Stop Ack Determines whether the Timer A module is in Stop mode 0 Timer A is not in Stop mode 1 Timer A is in Stop mode TDM3_STA 25 1 TDM3 Stop Ack Determines whether the TDM3 module is in Stop mode 0 TDM3 is not in Stop mode 1 TDM3 is in Stop mode TDM2_STA...

Page 622: ...MSC8113 Reference Manual Rev 0 19 8 Freescale Semiconductor Internal Peripheral Bus IPBus ...

Page 623: ...orting 256 channels running at up to 66 Mbps with 2 4 8 and 16 bit word size The TDM bus connects gluelessly to most T1 E1 frames as well as to common buses such as the ST BUS Each TDM module operates in independent or shared mode when receiving or transmitting data In independent mode there are different sync clock and data links for receive and transmit In shared sync and clock mode the clock an...

Page 624: ...nc signals between the TDM modules and the MSC8113 signal lines The TDM is configured by all three SC140 cores through the interface to the IPBus see Figure 20 1 Data is received and transmitted from the TDM modules to the channel buffers through the local bus Figure 20 2 shows the TDM block diagram and the receive and transmit data flows The dashed line depicts the transmit data flow from the loc...

Page 625: ...ta_a d tdm3_tclk tdm3_rclk 4 4 TDM Arbiter 6 _ and TDM3TCLK tdm3_tsync TDM 3 3 Rx error int0 Rxthreshold1 int0 Rxthreshold2 int0 1 1 2 Rx error int1 Rx threshold1 int1 Rx threshold2 int1 2 Rx error int2 Rx threshold1 int2 Rx threshold2 int2 3 4 Rx error int3 Rx threshold1 int3 Rx threshold2 int3 4 TDM 1 TDM 2 tdm1_rdata_a d tdm1_rsync tdm1_rclk tdm1_tdata_a d tdm1_tsync tdm1_tclk TDM 0 tdm0_rdata_...

Page 626: ...Bus Multiplex tdmx_rdata_a tdmx_rdata_b tdmx_rdata_c tdmx_rdata_d tdmx_rsync tdmx_rclk 64 IP logic Status Registers Control Registers Configuration Registers 32 From I O Matrix To I O Matrix TDM x Machine 32 Notes X is the TDM number A m Law Data Conversion 64 64 128 Transmit data out Receive data flow Transmit data flow tdmx_tdata_a tdmx_tdata_b tdmx_tdata_c tdmx_tdata_d tdmx_tsync tdmx_tclk Rece...

Page 627: ...the network through a framer Figure 20 3 TDM Point to Point Configuration Figure 20 4 TDM Point to Multi Point Configuration TDMxTDAT TDMxTSYN TDMxTCLK TDMxRDAT TDMxRSYN TDMxRCLK TDMxRDAT TDMxRSYN TDMxRCLK TDMxTDAT TDMxTSYN TDMxTCLK On Board Clock Generator On Board Clock Generator MSC8113 MSC8113 TDMxTDAT TDMxTCLK TDMxTSYN TDMxRDAT TDMxRCLK TDMxRSYN From Receiver Clock Generator From transmitter ...

Page 628: ...nnels for each TDM module is unified and it can be 2 4 8 and 16 bits The receive channel size is determined by the RCS field in the TDMxRFP the transmit channel size is determined by the TCS field in the TDMxTFP refer to page 20 49 When the TDM connects to a T1 framer the RT1 field in the TDMx Receive Frame Parameters Register TDMxRFP see page 20 47 and the TT1 field in the TDMx Transmit Frame Par...

Page 629: ... TDMxRDAT receive data Channel 0 Channel 1 Channel 0 Channel 1 Channel0 TDMxTCLK transmit clock TDMxTSYNC transmit sync TDMxTDAT channel 0 channel 1 Channel 2 Channel 3 Channel 0 Receive Frame parameters RNCF 7 0 8 1 2 channels RCS 4 1 2 bits and RT1 0 nonT1 TNCF 7 0 8 3 4 channels TCS 4 3 4 bits and TT1 0 non T1 Transmit Frame parameters Channel size Frame Size TDMxT RCLK TDMxT RSYN TDMxT RDAT FA...

Page 630: ...hould be identical for the TDM modules that share signals There are only three possibilities for sharing TDMs TDM0 and TDM1 TDM0 TDM1 and TDM2 or TDM0 TDM1 TDM2 and TDM3 Figure 20 8 illustrates a common receive sync receive clock transmit sync and transmit clock for TDM 0 and TDM 1 When the CTS bit of the TDMx General Interface Register see page 20 36 is cleared the TDM modules do not share signal...

Page 631: ...0 TDM0RSYN Rxdata 1 TDM0RCLK Txdata 1 TDM0TDAT Txdata 0 TDM0TSYN Txsync common TDM0TCLK Txclk common TDM1RDAT Rxdata 2 TDM1RSYN Rxdata 3 TDM1RCLK Txdata 3 TDM1TDAT Txdata 2 TDM1TSYN Rxsync common TDM1TCLK Rxclk common TDM2RDAT Rxdata 4 TDM2RSYN TDM2RCLK Txdata 5 TDM2TDAT Txdata 4 TDM2TSYN TDM2TCLK TDM3RDAT Rxdata 6 TDM3RSYN Rxdata 7 TDM3RCLK Txdata 7 TDM3TDAT Tx data 6 TDM3TSYN TDM3TCLK RTSAL 3 0 ...

Page 632: ...transmit links is output When bits 3 and 2 of the RTSAL field in the TDMx General Interface Register see page 20 36 equal 0b11 the receive and the transmit are shared as illustrated on the right side of Figure 20 11 The transmit and the receive share the Frame Sync FSYN the Frame Clock FCLK and the data signals In this mode the data links are full duplex and are used for both transmit and receive ...

Page 633: ... are always received transmitted on the same link one after another Figure 20 12 Receive and Transmit Totally Independent Figure 20 13 Shared Sync and Clock Two Active Data Links TDMxRCLK TDMxRSYN TDMxRDAT Channel N 1 Channel 0 Channel 1 Channel 2 TDMxTCLK TDMxTSYN TDMxTDAT Channel M 1 Channel 0 Channel 1 Channel 2 X The TDM number N The number of channel in the receive TDM frame M The number of c...

Page 634: ...er second so higher bit rates can be processed per second Table 20 2 describes the maximum bit rate as a function of these parameters Factors other than the width of the channel can affect the bit rate for example capacity on the data links Figure 20 14 Receive and Transmit Share Sync Clock and Data Four Active Links Table 20 1 Maximum Number of Channels Per Active Link Number of Active Links 1 Ac...

Page 635: ...m the TDMx receive local memory see Chapter 8 Memory Map This memory can contain 1 2 4 8 16 or 32 indexed buffers starting at 0 Each buffer contains multiple frames The number of buffers used to store the transmitted data is indicated in the TNB field of the TDMx Transmitter Number of Buffers Register TDMxTNB Channel C in buffer B is the 8 bytes starting at 256 TNB 1 B C 8 Figure 20 15 shows an ex...

Page 636: ...LSB of the memory row Figure 20 17 describes a row in the TDMx local memory in which the 0x00112233 data is received before the 0x44556677 data In this example the data to be read through the IPBus interface from address 0x1000 offset from TDMx Receive Local Memory is 0x44556677 and the data to be read from address 0x1004 offset from TDMx Receive Local Memory is 0x00112233 Figure 20 15 TDM Local B...

Page 637: ...MxTIR TSO 1 Task Register Control the length of the sync_out signal If the SOL bit is clear then the sync_out width is one transmit bit else the sync_out length is one transmit channel TDMxTIR SOL page 20 45 Control the transmit clock edge on which the sync_out is driven out If the SOE bit is clear the sync_out is driven out on the rising edge of the transmit clock TDMxTIR SOE page 20 45 Control t...

Page 638: ...pled driven out at the same clock edge is TFSD 1 And when the sync and the data sampled driven out at different clock edge is TFSD 1 0 5 Table 20 5 Transmit and Receive Frame Configuration Control Register Which receive clock edge samples the receive frame sync If RFSE is clear the receive frame sync is sampled on the rising edge of the receive clock TDMxRIR RFSE bit page 20 43 Which transmit cloc...

Page 639: ...ta and the sync drive sample at the different edges TDE 1 TFSE 0 TFSD 00 Start of the frame 0 5 bit delay data driven out 0 5 bits before the sync is sampled The data and the sync sample with the same edge Two bit delay The data and the sync sample with different edges RDE 1 RFSE 0 RFSD 10 Start of the frame 2 5 bit delay TDMxTCLK TDMxTSYN TDMxTDAT D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 Chan...

Page 640: ... beginning of every frame The frame sync synchronization is necessary when more than one device drives the bus Figure 20 22 shows the state diagram of the frame sync synchronization Figure 20 20 Frame Sync Configuration At T1 Mode Figure 20 21 Frame Sync Polarity TDMxRCLK TDMxRSYN TDMxRDAT D0 D1 D7 D0 D7 FA D6 Start of the Frame No sync delay The data and the sync sample with the same edge RDE 0 R...

Page 641: ...recognized early the state returns to the WAIT state Otherwise the machine transfers to the SYNC state at the last bit of the TDM frame During PRESYNC state data is neither received nor transmitted SYNC 0b10 At least one sync event has appeared exactly where it was expected This state is maintained as long as the sync event continues to appear where expected If a sync is missed or a sync event is ...

Page 642: ...e TDMxTER TSE bit see page 20 66 is asserted If the TDMxTIER TSEIE bit see page 20 61 is also set a transmit error interrupt is generated The frame sync synchronization state can identify different problems In the initial design stages the frame sync summarization state indicates whether the TDM programming matches the actual TDM stream During operation the synchronization state and the error inte...

Page 643: ...he maximum receive data latency is calculated as maximum receive data latency RCDBL RCS receive frame time When the amount of received data exceeds the size of the TDM receive local memory the TDMxRER OLBE bit is set see page 20 65 If the TDMxRIER OLBEE bit is also set an error interrupt is generated This error should not occur during normal operation It indicates that the TDM has not received eno...

Page 644: ... transmit data channel is stored in a different buffer mapped on the internal local bus This buffer can be located in the M1 memory of one of the SC140 cores or in the M2 memory which is shared by all the SC140 cores 20 2 6 1 Data Buffer Size and A μ law Channels Data buffer size is identical for all receive channels belonging to a TDM module and is indicated in the TDMxRDBS RDBS field Data buffer...

Page 645: ...uffer Displacement TDMxRDBDR RDBD field page 20 62 Adding this field to the first byte of receive data buffer n indicates the location to which the TDM will write next RGBA 16 RCDBA RDBD is the current write pointer to the receive data buffer n In most cases the RDBD can be used to indicate that data is written to the buffer and can be processed However in some cases in which the local bus is extr...

Page 646: ...first byte of transmit data buffer n indicates the location to which the TDM will read next TGBA 16 TCDBA TDBD is the current read pointer of transmit data buffer n The TDBD can be used to show which data is already read from the buffer so that the buffer can be filled with new data Note For A μ law channels the RDBD and the TDBD fields should be doubled before use ...

Page 647: ...TDMxRGBA 16 Receive Data Buffer Memory Map 8 bytes channel k A μ law active transparent channel transparent channel Receive Data Buffer i RDBS Bytes RDBSx2 Bytes RCPRk RCDBA Transmit Global Base Address TDMxTGBA 16 Transmit Data Buffer channel m A μ law active Bytes TDBS Bytes TDBSx2 RCPRi RCDBA Transmit data buffer l TCPRl TCDBA TCPRm TCDBA 0000 RCDBA RCPRx RGBA RGBA Receive data buffer i base ad...

Page 648: ...he byte to which the second threshold TDMxRDBST RDBST points Meanwhile the TDM keeps writing new data to the first part of the buffer Note The TDMxRER RFTE and TDMxRER RSTE bits are set and the associated interrupts are generated when the TDM performs the first access after the buffers reach the associated threshold level and not immediately when the threshold is reached The transmit data buffers ...

Page 649: ...ointers for transparent and A μ law channels The TDMxRDBFT RDBFT TDMxRDBST RDBST TDMxTDBFT TDBFT and TDMxTDBST TDBST fields are control fields and can therefore be updated while the TDM is active For example to invoke an interrupt for each 64 bits written to the local bus memory the interrupt routine that handles the receive first threshold interrupt should include If TDMxRDBFT RDBFT TDMxRDBS RDBS...

Page 650: ...ls 0 and 1 are located in the TDMxRCPR0 register Unified Buffer mode essentially creates a one channel link that is typically used in point to point connections When TDMxTFP TUBM 1 data is transmitted from one buffer into two transmit channels each four eight or sixteen bits wide Figure 20 27 describes the transmit data flow in independent data buffers mode TDMxTFP TUBM 0 Each data channel transfe...

Page 651: ...he transmitter is configured as Unified Buffer Mode the TRDO bit in the TDMxTIR should be cleared 20 2 7 Adaptation Machine Each TDM module has an adaptation machine that counts the number of bits between frame SYNCs This module can be used to determine the frame size in bits MSC8113 boot code uses this module during boot from TDM to determine whether the TDM boot master is a T1 193 bits or an E1 ...

Page 652: ...ptation Status Register TDMxASR The following steps define how to use the adaptation machine 1 Configure the LTS bit to define whether the adaptation machine is fed with the Transmit or with the receive frame sync and clock See the TDMxACR TDMx Adaptation Control Register on page 20 53 2 Set the AME bit in the TDMxACR to enable the adaptation machine 3 Wait for AMS bit in the TDMxASR to be set to ...

Page 653: ... registers get the system clock only at reset or during an IPBus access Each TDM has a status bit in the Stop Ack Status Register SASR see page 19 7 which indicates the TDM system clock activity status 20 4 Channel Activation The TACT and RACT bits in the Transmit Receive Channel Parameter Registers see page 20 58 and page 20 59 are enabled during the receiver transmitter operation to control the ...

Page 654: ...0 0x0417 the channel location in buffer 2 0x0610 0x0617 the channel location in buffer 3 20 5 Loopback Support In Loopback Test mode the receiver receives the same data that is transmitted The frame clock should supply to the TDM and the frame sync can be generated internally or supplied externally The receiver and transmitter share the frame sync frame clock and data links RTSAL 3 2 0b11 The numb...

Page 655: ...e page 20 54 enables the receiver part of the TDM module When TDMxRCR REN is clear the receive TDM is disabled but all the registers retain their values except for the TDMx Receive Data Buffers Displacement Register TDMxRDBDR The TDMxTCR TEN bit see page 20 54 enables the transmit part of the TDM module When TDMxTCR TEN is clear the transmit TDM is disabled but all the registers retain their value...

Page 656: ...ER event registers by writing a value of 0xF to each of them 6 Set the TDMxRCR REN bit and or the TDMxTCR TEN bit 20 7 TDM Programming Model The handshake between the TDM module and the SC140 core occurs via a set of registers data structures in the memory and interrupts All TDM registers are mapped into the IPBus address space See Chapter 8 Memory Map for details on IPBus addressing There are fou...

Page 657: ...nel Parameter Register 0 255 TDMxTCPR 0 255 page 20 59 TDMx Receive Interrupt Enable Register TDMxRIER page 20 60 TDMx Transmit Interrupt Enable Register TDMxTIER page 20 61 TDMx Adaptation Sync Distance Register TDMxASDR page 20 62 TDMx Receive Data Buffers Displacement Register TDMxRDBDR page 20 62 TDMx Transmit Data Buffers Displacement Register TDMxTDBDR page 20 63 TDMx Receive Number of Buffe...

Page 658: ...are signals as follows TDM0 TDM1 TDM2 and TDM 3 do not share signals TDM0CTS 0 TDM1CTS 0 TDM2CTS 0 TDM3CTS 0 TDM0 and TDM1 share signals but TDM2 and TDM 3 do not share signals with the other TDM modules TDM0CTS 1 TDM1CTS 1 TDM2CTS 0 TDM3CTS 0 TDM0 TDM1 and TDM2 share signals but TDM3 does not share signals with the other TDM modules TDM0CTS 1 TDM1CTS 1 TDM2CTS 1 TDM3CTS 0 TDM0 TDM1 TDM2 TDM3 shar...

Page 659: ...001The receive and transmit are independent The TDM receives two data links and transmits two data link s valid only if CTS 1 0010Reserved 0011Reserved 0100The receive and transmit share the frame clock and frame sync The TDM receives one data link and transmits one data link 0101The receive and transmit share the frame sync and frame clock The TDM receives two data links and transmits two data li...

Page 660: ...Full duplex data links the data link is inout and is used for receive and transmit TDMxRDAT Unused signals TDMyTCLK TDMyTSYN TDMxRCLK TDMxRSYN and TDMxTDAT TDMx specifies the TDM number and any one of the shared TDM modules TDMy specifies the TDM number and any one of the shared TDM modules except TDM0 For example if TDM0 and TDM1 share signals the unused signals are TDM0RCLK TDM1RCLK TDM0RSYN TDM...

Page 661: ...ut Output Inout Input 1 0 0001 Reserved 2 0 0010 Reserved 3 0 0011 Reserved 4 0 0100 receive data RDATA_A not used not used transmit data TDATA_A frame sync frame clock The TDM does not share signals with others TDM modules Receive and transmit share sync and clock signals One active data link direction input Output Inout Input 5 0 0101 receive data RDATA_A receive data RDATA_B transmit data TDATA...

Page 662: ... Input 10 0 1110 Reserved 11 0 1111 data link DATA_A data link DATA_B data link DATA_D data link DATA_C frame sync frame clock The TDM does not share signals with other TDM modules Receive and transmit share the sync clock and data signals Four full duplex active data links direction Inout Inout Inout Inout Inout Input 12 1 0000 receive data RDATA_A not used not used transmit data TDATA_A receive ...

Page 663: ...rame sync not used frame clock not used The TDM shares the frame sync and frame clock with other TDM modules Receive and transmit shared sync and clock signals One active data link direction input Output Inout Input 17 1 0101 receive data RDATA_A receive data RDATA_B transmit data TDATA_B transmit data TDATA_A frame sync not used frame clock not used The TDM shares the frame sync and frame clock w...

Page 664: ...x active data links direction Inout Inout Inout Input 22 1 1110 Reserved 23 1 1111 data link DATA_A data link DATA_B data link DATA_D data link DATA_C frame sync not used frame clock not used The TDM shares the frame sync and frame clock with other TDM modules Receive and transmit share the sync clock and data signals Four full duplex active data links direction Inout Inout Inout Inout Inout Input...

Page 665: ...lse 1 Receive first threshold interrupt is level RSTL 17 0 Receive Second Threshold Level Determines whether the receive second threshold interrupt is pulse or level For details see Section 20 2 6 3 0 Receive second threshold interrupt is pulse 1 Receive second threshold interrupt is level 18 25 0 Reserved Write to zero for future compatibility RFSD 26 27 0 Receive Frame Sync Delay With the RDE an...

Page 666: ...bit of a received channel is stored as the most significant bit in the internal memory 1 The first bit of a received channel is stored as the least significant bit in the internal memory Table 20 11 Received Data Delay for Receive Frame Sync Frame Sync Delay Frame Sync Edge Data Edge Receive Clocks1 00 0 0 0 0 00 0 1 0 5 00 1 0 0 5 00 1 1 0 0 01 0 0 1 0 01 0 1 1 5 01 1 0 1 5 01 1 1 1 0 10 0 0 2 0 ...

Page 667: ...shold interrupt is pulse or level For details see Section 20 2 6 3 0 Transmit second threshold interrupt is pulse 1 Transmit second threshold interrupt is level TSO 18 0 Transmit Sync Output Determines whether the transmit sync is driven out by the TDM transmitter or it input to the TDM transmitter For details see Section 20 2 4 1 0 Transmit sync is input 1 Transmit sync is output TAO 19 0 Transmi...

Page 668: ...ether the transmit frame sync signal is sampled with the rising or falling edge of the receive clock For details see Section 20 2 4 2 0 The transmit frame sync signal is sampled with the rising edge of the transmit clock 1 The transmit frame sync signal is sampled with the falling edge of the transmit clock TRDO 31 0 Transmit Reversed Data Order For examples see Section 20 2 4 4 0 The most signifi...

Page 669: ...contain 2 256 channels at a granularity of two Notes 1 RNCF 8 15 number of channels that received on one active link number of active data links 1 the number of active data links is specified in the RTSAL field 2 If RCDBL field is clear then the minimum number of channels is limit The minimum receive number of channels is 128 receive channel size 2 For example if the channel size is 4 bits then th...

Page 670: ...Unified Buffer mode RUBM 1 the channel size must be 4 bits RCS x3 0000 Reserved 0001 The receiver channel size is 2 bits 0010 Reserved 0011 The receiver channel size is 4 bits 0100 0110 Reserved 0111 Receiver channel size is 8 bits 1000 1110 Reserved 1111 Receiver channel size is 16 bits RT1 30 0 Receive T1 frame Determines whether the receive frame is T1 frame or non T1 Note In T1 mode the channe...

Page 671: ...Reserved Write to zero for future compatibility TNCF 8 15 0 Transmit Number of Channels in a TDM Frame Specifies the total number of channels that are transmitted in the TDM modules One TDM frame contains 2 256 channels Notes 1 TNCF 8 15 number of channels that transmit on one active link number of active data links 1 the number of active data links is specified in the RTSAL field 2 If TCDBL field...

Page 672: ... 0x3 0000 Reserved 0001 The transmitter channel size is 2 bits 0010 Reserved 0011 The transmitter channel size is 4 bits 0100 Reserved 0101 Reserved 0110 Reserved 0111 The transmitter channel size is 8 bits 1000 1110 Reserved 1111 The transmitter channel size is 16 bits TT1 30 0 Transmit T1 Frame Determines whether the TDM transmitter drives a T1 frame or non T1 frame Note In T1 mode the channel s...

Page 673: ... 11 12 13 14 15 RDBS Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RDBS Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 20 18 TDMxRDBS Bit Descriptions Name Reset Description Settings 0 7 0 Reserved Write to zero for future compatibility RDBS 8 31 0 Receive Data Buffers Size Receive data buffers size equals the receive data buffer size in b...

Page 674: ...ection 20 2 6 1 Note The minimum buffer size is 16 bytes 0x00000F to 0xFFFFFF TDMxRGBA TDMx Receive Global Base Address Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RGBA Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 20 20 TDMxRGBA Bit Descriptions Name Reset Description 0 15 0 Reserved Write to z...

Page 675: ...s of the transmit data buffers It is added to channel data buffer address and to the current transmit displacement to generate the actual address TDMxACR TDMx Adaptation Control Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LTS AME Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 20 22 TDMxA...

Page 676: ...R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 20 23 TDMxRCR Bit Descriptions Name Reset Description Settings 0 30 0 Reserved Write to zero for future compatibility REN 31 0 Receive Enable Determines whether the receive TDM is enabled or disabled Note Setting this bit is the last step in initializing the receiver 0 Receiver is disabled 1 Receiver is enabled TDMxTCR TDMx Transmit Control Register ...

Page 677: ...er the transmit TDM is enabled or disabled Setting this bit is the last step in initializing the transmitter 0 Transmitter is disabled 1 Transmitter is enabled TDMxRDBFT TDMx Receive Data Buffers First Threshold Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDBFT Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RDBFT Type R W Reset 0 0 0 0 0 0 0 0 0 0 ...

Page 678: ...M Interface TDMxTDBFT TDMx Transmit Data Buffers First Threshold Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDBFT Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TDBFT Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 679: ...ed enable bit is also set an interrupt is generated This register can be updated any time even when the TDMx receiver is enabled For details see Section 20 2 6 3 Table 20 26 TDMxTDBFT Bit Descriptions Name Reset Description Settings 0 7 0 Reserved Write to zero for future compatibility TDBFT 8 31 0 Transmit Data Buffer First Threshold Determines the location of the first threshold in the transmit ...

Page 680: ...Rn RACT is cleared The read write access to TDMxRCPRn registers can done only to 32 bits write or read of byte or word is not valid The register reset value is unknown TDMxTDBST TDMx Transmit Data Buffers Second Threshold Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDBST Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TDBST Type R W Reset 0 0 0 0 0 0 0 ...

Page 681: ... valid when setting the corresponding TDMxTCR TEN bit see page 20 54 Table 20 29 TDMxRCPRn Bit Descriptions Name Reset Description Settings RACT 0 Receive Channel Active Set when the receive channel n is active 0 The channel is non active 1 The channel is active RCONV 1 2 Receive Channel Convert Determines the type of the incoming channel n Transparent A law or μ Law 00 Receive channel n is a tran...

Page 682: ...ould be clear For details see Section 20 2 6 2 0x000000 0xFFFFF0 TDMxRIER TDMx Receive Interrupt Enable Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RSEEE OLBEE RFTEE RSTEE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 20 31 TDMxRIER Bit Descriptions Name Reset Description Settings 0 27 ...

Page 683: ... TSEIE 28 0 Transmit Sync Error Event Enabled Enable assertion of the transmit error interrupt when the Transmit Sync Error TSE bit is set See page 20 66 0 Transmit sync error interrupt is disabled 1 Transmit sync error interrupt is enabled ULBEE 29 0 Underrun Local Buffer Event Enabled Enable assertion of an interrupt when the Underrun Local Buffer Event ULBE bit is set See page 20 66 0 Underrun ...

Page 684: ...o for future compatibility ASD 21 31 0 Adaptation Sync Distance Indicate the number of bits between the last two consecutive sync events If the TDMxACR LTS bit is set the ASD field indicates the number of transmit bits between the last two transmit sync events If the LTS bit is clear the value indicates the number of receive bits between the last two receive sync events 0x000 The number of bits be...

Page 685: ...ta in the data buffers The value is unified to all the transparent channels and is doubled for A μ law channels 0 to RDBS 7 Receive Data Buffer Size TDMxTDBDR TDMx Transmit Data Buffers Displacement Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDBD Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TDBD Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 686: ...ble 20 36 TDMxRNB Bit Descriptions Name Reset Description Settings 0 26 0 Reserved Write to zero for future compatibility RNB 27 31 0 Receive Number of Buffers Holds the number of buffers in the TDM receive local buffer For details see Section 20 2 5 Note The number of receive buffers equals RNB 1 0x001 buffer 0x012 buffers 0x034 buffers 0x078 buffers 0x0F 16 buffers 0x1F32 buffers The other value...

Page 687: ...ynchronization state change from SYNC to HUNT state because that a frame sync arrive early or it not recognized at the expected position During operation this bit indicates errors on the receive signals of the TDM module For details see Section 20 2 4 3 0 Normal operation No receive error has occurred 1 Receive sync error has occurred OLBE 29 0 Overrun Local Buffer Event Indicates whether an overr...

Page 688: ...hronization is lost the synchronization state change from SYNC to HUNT state because that a transmit frame sync arrive early or it not recognized at the expected position During operation this bit indicates errors on the transmit signals of the TDM module For details see Section 20 2 4 3 0 Normal operation No transmit sync error has occurred 1 A transmit sync error has occurred ULBE 29 0 Underrun ...

Page 689: ...4 15 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 AMS Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 20 40 TDMxASR Bit Descriptions Name Reset Description Settings 0 30 0 Reserved Write to zero for future compatibility AMS 31 0 Adaptation Machine Status Indicates the status of the adaptation machine If the bit is set new sync arrive and t...

Page 690: ...delayed because of the different clocks domains Note If the serial clock is not toggling this bit may not reflect updated values 0 The receiver machine is disabled 1 The receiver machine is enabled TDMxTSR TDMx Transmit Status Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TSSS TENS Type R Reset 0 ...

Page 691: ... Error Status and Control Register L_TESCR1 indicates whether an error has occurred on the local bus and L_TESCR1 TC indicates whether the TDM initiated the error access see page 12 112 The register is undefined at reset LGTDTEA Local Bus GTD Transfer Error Address Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDRESS Type R Reset undefined Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ADDRESS T...

Page 692: ...t reset LGTDTER GTD Transfer Error Requestor Number Register Bit 0 1 2 3 4 5 6 7 RQNUM Type R Reset Undefined Table 20 43 LGTDTER Bit Descriptions Name Reset Description Settings RQNUM 0 4 Requestor Number Indicates the number of the requestor accessing the bus when the bus error occurred 00000 Receive TDM0 00001 Transmit TDM0 00010 Receive TDM1 00011 Transmit TDM1 00100 Receive TDM2 00101 Transmi...

Page 693: ...n service UART interrupts The UART interrupt signal also connects to the GIC which drives INT_OUT so that an external host using interrupts on INT_OUT signal can service UART interrupts For details on UART interrupt signal connectivity to LICs and GIC refer to Chapter 17 Interrupt Processing When accepting an interrupt request an SC140 core or external host should read the UART status register SCI...

Page 694: ... the full duplex communication to guarantee that no more than one slave UART transmits to the URXD signal of the master at a given time Receiver wake up can obtain such a protocol see Section 21 2 7 Receiver Wake Up The UART UTXD signal can be configured with full CMOS drive or with open drain drive see Chapter 23 GPIO In both cases the external pull up resistor is needed to avoid floating input a...

Page 695: ... 3 Figure 21 3 Full Duplex Multiple UART System UART Rx Chip ID n1 UART Tx UTXD URXD UART Rx Chip ID n3 UART Tx UTXD URXD UART Rx Chip ID n2 UART Tx UTXD URXD Master Device URXD TxD Note The RC value on the MultiPoint TxD may limit system baud rate R MSC8113 ...

Page 696: ...gured with open drain drive see Chapter 23 GPIO and an external pull up resistor For details on single wire see Section 21 4 2 Single Wire Operation Figure 21 4 Single Wire Connection UART Rx Chip ID n1 UART Tx TxD UART Rx Chip ID n3 UART Tx TxD UART Rx Chip ID n2 UART Tx TxD Note The RC value on the MultiPoint UTXD might limit system baud rate R Master device RXD MSC8113 ...

Page 697: ...ta bits has a total of 11 bits including a start bit and a stop bit Figure 21 5 UART Data Formats Table 21 1 Examples of 8 Bit Data Format Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Note The address bit identifies the frame as an address character The address bit is bit 7 M 0 or bit 8 M 1 See Section 21 2 7 Receiver Wake Up Table 21 2 Example of 9 Bit Data ...

Page 698: ...ling for details on adjusting to the received baud rate at the receiver Table 21 3 lists some examples of achieving target baud rates with a system clock frequency of 100 MHz using the following formula 21 1 Transmitter The UART transmitter accommodates either 8 bit or 9 bit data characters The state of the M bit in the SCI Control Register SCICR determines the length of the data characters When 9...

Page 699: ...r shift register If the Transmit Interrupt Enable TIE bit in the SCICR is set the TDRE flag asserts a UART interrupt request The transmit interrupt service routine responds to this flag by writing another character to the transmitter buffer SCIDR while the shift register is still shifting out the first character If the TDRE flag is set and no new data or break character transferred to the shift re...

Page 700: ...format Reading TDRE bit in the SCISR and then writing new data to T 7 0 in the SCIDR clears the TDRE flag Otherwise the last data transmitted and then UTXD goes to idle condition that is a logic 1 high 3 Repeat step 2 for each subsequent transmission Note The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDR which occurs 9 16ths of a bit time after ...

Page 701: ...the last character of the first message to the SCIDR 2 Wait for the TDRE flag to go high indicating the transfer of the last frame to the transmit shift register 3 Insert a preamble by clearing and then setting the SCICR TE bit 4 Write the first character of the second message to the SCIDR Another way to separate messages with idle line is to wait until the TC flag is set after writing the last ch...

Page 702: ...usly written to the SCI data register Toggle the SCICR TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next character to the SCI data register See Figure 21 7 Queuing an Idle Character 21 1 4 Parity Bit Generation The UART can be configured to enable parity bit generation by the parity enable bit SCICR PE The parity type bit SCICR PT determines whet...

Page 703: ... that the baud rate generator is disabled when the baud rate is zero Writing to 5 MSB bits of SCIBR SBR 12 8 has no effect without also writing to 7 LSB of SCIBR SBR 7 0 b Configure GPIO27 for UART URXD see Chapter 23 GPIO Set PAR DD27 and PSOR SO27 PAR DD27 PSOR SO27 1 to connect the UART URXD signal to the external connection Clear PDIR DR27 PDIR DR27 0 c Write to the SCICR to configure data len...

Page 704: ...s a valid logic 1 and the majority of the next RT8 RT9 and RT10 samples returns a valid logic 0 To locate the start bit data sampling logic searches for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock logic begins to count to 16 Figure 21 8 UART Receiver Block Diagram All Ones M WAKE ILT PE PT RE H 8 7 6 5 4 3 2 1 0 L 11 Bit Receive Shift Regi...

Page 705: ...ample logic takes samples at RT8 RT9 and RT10 The data bit value is determined by the majority of the samples The noise flag NF is set if not all samples have the same logical value Table 21 5 summarizes the results of the data bit samples Figure 21 9 Receiver Data Sampling Table 21 4 Start Bit Verification RT3 RT5 and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011...

Page 706: ...aming error flag FE is set Table 21 6 summarizes the results of the stop bit samples In Figure 21 10 the start bit verification samples RT3 and RT5 determine that the first logic 0 detected is noise and not the beginning of a start bit The RT counter is reset and the start bit search resumes The noise flag is not set because the noise occurred before the start bit was found Table 21 6 Stop Bit Rec...

Page 707: ...ins again Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 of the next bit are within the bit time and data recovery is successful For this case the noise and framing error flags are not set Figure 21 11 Start Bit Search Example 2 Figure 21 12 Start Bit Search Example 3 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT11 RT10 RT9 RT14 RT13 RT12 RT2 RT1 RT16 RT15...

Page 708: ...uses the start bit not to be found and resets the RT counter The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge Depending on the timing of the start bit search and on the data the frame may be missed entirely or it may set the framing error flag Figure 21 13 Start Bit Search Example 4 Figure 21 14 Start Bit Search Example 5 Reset RT Cou...

Page 709: ...acter has no stop bit The FE flag is set at the same time that the RDRF flag is set FE inhibits further data reception until it is cleared Clear SCISR FE by reading SCISR and then reading the SCIDR Figure 21 15 Start Bit Search Example 6 Figure 21 16 Start Bit Search Example 7 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 Start Bit ...

Page 710: ...t set the RDRF flag again before another break character can set it again 3 The SCIDR is cleared 4 The overrun flag OR noise flag NF parity error flag PF or the receiver active flag RAF is set see the discussion in Section 21 6 21 2 6 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate Accumulated bit time misalignment can cause one of th...

Page 711: ...ting device is 9 bit 16 RT cycles 3 RT cycles 147 RT cycles The maximum percent difference between the receiver count and the transmitter count of a slow 8 bit data character with no errors is 154 147 154 100 4 54 For a 9 bit data character data sampling of the stop bit takes the receiver 10 bit 16 RT cycles 10 RT cycles 170 RT cycles With the misaligned character the receiver counts 170 RT cycles...

Page 712: ...176 RT cycles The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is 170 176 170 100 3 53 21 2 7 Receiver Wake Up The receiver can be put into a standby state so that the UART SCI can ignore transmissions intended only for other receivers in multiple receiver systems This is sometimes called putting the receiver to sleep Sett...

Page 713: ...E bit clear setting the SCICR RWU bit after URXD has been idle can cause the receiver to wake up immediately 21 2 7 2 Address Mark Wake Up WAKE 1 In address mark wake up a logic 1 in the MSB position of a frame clears the SCICR RWU bit and wakes up the SCI This frame is considered to contain an address character Hence all data characters should have their MSB at zero Each receiver s software evalu...

Page 714: ...re operation by setting the SCICR LOOPS bit and the receiver source bit SCICR RSRC Setting the SCICR LOOPS bit disables the path from URXD to the receiver Setting the SCICR RSRC bit connects the receiver input to the output of UTXD Both the transmitter and receiver must be enabled SCICR TE 1 and SCICR RE 1 The PODR bit which corresponds to UTXD at the PODR of GPIO see Chapter 23 GPIO configures UT...

Page 715: ... output connection Clearing the SCICR RSRC bit connects the transmitter output to the receiver input Both the transmitter and receiver must be enabled SCICR TE 1 and SCICR RE 1 for loop operation 21 4 4 Stop Mode The UART stops its clock to provide reduced power consumption when the UART_STC bit is set in the Stop Control Register see page 19 6 When the UART enters Stop mode the states of the UART...

Page 716: ...ace Refer to Section 8 5 IPBus Address Space for the UART Base address This section describes the UART SCI module registers which are listed as follows SCI Baud Rate Register SCIBR on page 21 25 SCI Control Register SCICR on page 21 25 SCI Status Register SCISR on page 21 28 SCI Data Register SCIDR on page 21 30 SCI Data Direction Register SCIDDR on page 21 31 Table 21 7 UART Interrupt Sources Sou...

Page 717: ...5 6 7 8 9 10 11 12 13 14 15 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SBR12SBR11SBR10 SBR9 SBR8 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Table 21 8 SCIBR Bit Descriptions Name Reset Description Settings 0 18 0 Reserved Write to zero for future compatibility SBR 12 0 19 31 4 SCI Baud Rate The baud...

Page 718: ... which condition wakes up the SCI a logic 1 address mark in the most significant bit position of a received data character or an idle condition on URXD 10 consecutive logic 1s if M 0 or 11 consecutive logic 1s if M 1 1 Address mark wake up 0 Idle line wake up ILT 21 0 Idle Line Type Bit Determines when the receiver starts counting logic 1s as idle character bits The counting begins either after th...

Page 719: ...eue an idle preamble 1 Transmitter enabled 0 Transmitter disabled RE 29 0 Receiver Enable Enables the SCI receiver 1 Receiver enabled 0 Receiver disabled RWU 30 0 Receiver Wake Up Enables the wake up function and inhibits further receiver interrupt requests Normally hardware wakes the receiver by automatically clearing RWU 1 RWU Standby state 0 Normal operation SBK 31 0 Send Break Toggling this bi...

Page 720: ...register TC 17 1 Transmit Complete Flag Set low when there is a transmission in progress or when a preamble or break character is loaded TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set UTXD becomes idle logic 1 This flag can generate an interrupt request refer to Section 21 5 Clear TC by reading TC and then writing to T 7 0 in th...

Page 721: ...rate an interrupt request refer to Section 21 5 Clear OR by reading OR then reading R 7 0 in the SCIDR 1 Overrun 0 No overrun NF 21 0 Noise Flag Set when the SCI detects noise on the receiver input NF is set during the same cycle as the RDRF flag but is not set for an overrun Clear NF by reading NF and then reading R 7 0 in the SCIDR 1 Noise 0 No noise FE 22 0 Framing Error Flag Set when a logic 0...

Page 722: ...received when the SCI is configured for 9 bit data format M 1 T8 17 0 Transmit Bit 8 The ninth data bit transmitted when the SCI is configured for 9 bit data format M 1 18 23 0 Reserved Write to zero for future compatibility 24 31 R 7 0 0 Received Bits 7 0 Received bits seven through zero for 9 bit or 8 bit data formats T 7 0 Transmit Bits 7 0 Transmit bits seven through zero for 9 bit or 8 bit fo...

Page 723: ...t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 21 13 SCIDDR Bit Descriptions Name Reset Description Settings 0 21 0 Reserved Write to zero for future compatibility DDRTX 22 0 Data Direction Bit TX Controls the TX signal direction in single wire mode refer to Section 21 4 2 1 If TE 1 TX is driven by the transmitter Otherwise if TE 0 UTXD is driven by logic 0 0 UTXD is not driven when the transmitter is di...

Page 724: ...MSC8113 Reference Manual Rev 0 21 32 Freescale Semiconductor UART ...

Page 725: ...imer For details see Chapter 4 System Interface Unit SIU Two timers in each timers module can drive two outputs see Figure 22 1 When the timers serve as frequency dividers the output can be configured in one of two ways Pulse The output frequency is out in compare register value Toggle The output frequency is out in compare register value 2 The timer modules are accessible and configured through t...

Page 726: ...e you reenable a timer set the compare value to a relatively high number and allow the counter to advance for at least three input clocks to flush the cache Then reenable the timer Table 22 1 Input Output Frequency Range Timer Combination Input Output Minimum Maximum Minimum Maximum One timer for the bus clock 0 Bus Clock 0 Bus Clock 2 One timer for the external clock 0 Bus Clock 0 External Clock ...

Page 727: ...M1RCLK TDM0TCLK TDM1TCLK Local Clock Local Clock 15 to 1 of Timers Timers Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 Timer B6 Timer B7 Timer B8 Timer B9 Timer B10 Timer B11 Timer B12 Timer B13 Timer B14 Timer B15 To SIU Multiplexers 16 15 to 1 of Multiplexers Module B Module A IPBus IPBus TIMER0 TIMER1 GPIO TIMER2 TIMER3 GPIO GPIO External Signals External Signals TIMER2 TIMER3 TDM2RCLK...

Page 728: ...CLK TDM1RCLK TDM0TCLK TDM1TCLK Local Bus Clock TIMERA8_OUT TIMERA9_OUT TIMERA10_OUT TIMERA11_OUT TIMERA12_OUT TIMERA13_OUT TIMERA14_OUT TIMERA15_OUT Comparator Configuration Register Compare Register TCFRAx Count Register TCNRAx 16 bit Counter 32 32 TCMPAx IPBus 16 16 15 to 1 Multiplexers Control Register TCRAx 32 Status Register TSRAx Event Register Interrupt to the PIC LIC SIU PAD GPIO 32 TERAx ...

Page 729: ...write a 0 to TCRAx to disable the timer the interrupt does not clear unless a 1 is written to the relevant bit in the TER When timer n reaches the compare TCMP value the TER CFn bit is set The CFn bit is cleared only when a 1 is written to the associated TER CFn bit The CFn bit is unaffected by Stop mode or timer restarts Note The TDM can use each of the TDM0RCLK TDM1RCLK TDM2RCLK and TDM3RCLK sig...

Page 730: ...he selected source is TIMER0 or TIMER1 configure it as an input its reset value If the timerA0 output connects to TIMER0 or the timer A4 output connects toTIMER1 configure the signal lines as outputs through the GPIO registers Timer General Configuration Register A TGCRA DIR0 or DIR4 bit 0 Input 1 Output page 22 9 Designate the signal as a pulse so that it is asserted for one clock cycle the input...

Page 731: ... register Timer Event Register A TERA CFx 1 page 22 18 An interrupt is generated Timer Interrupt Mask Register A TIERA IEx 1 page 22 11 Programmer Actions While Running Restart the counter at any time by writing a 1 to the enable bit in the TCRAx see the note on page 22 16 Timer Control Register A TCRA page 22 16 Read the value of the timer internal counter at any time Timer Count Register A TCNRA...

Page 732: ...gisters for individual timers Status registers Can be accessed at any time Note The global configuration and control registers configure all 16 timers in a module including the registers that define the I O This section describes the timer module registers which are listed as follows Timer General Configuration Register A TGCRA page 22 9 Timer General Configuration Register B TGCRB page 22 10 Time...

Page 733: ... is asserted for one clock 1 The signal is toggled DIR4 26 0 Signal Direction Defines the direction of TIMER1 0 TIMER1 is an input 1 TIMER1 is an output 27 0 Reserved Write to zero for future compatibility INTP 28 0 Interrupt Pulse Level Defines whether the Interrupts of Timers Module A are pulse or level If the timer is disabled the interrupt may remain asserted even if it in pulse mode until the...

Page 734: ...es the value of the associated COMPVAL field This bit is valid only when then TIMER3 is configured as output 0 The signal is asserted for one clock 1 The signal is toggled 26 27 0 Reserved Write to zero for future compatibility INTP 28 0 Interrupt Pulse Level Defines whether the interrupts of Timer Module B are pulse or level If the timer is disabled the interrupt may remain asserted even if it in...

Page 735: ...e Reset Description Settings 0 15 0 Reserved Write to zero for future compatibility IE 15 0 16 31 0 Timer A 15 0 Interrupt Enable When IEx and the corresponding TERA CFx are both set an interrupt is generated 0 Interrupt disabled 1 Interrupt enabled TIERB Timer Interrupt Enable Register B Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21...

Page 736: ...ty INSEL 25 28 6 Input Select Defines the source of the timer Ax clock 0000 TIMER0 0001 TIMER1 0010 TDM0RCLK 0011 TDM1RCLK 0100 TDM0TCLK 0101 TDM1TCLK 0110 Internal Local BUSES_CLOCK 0111 Reserved 1000 Timer A8 output 1001 Timer A9 output 1010 Timer A10 output 1011 Timer A11 output 1100 Timer A12 output 1101 Timer A13 output 1110 Timer A14 output 1111 Timer A15 output 29 0 Reserved Write to zero f...

Page 737: ...frequency divided by 4 In Cyclic mode the counter of Timer n counts from 0 until TCMPA COMPVAL wraps back to 0 and continues counting 0 One Shot mode 1 Cyclic mode Notes 1 IPOL in TCFRAx has no effect if the bus clock is used The counter counts on the positive edge 2 If an external clock is selected you configure the GPIO registers If an external input clock TDM0RCLK or TDM1RCLK is selected as an ...

Page 738: ...ut 29 0 Reserved Write to zero for future compatibility IPOL 30 0 Input Clock Polarity Defines the polarity of the input clock for Timer Bx IPOL has no effect if the bus clock is selected 0 Counter changes at the clock rising edge 1 Counter changes at the clock falling edge CYC 31 0 Cyclic One Shot Defines whether the Timer Bx operating mode is cyclic or one shot In Cyclic mode the timer counter c...

Page 739: ...Ax CYC 1 the counter is cleared and the counting continues In One Shot mode TCFRAx CYC 0 the counter is frozen and its output remains asserted until it is cleared TCMPB 0 15 Timer Compare Register B 0 15 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 COMPVAL Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 740: ...to the enable bit causes a one shot configured timer to count again regardless of whether its value is 0 or 1 0 The timer is disabled 1 The timer is enabled TCRB 0 15 Timer Control Register B 0 15 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 22 13 ...

Page 741: ...1 TES0 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 22 14 TSRA Bit Descriptions Name Reset Description Settings 0 15 0 Reserved Write to zero for future compatibility TES 15 0 16 31 0 Timer A 15 0 Enable Status Real status enable of Timer A 15 0 0 Timer status is disabled 1 Timer status is enabled TSRB Timer Status Register B Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0...

Page 742: ...Register A Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 22 16 TERA Bit Descriptions Name Reset Description Settings 0 15 0 Reserved Write to zero for future compatibility CF 15 0 16...

Page 743: ... Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CNTVAL Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 22 18 TCNRA 0 15 Bit Descriptions Name Reset Description 0 15 0 Reserved Write to zero for future compatibility CNTVAL 16 31 0 Counter Value Contains the counter value of Timer Ax from the Timers Module A Notes 1 When two timers are concatenated you c...

Page 744: ... 0 15 Bit Descriptions Name Reset Description 0 15 0 Reserved Write to zero for future compatibility CNTVAL 16 31 0 Counter Value Contains the counter value of Timer Bx from the Timers Module B Notes 1 When two timers are concatenated you can read only one counter each time Therefore the value that is read cannot be synchronized from the two counters as if there were a counter of 32 bits unless th...

Page 745: ...o voltage but goes to tri state when driving a high voltage GPIO ports do not have internal pull up resistors The dedicated MSC8113 peripheral functions multiplexed with the GPIO ports are grouped to maximize the usefulness of the ports in the greatest number of MSC8113 applications Note To understand the port assignment capability described in this chapter you must first understand the Ethernet T...

Page 746: ...T2 PDATx Read 0 1 0 1 PAR Open Drain OD 0 Reg From DED OUT1 PSOR 1 0 1 PDATx Write To from internal bus PAR Synchronizer Notes 1 Force Output may be asserted high by dedicated peripheral 2 direction control only when PODRx Reg PDIR Force Output1 Output Enable OE Data Out D OD D OE Pin x x 0 Z 0 d 1 d 1 0 1 0 1 1 1 Z PAR 1 and PSOR 1 selects this peripheral and PDIR 0 input It is used for bidirecti...

Page 747: ...Synchronizer Notes 1 Force Output may be asserted high by dedicated peripheral 2 direction control only when PODRx Reg PDIR Force Output1 Output Enable OE Data Out D OD D OE Pin x x 0 Z 0 d 1 d 1 0 1 0 1 1 1 Z PAR 1 and PSOR 1 selects this peripheral and PDIR 0 input It is used for bidirectional operation allowing the peripheral to dynamically control the port direction Force Tri state 2 2 Force T...

Page 748: ...d PSOR 5 ETHRXD3 GPIO or Dedicated functionality according to PAR and PSOR 6 ETHRXD2 GPIO or Dedicated functionality according to PAR and PSOR 7 ETHTXD3 GPIO or Dedicated functionality according to PAR and PSOR 8 ETHCOL GPIO or Dedicated functionality according to PAR and PSOR 9 ETHMDIO ETHMDIO ETHMDIO GPIO or Dedicated functionality according to PAR and PSOR 10 ETHRX_DV ETHCRS_DV NC leave unconne...

Page 749: ...PIO or Dedicated functionality according to PAR and PSOR 23 GPIO or Dedicated functionality according to PAR and PSOR 24 GPIO or Dedicated functionality according to PAR and PSOR 25 GPIO or Dedicated functionality according to PAR and PSOR 26 GPIO or Dedicated functionality according to PAR and PSOR 27 GPIO or Dedicated functionality according to PAR and PSOR 28 GPIO or Dedicated functionality acc...

Page 750: ... reaching the external port When a multiplexed GPIO port is not configured as a GPIO it has a dedicated functionality as described in Table 23 2 If an input to a peripheral is not supplied externally a default value is supplied to the internal peripheral as listed in the right most column Note Some functions can be output on two different ports You can freely configure such functions to be output ...

Page 751: ... PDIR for GPIO6 does not select the primary IRQ4 input the secondary IRQ4 input can be used if the combination of PAR PSOR and PDIR for GPIO0 selects it Figure 23 3 Using the Default Value to Select SIU TMCNT Clock Source Figure 23 4 Using the Default Value to Connect the IRQ4 Secondary to Primary Input Source MUX MUX From GPIO30 GND 0 1 0 1 TMCLK clock input TimerA6 Output TIMER2 clock input to T...

Page 752: ...y 1 TIMER1 Inout 0 3 IRQ1 1 TDM3TSYN Inout 0 4 IRQ2 1 TDM3TCLK 0 5 IRQ3 1 TDM3TDAT Inout 0 6 IRQ4 primary by GPIO0 TDM3RSYN Inout 0 7 IRQ5 primary by GPIO1 TDM3RCLK Inout 0 8 IRQ6 primary by GPIO2 TDM3RDAT Inout 0 9 IRQ7 1 TDM2TSYN Inout 0 10 IRQ8 1 TDM2TCLK 0 11 IRQ9 1 TDM2TDAT Inout 0 12 IRQ10 1 TDM2RSYN Inout 0 13 IRQ11 1 TDM2RCLK Inout 0 14 IRQ12 1 TDM2RDAT Inout 0 15 DREQ1 primary by GPIO27 T...

Page 753: ...describes these registers in detail Following is a list of the registers Pin Open Drain Register PODR page 23 10 Pin Data Register PDAT page 23 10 Pin Data Direction Registers PDIR page 23 11 Pin Assignment Register PAR page 23 11 Pin Special Options Registers PSOR page 23 12 21 0 TDM0TSYN Inout 0 22 TDM0TCLK 0 DRACK2 DONE2 Inout 1 23 IRQ13 1 TDM0TDAT Inout 0 24 IRQ14 1 TDM0RSYN Inout 0 25 IRQ15 1...

Page 754: ... still stored in the output register but it is prevented from reaching the actual pin When the PDAT register is read the state of the actual pin is read PODR Pin Open Drain Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OD31 OD30 OD29 OD28 OD27 OD26 OD25 OD24 OD23 OD22 OD21 OD20 OD19 OD18 OD17 OD16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ...

Page 755: ...t Description Settings DR 0 31 0 Direction Indicates whether a port is an input or an output 0 The corresponding port is an input 1 The corresponding port is an output PAR Pin Assignment Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DD31 DD30 DD29 DD28 DD27 DD26 DD25 DD24 DD23 DD22 DD21 DD20 DD19 DD18 DD17 DD16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 2...

Page 756: ...SOR PODR PDIR PAR PSOR Pin Special Options Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SO31 SO30 SO29 SO28 SO27 SO26 SO25 SO24 SO23 SO22 SO21 SO20 SO19 SO18 SO17 SO16 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SO15 SO14 SO13 SO12 SO11 SO10 SO9 SO8 SO7 SO6 SO5 SO4 SO3 SO2 SO1 SO0 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 23 6...

Page 757: ...le 24 1 Global symbols See Table 24 2 Global core registers See Table 24 3 The I2 C software module is invoked by calling the i2c_read_SequentialData routine using the falling routine d12 size of data bytes to read r3 address at the serial EEPROM r4 address at memory move l DATA_SIZE d12 move l SerMem_ADDR r3 move l IntMem_ADDR r4 bsr i2c_read_SequentialData The i2c_read_SequentialData routine set...

Page 758: ...ion 24 5 i2c_assert_start Routine on page 24 10 i2c_assert_stop Refer to Section 24 6 i2c_assert_stop Routine on page 24 11 i2c_WaitFor_StartCond_BusFreeTim e Refer to Section 24 7 i2c_WaitFor_StartCond_BusFreeTime Routine on page 24 12 i2c_write_SequentialData Refer to Section 24 8 i2c_write_SequentialData Routine on page 24 13 Figure 24 1 I2 C Multi Master Procedure Flow Table 24 2 Global Symbol...

Page 759: ...efer to Table 24 6 BASE_IP_B 0x01FBC000 IPBus memory PDAT_ADDR 0x01FBC208 GPIO PDAT register Table 24 3 Global Registers Register Value Description D4 Bit position D5 Transmit byte D6 Receive byte D7 Control byte bit 1 determines transmit or receive bit session D8 SCL_SDA_11 11 mask for SCL SDA GPIO31 GPIO30 D9 CHIPID value D10 Checksum calculation D12 Size of data to read D14 HIGH_PERIOD High Per...

Page 760: ...it or write of 1 bit 0 if write of 0 bit 14 tfr d15 d0 Wait HALF_LOW_PERIOD See Table 24 4 15 lperiod_data_2 16 deceq d0 17 bf lperiod_loop_2 18 or SCL_SDA_10 d1 l 19 move l d1 r0 20 move w d1 r9 Set SCL to 1 21 wait_scl_high Wait for SCL line to be 1 22 bsr i2c_sample_gpio GPIO at D2 23 and SCL_SDA_11 d2 d3 24 and SCL_SDA_10 d2 25 tsteq d2 26 bt wait_scl_high 27 bmchg SCL_SDA_01 d3 l 28 tfr d14 d...

Page 761: ... l Set D6 according to receive write bit value 40 deceq d0 41 bf hperiod_loop 42 bmtstc 1 d7 l 43 nop 44 iff rts Write session no need to check for arbitration lost 45 bmtstc 1 d6 l Check for arbitration lost in write session 46 move l r0 d1 47 iff move w SCL_SDA_10 d0 48 ift tfr d8 d0 49 cmpeq d0 d1 Set T bit for arbitration lost indication for higher routines 50 rts Table 24 4 HIGH_PERIOD and HA...

Page 762: ...clr d6 Receive byte 3 move w 80 d4 Bit position 4 byte_loop 5 bsr i2c_txrx_bit 6 ift rts Return if arbitration lost or start stop condition indication 7 asr d4 d4 8 asl d6 d6 Next bit read 9 tsteq d4 10 bf byte_loop 11 bmchg 1 d7 l 12 bsr i2c_txrx_bit 13 asr d6 d6 14 bmchg 1 d7 l 15 rts Figure 24 3 i2c_txrx_byte Routine ...

Page 763: ...Diagram Refer to Figure 24 4 Line Code Description 1 i2c_read_SequentialData 2 clr d7 3 moveu l 00ffffff d0 4 and d0 d12 5 bsr i2c_assert_start 6 clr d5 7 move l r3 d0 Serial memory address 8 extractu 3 10 d0 d5 Extract A0 A1 A2 9 asl d5 d5 10 bmset a0 d5 Write session 11 move l d5 r7 12 bsr i2c_txrx_byte Transmit slave address and A0 A1 A2 13 ift rts Return for any arbitration lost wrong ACK or s...

Page 764: ...bsr i2c_txrx_byte 28 ift rts Return for any arbitration lost Wrong ACK start stop condition indication 29 read_byte_loop 30 deceq d12 31 move w 1 d7 Read byte indication 32 ift bmset 2 d7 l Last byte indication 33 bsr i2c_txrx_byte 34 ift rts 35 move l 1 d7 36 bsr txrx_byte 37 ift rts Return for any arbitration lost Wrong ACK start stop condition indication 38 move b d6 r4 39 inca r4 40 inca r3 41...

Page 765: ...ws only two successive stabilized samples to be acknowledged Global Register Use D2 D9 Local Register Use D1 Line Code Description 1 i2c_sample_gpio 2 moveu w PDAT_ADDR d1 3 and d8 d1 4 loop_sample 5 moveu w PDAT_ADDR d2 6 and d8 d2 7 cmpeq d1 d2 8 tfr d2 d1 9 bf loop_sample 10 rts Figure 24 6 i2c_sample_gpio Routine Read GPIO to D1 Read GPIO to D2 D1 D2 PIN_VAL D2 Yes No D1 D2 ...

Page 766: ...nal Diagram Line Code Description 1 i2c_assert_start 2 move w SCL_SDA_10 r9 Set SDA to 0 3 move l HD_STA_TIME d0 Wait HD_STA_TIME Refer to Table 24 5 4 start_loop 5 bsr i2c_sample_gpio 6 bmtstc SCL_SDA_10 d2 l 7 bt start_rts Exit loop on SCL 0 8 deceq d0 9 bf start_loop 10 start_rts 11 rts Figure 24 7 i2c_assert_start Routine Table 24 5 HD_STA_TIME Timing Parameter Core_Clock at Core Bus 3 Core_Cl...

Page 767: ... 5 ift rts Return for any arbitration lost wrong ACK or start stop condition indication 6 move w d8 r9 Set SDA to 1 7 wait_sda_high Wait for SDA to be 1 8 bsr i2c_sample_gpio 9 bmtstc SCL_SDA_01 d2 l 10 bt wait_sda_high 11 move l BUF_TIME d0 12 stop_loop Wait BUF_TIME Refer to Table 24 6 13 bsr i2c_sample_gpio 14 bmtstc SCL_SDA_01 d2 l 15 bt stop_rts Exit loop on SDA 0 16 deceq d0 17 bf stop_loop ...

Page 768: ...Code Description 1 i2c_WaitFor_StartCond_BusFreeTi me 2 move l HALF_BUS_FREE_TIME d0 Wait HALF_BUS_FREE_TIME Refer to Table 24 6 3 busfree_loop bsr i2c_sample_gpio bmtsts SCL_SDA_11 d2 l bf i2c_WaitFor_StartCond_BusFreeTi me deceq d0 bf busfree_loop move l BUS_FREE_TIME d0 Wait BUS_FREE_TIME Refer to Table 24 7 3 wait_loop 4 bsr i2c_sample_gpio 5 bmtstc SCL_SDA_10 d2 l 6 bt i2c_WaitFor_StartCond_B...

Page 769: ...BUS_FREE_TIME 500 μs at 500 MHz 250000 290000 3150000 346200 Figure 24 10 I2 C Serial Memory Sequential Write Global Register Use D2 D7 R3 Local Register Use D0 Counting loop D5 Slave address Routine call i2c_assert_start i2c_assert_stop Signal Diagram Refer to Section 24 10 Line Code Description 1 i2c_write_SequentialData 2 clr d7 3 bsr i2c_assert_start 4 clr d5 Slave address 5 move l r3 d0 6 ext...

Page 770: ...actu 8 0 d0 d5 18 bsr i2c_txrx_byte 19 ift rts 20 move b r4 d5 21 bsr i2c_txrx_byte 22 ift rts 23 bsr i2c_assert_stop 24 inca r3 25 move l 100000 d0 Burn waiting time 26 write_loop 27 deceq d0 28 bf write_loop 29 deceq d12 30 bf i2c_write_SequentialData 31 rts Figure 24 11 i2c_write_SequentialData Routine Continued ...

Page 771: ...ines the requirements for a media independent interface MII that can support various physical implementations Other protocols developed modifications to this basic interface including the reduced media independent interface RMII and the serial media independent interface SMII The MSC8113 Ethernet controller supports MII RMII and SMII for the 10 100 Ethernet rate 25 1 Ethernet Basics The Ethernet p...

Page 772: ...er so that the MAC layer can be used with various implementations of the physical layer PCS Contains the functions to encode the data bits into code groups that can be transmitted over the physical medium Three PCS structures are defined for 100Base T one for 100Base X one for 100Base T4 and one for 100Base T2 see IEEE Std 802 3 Clauses 23 24 and 32 The PCS transmit function accepts data nibbles f...

Page 773: ...ctets transmit a pause time PT parameter pausetime 0x0000 for on and 0xFFFF for off In addition a third two octet field can be used for an extended pause control parameter PTE Because the use of these fields varies with the protocol the ability to examine them and report their content can significantly accelerate Ethernet frame processing Frame check sequence FCS Specifies the standard 32 bit cycl...

Page 774: ...of control variable unnumbered information transfer or supervisory and the rest of the 8 or 16 bit field defines the rest of the control parameters The LLC defines service access for protocols that conform to the open system interconnection OSI model for network protocols However many protocols including IP and IPX do not obey the rules for those layers and information on these protocols must be a...

Page 775: ...ment signals SMII Supports a serial interface with 6 Ethernet signals a receive data line a transmit data line a sync signal a clock and two data management signals In SMII MAC to MAC mode instead of driving the SYNC signal output the Ethernet controller uses the SYNC_IN signal input in this mode the ETHMDC and ETHMDIO signals are not used Section 25 5 discusses the signals used by each of these i...

Page 776: ...rogramming Model on page 25 49 Table 25 3 Selecting the Ethernet Controller Operating Modes Interface Mode Register Configurations Operating Mode MII mode MIIGSK_CFGR IFMODE 00 Operating speed is determined by the ETHTX_CLK and ETHRX_CLK signals which are driven by the transceiver RMII mode MIIGSK_CFGR IFMODE 01 For RMII and SMII modes 100 Mbps MIIGSK_CFGR FRCONT 0 10 Mbps MIIGSK_CFGR FRCONT 1 SMI...

Page 777: ...formation between a 10 100 PHY and MAC using two signals per port and generates the output SYNC signal to allow a MAC to PHY connection The SMII reference clock generates both transmit and receive clocks for the MII clocks You can configure the Ethernet controller for SMII MAC to PHY mode by writing 10 to MIIGSK_CFGR IFMODE and selecting the SYNC output signal by writing a 0 to MIIGSK_SMII_SYNCDIR...

Page 778: ...lts in a return to normal operation in MII mode Internal Loopback in RMII Domain Select RMII mode MIIGSK_CFGR IFMODE 01 Clear MACCFG1R MIILB Set RMIICFGR LBMODE Set MACCFG2R FDUP to select Full Duplex mode This configuration causes the RMII MAC transmit outputs to be looped back to the MAC receive inputs Clearing RMIICFGR LBMODE results in a return to normal operation in RMII mode Internal Loopbac...

Page 779: ...s pending on the Internal Peripheral Interface IPI line In Low Power Stop mode the Ethernet controller conversion operation is still enabled but the Ethernet controller registers cannot be accessed and no new interrupts are captured because the Ethernet controller output interrupt line is deasserted To exit from Low Power Stop mode clear SCR1 ETH_STC in the IP master block To clear all pending int...

Page 780: ...Standard Name HD40 D40 ETHRXD0 GPIO14 TDM2RDAT IRQ12 ETHRXD03 RXD0 RXD0 HD41 D41 ETHRXD1 GPIO12 TDM2RSYN IRQ10 ETHRXD1 ETHSYNC RXD1 RXD1 SYNC HD42 D42 ETHRXD2 NC GPIO6 TDM3RSYN IRQ4 ETHRXD2 NC RXD2 HD43 D43 ETHRXD3 NC GPIO5 TDM3TDAT IRQ3 ETHRXD3 NC RXD3 HD46 D46 ETHTXD0 GPIO0 CHIP_ID0 IRQ4 ETHTXD0 TXD0 TXD0 HD47 D47 ETHTXD1 GPIO1 TIMER0 CHIP_ID1 IRQ5 ETHTXD1 TXD1 TXD1 HD48 D48 ETHTXD2 NC GPIO3 TDM...

Page 781: ... clock to support 100 10 Mbps data rate operations ETHTX_CLK is a continuous transmit clock that provides the timing reference for the transfer of the ETHTX_EN ETHTXD and ETHTX_ER signals from the MAC to the PHY In MII mode the ETHTX_CLK is sourced by the PHY ETHTX_ER O MII Transmit Error 0 ETHCOL I MII Collision Detect ETHRX_DV I MII Receive Data Valid ETHRXD 3 0 I MII Receive Data Bits 3 0 ETHRX...

Page 782: ...ce can be configured as fast as 12 5 MHz if the PHY supports that speed ETHMDIO I O Management Data ETHMDIO is a bidirectional signal to input PHY supplied status during management read cycles and output control during management write cycles Table 25 8 Ethernet Controller Interface Signals In SMII Mode Signal Name Type Description Reset State ETHSYNC O Transmit Synchronization Control Signal Used...

Page 783: ... of ETHTX_CLK The number of driven preambles is configured by writing to MIICFG2R PREAL see page 25 85 After driving the specified number of preambles the Ethernet controller drives one byte of SFD 0b01011101 and then the data Four CRC bytes are appended according to the values in MACCFG2R PADCRC and MACCFG2R CRCEN see page 25 85 ETHTX_EN is deasserted at the rising edge of the ETHTX_CLK following...

Page 784: ...asserted while the value on the ETHRXD 3 0 is 1 or more bytes of preamble defined as 0b01010101 followed by 1 byte of start frame delimiter SFD defined as 0b01011101 After the Ethernet controller detects SFD ETHRX_DV must stay asserted until the Ethernet controller receives the last nibble of data Figure 25 6 shows the Ethernet controller MII transmit flow in Full Duplex Mode 25 6 2 RMII The MSC81...

Page 785: ... Ethernet controller drives one SFD byte 0b01011101 followed by the data Four CRC bytes are appended according to MACCFG2R PADCRC and MACCFG2R CRCEN ETHTX_EN is deasserted at the rising edge of ETHREF_CLK after the last two bits of the frame are transmitted In Half Duplex Mode asserting the carrier sense receive data valid CRS_DV input signal together with ETHTX_EN indicates a collision The behavi...

Page 786: ...art frame delimiter SFD 0b01011101 After the Ethernet controller detects SFD ETHRX_DV must stay asserted until the last nibble of data is received by the Ethernet controller end of frame is indicated by the deassertion of CRS_DV for two continuous ETHREF_CLK cycles Figure 25 7 and Figure 25 8 show the Ethernet controller RMII transmit flow in Full Duplex mode 25 6 3 SMII The MSC8113 Ethernet contr...

Page 787: ...me bit IFB value configured in the MIIGSK_TIFBR see page 25 99 When there is a valid frame transmission the Ethernet controller transmits one or more 10 bit segments as follows Preamble TX_ER TX_EN 1 0b01010101 SFD TX_ER TX_EN 1 0b01010111 Multiple segments each convey one byte of data in the form TX_ER TX_EN 1 data byte 4 CRC bytes can be appended according to MACCFG2R PADCRC CRCEN fields page 25...

Page 788: ... SMII SYNC Mode Full Duplex 100 Mbps Figure 25 13 Transmission Flow with No Errors End Of Frame in SMII SYNC Mode Full Duplex 100 Mbps ETHCLOCK ETHSYNC ETHTXD 1 TX_ER TX_EN 0 10 Bit valid segment PREAMBLE 1 0 SFD 1 0 Data 1 to 7 Bytes ETHCLOCK ETHSYNC ETHTXD 1 TX_ER TX_EN 0 10 Bit valid segment Data 1 0 CRC 0 0 10 Bit IFG segment IFG Data 4 Bytes ...

Page 789: ...d segment of data or an inter frame segment Bits 3 10 of the received segment are the data bits To interpret a received frame correctly the received 10 bit segment must have the following in order Preamble CRS RX_DV 1 0b01010101 SFD CRS RX_DV 1 0b01010111 Multiple 1 byte data segments CRS RX_DV 1 data byte Note In SMII SYNC In mode the Ethernet controller is synchronized on the receive SYNC signal...

Page 790: ...tart Of Valid Frame SMII Mode 100 Mbps Figure 25 16 Receive Flow with No Errors End Of Valid Frame SMII Mode 100 Mbps ETHCLOCK ETHSYNC ETHRXD 1 CRS RX_DV X 10 Bit valid segment Preamble 1 X SFD 1 X Data 1 or more ETHCLOCK ETHSYNC ETHRXD 1 CRS RX_DV X 10 Bit valid segment Data 1 X CRC 0 X 10 Bit IFG segment IFG Data 4 Bytes ...

Page 791: ... sends the 32 bit jam sequence The jam sequence inverts several bits of the CRC to guarantee an invalid CRC upon reception A collision signal is sent to the system to request retransmission of the start of the frame The Ethernet controller then stops the transfer for a time determined by the truncated binary exponential back off BEB algorithm The delay time is an integer number of slot times The n...

Page 792: ...ceived This also can be detrimental in that packets may now experience excessive collisions causing them to be dropped in the stations from which they originate To reduce the likelihood of lost packets and packets leaking through the back pressure mechanism BPNB must be set The Ethernet controller periodically drops the carrier ceases transmitting preamble to avoid excessive defer conditions in ot...

Page 793: ...s or conditionally accepts a frame Conditional acceptance occurs for a pattern match in which the accept decode PCNTRLn PMC is 10 and the continue search enable bit PCNTRLn CSE is also set You can program the Ethernet controller to continue searching past a successful pattern match by setting PCNTRLn CSE However once a sample pattern is not matched the frame is discarded immediately regardless of ...

Page 794: ...ing frames see Figure 25 17 If the reject all bit is set the frame is discarded Figure 25 17 Frame Acceptance Rejection Flowchart Yes No Pattern No Match Yes Yes Yes Yes Accept CSE 0 256 Bytes Received or Pattern Match Reject No No No Receive Frame Reject All Yes No No and Perform any Action Determined by Match es Yes EOF Valid Pattern Match Pattern Match Reject Yes Address No Recognition Match wi...

Page 795: ...ysical address that you program in the station address registers MACSTNADDR1 and MACSTNADDR2 If the destination address does not match the station address the controller performs address recognition on multiple individual addresses using the IADDRn hash table You must write zeros to the hash to avoid a hash match and ones to the station address to avoid an individual address match or you can turn ...

Page 796: ...om Pattern I G Address Station Address Match Individual Group Broadcast Address Broadcast Reject Yes No Hash Search Use Group Table Hash Search Use Individual Table Yes Hash Match Yes Promiscuous Discard Frame Yes No No No No Yes Match Flowchart Receive Frame and Perform Any Action Determined by Match Back to Pattern Matching Flowchart ...

Page 797: ...rom reaching memory Software must further filter those that reach memory to determine if they contain the correct addresses In addition if pattern matching is enabled the Ethernet controller can reduce the burden on the software and further accelerate the reception by performing additional filtering Better performance is achieved when the group and individual hash tables are used in combination Fo...

Page 798: ...rformed on the transmitting side Pattern matching can be used to define up to eight more station addresses Pattern match reject can also be performed in 8 byte mode Use the Default Attribute Register to change the default filing queue These features can reduce the memory space smaller BD rings required and increase performance less DMA read write required for the 8 byte BD as compared to the 32 by...

Page 799: ... BDs must reside sequentially in memory The Ethernet controller increments the current BD location appropriately to the next BD location to be processed A wrap bit in the last BD informs the Ethernet controller to loop back to the beginning of the BD chain Figure 25 19 Example Memory Structure for an 8 Byte BD Figure 25 20 Buffer Descriptor Ring Status and Control Data Length Buffer Pointer Status...

Page 800: ...ern size Noncontiguous concatenated patterns each bit of a pattern can be individually masked Multi pattern hit detection Pattern matching enables you to process receive frames with a set of tools to assist network applications Features such as filing of frames in queues based on a pattern hit can accelerate post processing of data You can further enhance address recognition filtering by applying ...

Page 801: ...h of the four receive queues stores the frame Figure 25 22 shows these registers their relationship to each other and how the contents of the registers are mapped to a BD Pattern matching table entries can be used in several ways Concatenate two entries by setting the appropriate PCNTRLn CP to set up an exact address match A maximum of eight additional exact addresses can be set up if all entries ...

Page 802: ...tch reject all other controls and attributes are ignored and the frame is discarded regardless of the state of the CSE bit Pattern matching continues if a pattern match hit occurs in which the CSE bit is set and the controls and attributes corresponding to this entry are used if no further match is found Pattern matching stops if there is a pattern match with the CSE bit cleared and the attributes...

Page 803: ...n match hit occurs but a destination address is recognized the frame uses the information in the default attributes register DATTR to determine how to process the frame When RCTRL PMEN is set RCTRL RA is cleared and the PCNTRLn PMC decodes to Entry Disabled for all entries destination address recognition determines whether the frame is rejected or accepted filed in default attribute register Figur...

Page 804: ...s RCTRL PROM broadcast BC reject RCTRL BC_REJ and pause frame received Figure 25 22 Example of Pattern Configurations P0 P1 P2 P3 P4 P5 P6 P7 P9 P10 P11 P12 P13 P14 P15 P8 P 0 1 P 2 3 P 4 5 P 6 7 P 8 9 P 10 11 P 12 13 P 14 15 P 0 3 P 4 7 P 8 11 P 12 15 P 0 7 P 8 15 P 0 15 PCNTRL0 CP 1 PCNTRL1 CP 1 PCNTRL2 CP 1 PCNTRL3 CP 0 PCNTRL4 CP 1 PCNTRO5 CP 1 PCNTRL6 CP 1 PCNTRO7 CP 0 PCNTRL8 CP 1 PCNTRL9 CP...

Page 805: ... up for filing PATTRBn PMF is set The QC field of the pattern attribute register for p2 PATTRB2 QC specifies the queue to store the frame However under the same conditions if pattern p2 is not set up for filing PATTRBn PMF is cleared the queue selected in the default attribute register is used Figure 25 23 depicts an example of how to prepare multiple patterns to examine different fields within a ...

Page 806: ...24 shows how a TxBD can be used to process the transmit frame and perform insertion with replacement BD0 and insertion with expansion BD1 To insert data into a transmit frame you must set up the following fields of the 32 byte BD for that frame Status and control Data length and Tx data buffer pointer Insert buffer pointer which points to the address of the buffer to be inserted Insert index which...

Page 807: ...sertion by Replacement and Insertion by Expansion Status and Control Data Length TX_BUF_PTR 32 b Insert Index TX_INS_BUF_PTR 32 b Insert Length Status and Control Data Length TX_BUF_PTR 32 b Insert Index TX_INS_BUF_PTR 32 b Insert Length BD0 BD1 BD0 Insertion Data BD1 Insertion Data Software must ensure that the data length of the frame s Type Length field is correct The inserted data replaces dat...

Page 808: ...ting flow control frames poll the Used Entry Count Register in the FIFO If the value is equal to or greater than the value in the Alarm Register use the following recommended steps to transmit flow control frames Table 25 11 Flow Control Frame Structure Size Octets Description Value Comment 7 Preamble 1 SFD Start frame delimiter 6 Destination address 01 80C2 00 00 01 Multicast address reserved for...

Page 809: ...ils on IEVENT see page 25 53 Receive inter frame bit status interrupt RIFGSI Only In SMII Mode For details on Receive Inter Frame Gap Data Event see page 25 86 The maskable interrupts are routed to the global interrupt controllers GIC or periodic interrupt controller PIC of each SC140 core see Table 25 12 The PIC can receive any of the five interrupt lines one for each event while the GIC receives...

Page 810: ...refetches BDs the BD table must be big enough that there is always another empty BD to prefetch See Table 25 14 Clear any set halt bits in TSTAT and RSTAT registers or DMACTRL GTS and DMACTRL GRS and continue normal execution Table 25 13 Non Error Transmit Interrupts Interrupt Description TXB Transmit buffer A TxBD that is not the last one in the frame was updated TXF Transmit frame A frame was tr...

Page 811: ...eception Errors Type Of Error Ethernet Controller Operation Overrun error The Ethernet controller maintains an internal FIFO buffer for receiving data If a receiver FIFO buffer overrun occurs the controller sets RxBD OV sets RxBD L closes the buffer and sets IEVENT RXFn The receiver then enters hunt mode seeking start of a new frame Note In some situations the overrun condition may be due to heavy...

Page 812: ... Ethernet controller to the PHY MAC in MII RMII and SMII modes In RMII and SMII mode some part of the Ethernet controller signals are used Table 25 4 indicates which signals are reserved in these modes and which signals should not be connected Note The MAC to MAC connection is not defined in the IEEE Std 802 3 Care must be taken to ensure that the receive side has enough set up and hold time CRC e...

Page 813: ...t TX_ER TX_EN TXD 3 0 TX_CLK COL RXD 3 0 RX_ER RX_CLK RX_DV CRS MDC MDIO Medium Ethernet MII PHY ETHTX_ER ETHTX_EN ETHTXD 3 0 ETHTX_CLK ETHCOL ETHRXD 3 0 ETHRX_ER ETHRX_CLK ETHRX_DV ETHCRS MSC8113 Ethernet signals ETHMDC ETHMDIO TX_ER TX_EN RXD 3 0 RX_CLK COL TXD 3 0 RX_ER TX_CLK RX_DV CRS Ethernet MII MAC ETHTX_ER ETHTX_EN ETHTXD 3 0 ETHTX_CLK ETHCOL ETHRXD 3 0 ETHRX_ER ETHRX_CLK ETHRX_DV ETHCRS ...

Page 814: ...to MAC Connection In RMII Mode TX_EN TXD 1 0 REF_CLK RXD 1 0 RX_ER CRS_DV MDC MDIO Medium Ethernet RMII PHY ETHTX_EN ETHTXD 1 0 ETHREF_CLK ETHRXD 1 0 ETHRX_ER CRS_DV MSC8113 Ethernet signals ETHMDC ETHMDIO 50 MHz Clock TX_EN TXD 1 0 REF_CLK RXD 1 0 RX_ER CRS_DV Ethernet RMII MAC ETHTX_EN ETHTXD 1 0 ETHREF_CLK ETHRXD 1 0 ETHRX_ER CRS_DV MSC8113 Ethernet signals 50 MHz Clock ...

Page 815: ...Y Connection in SMII Mode Figure 25 30 Ethernet Controller to MAC Connection in SMII Mode TXD CLOCK RXD MDC MDIO Medium Ethernet SMII PHY ETHTXD SYNC ETHCLOCK ETHRXD MSC8113 Ethernet signals ETHMDC ETHMDIO 125 MHz Clock SYNC RXD CLOCK TXD Ethernet SMII MAC ETHTXD ETHSYNC_IN ETHCLOCK ETHRXD MSC8113 Ethernet signals 125 MHz Clock SYNC ...

Page 816: ...gisters Other registers can also be initialized but they are optional and must be determined on the basis of system requirements Table 25 17 describes the minimum steps for register initialization Table 25 17 Minimum Register Initialization Initialization Step Register s Page 1 Set the MIIGSK_ENR EN bit MIIGSK Enable Register MIIGSK_ENR page 25 98 2 Wait until the MIIGSK_ENR R is set MIIGSK Enable...

Page 817: ... perform either method one or 8 Select RMII or SMII speed 10Mbps 100Mbps MIIGSK Configuration Register MIIGSK_CFGR page 25 96 9 Clear interrupts to prepare for interrupt events Interrupt Event Register IEVENT page 25 53 10 Initialize the interrupt mask to prepare for interrupt events Interrupt Mask Register IMASK page 25 55 11 Set the DMACTRL 30 bit DMA Control Register DMACTRL page 25 59 12 Initi...

Page 818: ... the DMACTRL GRS GTS bits Wait for both the IEVENT GRSC GTSC bits to be set clear them by writing 1 and then set the Ethernet controller internal reset bit MIIGSK_GPR IR The internal reset must be valid for at least 10 core cycles Then clear the MIIGSK_GPR IR bit and reconfigure the Ethernet controller During the MAC configuration the TBASE register and the RBASEn registers must be written with th...

Page 819: ...he following steps 1 Write 0xFF to the MIIGSK_IMASK register to enable all events 2 Wait for the interrupt 3 The interrupt handler should disable all events by writing 0x00 to the MIIGSK_IMASK register and then write 0xFF to the MIIGSK_IEVENT register to clear all events 4 After initialization you can configure the MIIGSK_IMASK and MIIGSK_ERIFBR register as required 25 17 Ethernet Controller Progr...

Page 820: ... Register FTXSR page 25 68 FIFO Transmit Starve Shutoff Register FTXSSR page 25 68 Transmit Control and Status Registers Transmit Control Register TCTRL page 25 69 Transmit Status Register TSTAT page 25 70 TxBD Data Length Register TBDLEN page 25 71 Current TxBD Pointer CTBPTR page 25 71 TxBD Pointer TBPTR page 25 72 Transmit Descriptor Base Address TBASE page 25 72 Out of Sequence TxBD Register O...

Page 821: ...ected Receive Inter Frame Bits Register MIIGSK_ERIFBR page 25 102 MIIGSK SMII Interrupt Event Register MIIGSK_IEVENT page 25 102 MIIGSK SMII Interrupt Mask Register MIIGSK_IMASK page 25 104 RMON Counters MIB Transmit and Receive 64 Byte Frame Counter TR64 page 25 105 Transmit and Receive 65 to 127 Byte Frame Counter TR127 page 25 106 Transmit and Receive 128 to 255 Byte Frame Counter TR255 page 25...

Page 822: ...25 123 Transmit FCS Error Counter TFCS page 25 124 Transmit Control Frame Counter TXCF page 25 124 Transmit Oversize Frame Counter TOVR page 25 125 Transmit Undersize Frame Counter TUND page 25 125 Transmit Fragment Counter TFRG page 25 126 Carry Register One CAR1 page 25 126 Carry Register Two CAR2 page 25 127 Carry Register One Mask CAM1 page 25 129 Carry Register Two Mask CAM2 page 25 130 Hash ...

Page 823: ... CRL XFUN Type R W R R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RXB0 RXB1 RXB2 RXB3 GRSC RXF0 RXF1 RXF2 RXF3 Type R W R R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 19 IEVENT Bit Descriptions Name Reset Description Settings 0 0 Reserved Write to zero for future compatibility RXC 1 0 Receive Control Interrupt A control frame was received ...

Page 824: ...d during an attempt to insert data during transmission of a frame 0 No insertion error 1 Insertion error LC 13 0 Late Collision A collision occurred beyond the collision window slot time in Half Duplex mode The frame is truncated with a bad CRC and the remainder of the frame is discarded 0 No collision 1 Collision occurred beyond collision window CRL 14 0 Collision Retry Limit The number of succes...

Page 825: ... last RxBD in that frame was updated This occurs only if the Interrupt I bit in the BD status word is set 0 No receive frame interrupt 1 Receive frame interrupt RXF2 26 0 Receive Frame Interrupt 2 A frame was received in queue 2 and the last RxBD in that frame was updated This occurs only if the Interrupt I bit in the BD status word is set 0 No receive frame interrupt 1 Receive frame interrupt RXF...

Page 826: ... Enable 0 IEI disabled 1 IEI enabled LCEN 13 0 Late Collision Enable 0 LC disabled 1 LC enabled CRLEN 14 0 Collision Retry Limit Enable 0 CRL disabled 1 CRL enabled XFUNEN 15 0 Transmit FIFO Underrun Enable 0 TFU disabled 1 TFU enabled RXBEN0 16 0 Receive Buffer Queue 0 Interrupt Enable 0 RBQ0I disabled 1 RBQ0I enabled RXBEN1 17 0 Receive Buffer Queue 1 Interrupt Enable 0 RBQ10I disabled 1 RBQ1I e...

Page 827: ...ost read or whether you must explicitly write the value of zero This is a steady state signal and must be set before the Ethernet controller is enabled It must not be changed without proper care The addressed counter values are input to the MSTAT module 0 User must write a value of zero to the addressed counter after a host read 1 A value of zero is automatically written to the addressed counter a...

Page 828: ...28 29 30 31 MINFLR Type R Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Table 25 22 MINFLR Field Descriptions Bit Reset Description 0 24 0 Reserved Write to zero for future compatibility MINFLR 25 31 1000000 Minimum Receive Frame Length typically 64 decimal Determines the minimum size of acceptable receive frames If the Ethernet controller receives an incoming frame shorter than MINFLR it discards that fr...

Page 829: ...e_quanta a speed independent constant of 512 bit times unlike slot time The most significant octet is transmitted first with a two pause_quanta resolution Note Because the pause period has a resolution of two pause_quanta the value programmed in this field is rounded up to the nearest even number before it is used as follows MAC Parameter Value Pause Period 0 None 1 or 2 2 pause_quanta 3 or 4 4 pa...

Page 830: ...thernet controller stops receiving frames after processing the current frame 1 Ethernet controller resumes receiving frames GTS 28 0 Graceful Transmit Stop Causes the Ethernet controller to stop transmitting frames after transmitting the current frame and the IEVENT GTSC is set to generate an interrupt If frame transmission is not currently underway the GTSC interrupt is generated immediately Once...

Page 831: ...to this bit after any reset or configuration DOOS 7 0 Disable Out of Sequence Buffer Descriptor 0 Out of Sequence buffer descriptor polling is enabled 1 Out of Sequence buffer descriptor polling is disabled 8 0 Reserved Always write a 0 to this bit after any reset or configuration 9 0 Reserved Always write a 1 to this bit after any reset or reconfiguration 10 11 0 Reserved Always write a 0 to this...

Page 832: ... and data buffers should be 64 byte aligned Also one insertion per frame should be used You can deviate from these recommended values to increase performance or use less memory but unless the default values of some of the FIFO registers are adjusted the probability of an underrun may also increase The FTXTHR default is 256 entries or 1 KB indicates the amount of data required to be in the FIFO bef...

Page 833: ...lts to empty 0 Not empty 1 Empty 31 Reserved FRXCTRLR FIFO Receive Control Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 Type R R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 27 FRXCTRLR Bit Descriptions Bit Reset Description 0 29 0 Reserved Write to zero for future compatibility 30 0 Alwa...

Page 834: ...e Table 25 28 FRXALAR Field Descriptions Bit Reset Description 0 22 Reserved Write to zero for future compatibility FRXALAR 23 31 100000000 FIFO Receive Alarm Indicates the value to trigger the receive alarm function The alarm triggers when the FIFO Receive Used Entry Count is equal to or greater than the FIFO Rx Alarm The alarm turns off only if the FIFO Receive Used Entry Count falls to less tha...

Page 835: ...ceive Panic Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FRXPA Type R R W Reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Table 25 30 FRXPAR Field Descriptions Bit Reset Description 0 22 0 Reserved Write to zero for future compatibility FRXPA 23 31 110000000 FIFO Receive Panic The value to trigger the rece...

Page 836: ...he FIFO Rx Used Entry Count falls to less than or equal to the value in FRXPSR FTXSTATR FIFO Transmit Status Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FULL EMPTY Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Table 25 33 FTXSTATR Field Descriptions Bit Reset Description Settings 0 28 0 Reserved ...

Page 837: ...ype R R W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Table 25 34 FTXTHR Bit Descriptions Bit Reset Description 0 22 0 Reserved Write to zero for future compatibility FTT 23 31 100000000 FIFO Transmit Threshold Specifies the number of entries in the transmit FIFO that trigger the unloading of frame data into the MAC FTXSPR FIFO Transmit Space Available Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ...

Page 838: ... Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FTXS Type R R W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Table 25 36 FTXSR Bit Descriptions Bit Reset Description 0 22 0 Reserved Write to zero for future compatibility FTXS 23 31 100000000 FIFO Transmit Starve Indicate the value to trigger the transmit starve function which triggers when the number of valid en...

Page 839: ...reater than or equal to the value in FTXSSR TCTRL Transmit Control Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 THDF RFCP TFCP Type R R W R R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 38 TCTRL Bit Descriptions Bit Reset Description Settings 0 19 0 Reserved Write to zero for future compat...

Page 840: ...e the MAC may still transmit a MAC control pause frame 0 No pause 1 Stop transmitting data frames for the specified duration 29 31 0 Reserved Write to zero for future compatibility TSTAT Transmit Status Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 THLT Type R W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 841: ...0 TxBD Data Length Specifies the length of the transmit or insert buffer The DMA module writes to TBDLEN internally The transmit channel remains active until TBDLEN contains a value of 0 CTBPTR Current TxBD Pointer Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CTBPTR Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CTBPTR Type R W R Reset 0 0 0 0 0 0 0...

Page 842: ... is read from memory In 32 byte mode ECNTRL DBDS is set this field must be 32 byte aligned This means that bits 27 and 28 are reserved in 32 byte mode 29 31 0 Reserved Write to zero for future compatibility TBASE Transmit Descriptor Base Address Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TBASE Type R W Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TBASE T...

Page 843: ...s this bit after the buffer is transmitted or after an error condition is encountered When this bit is set you cannot write to any fields of this BD This bit is written by the Ethernet controller and the user 0 The data buffer associated with this BD is not ready for transmission 1 The data buffer that the user has prepared for transmission was not transmitted or is currently being transmitted PAD...

Page 844: ...on and updates the bit value 0 Transmission before maximum retry limit is hit 1 The transmitter failed maximum retry limit 1 attempts to send a message successfully due to repeated collisions RC 10 13 0 Retry Count Indicates whether a retry was necessary to send the frame as well as the number of retries needed For example if this field holds a value of 15 then 15 or more retries were needed The E...

Page 845: ...DP Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OSTBDP Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 45 OSTBDP Bit Descriptions Bit Reset Description OSTDBP 0 31 0 Out of sequence Tx Data Buffer Pointer Contains the address of the associated data buffer There are no alignment requirements for this address OS32TBDP Out of Sequence 32 B...

Page 846: ...nment requirements The buffer resides in memory external to the Ethernet controller The inserted data is placed inside the transmit frame as defined by the insert index and insert length fields You can choose insertion by replacement or insertion by expansion see Figure 25 24 on page 25 37 You are responsible for ensuring that the value in the frame s type length field is correct The combination o...

Page 847: ...0 If TxBD IT 01 or 10 no insertion error 1 An error occurred during an attempt to insert data IT 30 31 0 Insert Type Defines the type of insertion to be perform 00 No insertion 01 Replacement 10 Expansion 11 Reserved OS32IIL Out of Sequence 32 Byte TxBD Insert Index Length Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OS32INX Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 2...

Page 848: ...bits of the CRC remainder to map the DA to the hash table entry 21 24 0 Reserved Write to zero for future compatibility PMEN 25 0 Pattern Match Enabled Enables disables pattern matching 0 Pattern match is disabled 1 Pattern match is enabled 26 0 Reserved Write to zero for future compatibility BCREJ 27 0 Broadcast Frame Reject Rejects frames with a destination address DA FFFF_FFFF_FFFF unless RCTRL...

Page 849: ... None of the Ethernet RXDB queues are halted 1 Ethernet controller receive activity in at least one RXBD queue is halted 1 7 0 Reserved Write to zero for future compatibility Q0HLT 8 0 RxBD Queue 0 Halted Halts all receive activity in RxBD queue 0 The current frame and all other frames directed to a halted queue are discarded A write with a value of 1 re enables the queue for receiving 0 RxBD queu...

Page 850: ... zero for future compatibility RBDLEN RxBD Data Length Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RBDLEN Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 52 RBDLEN Bit Descriptions Bit Reset Description 0 15 0 Reserved Write to zero for future compatibility RBDLEN 16 31 0 RxBD Data Lengt...

Page 851: ... the next buffer You write to MRBLR1 with a multiple of 64 for all modes The Ethernet controller can write fewer bytes to the buffer than the value set in MRBLR1 if a condition such as an error or end of frame occurs but it never exceeds the MRBLR1 value Therefore user supplied buffers must be at least as large as MRBLR1 Note that you can assign transmit buffers varying lengths by programming TxBD...

Page 852: ...Note that you can assign transmit buffers varying lengths by programming TxBD DL as needed They are not affected by the value in a MRBLRn MRBLRn is not to be changed dynamically while the Ethernet controller is operating Change MRBLRn only when the Ethernet controller receive function is disabled 10 15 0 To ensure that MRBLR2 and MRBLR3 are multiples of 64 these bits are reserved and should be cle...

Page 853: ...ytes depending on ECNTRL DBDS each time a descriptor is read from memory In 32 byte mode ECNTRL DBDS is set this field must be 32 byte aligned This means that bits 27 and 28 are reserved in 32 byte mode 29 31 0 Reserved Write to zero for future compatibility RBASEn Receive Descriptor Base Address 0 3 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RBASEn Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bi...

Page 854: ...7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MIILB RXFL TXFL SYRXEN RXEN SYTXEN TXEN Type R R W R R W R R W R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 58 MACCFG1R Field Descriptions Bit Reset Description Settings SRESET 0 0 Soft Reset Puts all MAC modules into reset For details on setting this bit see Section 25 16 Initialization and Reset 0 Normal operation 1 Soft reset 2 11 0 Reserved W...

Page 855: ...e receive stream 0 Frame reception is not enabled 1 Frame reception is enabled RXEN 29 0 Receive Enable Allows the MAC to receive frames from the PHY Clearing this bit prevents the reception of frames 0 MAC cannot receive frames 1 MAC can receive frames SYTXEN 30 0 Synchronized TX Enable Transmit Enable synchronized to the transmit stream 0 Frame transmission is not enabled 1 Frame transmission is...

Page 856: ...the actual data field length 0 No length field checking 1 The MAC checks the frame length field 28 0 Reserved Write to zero for future compatibility PADCRC 29 0 PAD CRC Indicates padding and CRC status 0 No padding and no CRC 1 The MAC pads all transmitted short frames and appends a CRC to every frame CRCEN 30 0 CRC Enable Enables MAC CRC checking Note If the configuration bit PAD CRC ENABLE or th...

Page 857: ...ne 8 0 Reserved Write to zero for future compatibility NBBIPG2 9 15 1100000 Non Back to Back Inter Packet Gap Part 2 This programmable field represents the non back to back inter packet gap in bits Its default is 0x60 96d which represents the minimum IPG of 96 bits MIFGE 16 23 01010000 Minimum IFG Enforcement This programmable field represents the minimum number of bits of the IFG to enforce betwe...

Page 858: ...ck pressure operation 0 Tx MAC follows the binary exponential back off rule 1 No back off during a back pressure operation NB 14 0 No Back off Configures the Tx MAC to immediately re transmit following a collision 0 Tx MAC follows the binary exponential back off rule 1 No back off ED 15 1 Excess Defer Configures the Tx MAC to allow the transmission of a packet that is excessively deferred 0 Abort ...

Page 859: ...0 0 0 0 Table 25 62 MAXFRM Descriptions Bit Reset Description 0 15 0 Reserved Write to zero for future compatibility MF 16 31 0000011000000000 Maximum Frame By default this field is set to 0x0600 It sets the maximum frame size in both the transmit and receive directions IFSTATR Interface Status Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 1...

Page 860: ...NADDR2 will return a value of 0x34120000 Note the I G and U L bits of the frame s DA field is located at the LSBs of the 1st octet stored in MACSTNADDR2 where the I G bit is bit 15 and the U L bit is bit 14 MACSTADDR1R MAC Station Address Part 1 Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SA1 SA2 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30...

Page 861: ...0x12345678abcd MACSTNADDR1 is set to 0xcdab7856 and MACSTNADDR2 is set to 0x34120000 Note The I G and U L bits of the frame DA field is located at the LSBs of the 1st octet stored in MACSTNADDR2 where the I G bit is bit 15 and the U L bit is bit 14 MACSTADDR2R MAC Station Address Part 2 Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SA5 SA6 Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16...

Page 862: ...gement read write cycles if requested 0 MII management enabled 1 MII management reset 1 26 0 Reserved Write to zero for future compatibility NOPRE 27 0 No Preamble Setting this bit causes the MII management to suppress preamble generation and reduce the management cycle from 64 clocks to 32 clocks in accordance with IEEE Std 802 3 22 2 4 4 2 Clearing this bit causes the MII management to perform m...

Page 863: ... 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCYC RCYC Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 67 MIIMCOMR Bit Descriptions Bit Reset Description 0 29 0 Reserved Write to zero for future compatibility SCYC 30 0 Scan Cycle Causes the MII management to perform continuous read cycles which is useful for monitorin...

Page 864: ...tibility PHYADDR 19 23 0 PHY Address The 5 bit PHY address field of management cycles Up to 31 PHYs can be addressed 0 is reserved The default value is 0x00 24 26 0 Reserved Write to zero for future compatibility RADDR 27 31 0 Register Address The 5 bit register address field of management cycles Up to 32 registers can be accessed The default value is 0x00 MIIMCONR MII Management Control Register ...

Page 865: ... 16 31 0 PHY Status Following an MII management read cycle you can read the 16 bit data from this location The default value is 0x0000 MIIMINDR MII Management Indicator Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NV SCAN BUSY Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 71 MIIMIND Bit D...

Page 866: ...t in MII mode 0 In RMII mode the clock source ETHREF_CLK is 50 MHz to support 100 Mbps operation In SMII mode the clock source ETHCLOCK is 125 MHz to support 100 Mbps operation 1 In RMII mode the clock source ETHREF_CLK is divided by 10 5 MHz to support 10 Mbps Operation In SMII mode the clock source ETHCLOCK is divided by 10 12 5 MHz to support 10Mbps Operation 26 0 Reserved LBMODE 27 0 RMII SMII...

Page 867: ...0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IR DS Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 73 MIGSK_GPR Bit Descriptions Bit Reset Description Settings 0 27 0 Reserved IR 27 Ethernet Controller Internal Reset Puts all Ethernet controller modules into reset Note MIIGSK_GPR is not reset by the Ethernet controller Internal Reset 0 Normal operation 1 Internal Reset 3...

Page 868: ...ignal is disabled MIIGSK_ENR MIIGSK Enable Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 READY EN Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 74 MIGSK_ENR Bit Descriptions Bit Reset Description Settings 0 29 0 Reserved READY 30 0 Ready This bit is set when the Ethernet controller is ...

Page 869: ...nly packet data For a MAC to MAC connection TXD 7 0 transfer signal status values You can write any value to these bits but the SMII specification provides recommended status bit definitions Note MIIGSK_TIFBR can be programmed only when MIIGSK_ENR EN 0 that is the Ethernet controller is disabled Table 25 75 MIGSK_SMII_SYNCDIR Bit Descriptions Bit Reset Description Settings 0 29 0 Reserved SYNC_IN ...

Page 870: ...he 10 bit data segments transferred in the inter packet gap between frames Note If the TX_EN bit 1 this is data If TX_EN 0 this is a status bit 0 No jabber 1 Jabber TXD3 28 0 IFG Transmit Segment Data Bit 3 Part of the 10 bit data segments transferred in the inter packet gap between frames Note If the TX_EN bit 1 this is data If TX_EN 0 this is a status bit 0 Link down 1 Link up TXD2 29 0 IFG Tran...

Page 871: ... bits 1 RXD6 25 0 IFG Receive Segment Data Bit 6 Allows you to read the value of the received inter frame segment bits 0 No false carrier detected 1 False carrier detected RXD5 26 0 IFG Receive Segment Data Bit 5 Allows you to read the value of the received inter frame segment bits 0 Upper nibble invalid 1 Upper nibble valid RXD4 27 0 IFG Receive Segment Data Bit 4 Allows you to read the value of ...

Page 872: ...MIIGSK_ERIFBR MIIGSK SMII Expected Receive Inter Frame Bits Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ERXD7 ERXD6 ERXD5 ERXD4 ERXD3 ERXD2 ERXD1 ERXD0 Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 78 MIIGSK_ERIFBR Bit Descriptions Bit Reset Description 0 23 0 Reserved ERXD 7 1 24 30...

Page 873: ...5 0 Interrupt Event 6 A difference was discovered between the MIIGSK_RIFBR RXD6 bit and the MIIGSK_ERIFBR ERXD6 bit 0 No effect 1 Difference in bit 6 IE5 25 0 Interrupt Event 5 A difference was discovered between the MIIGSK_RIFBR RXD5 bit and the MIIGSK_ERIFBR ERXD5 bit 0 No effect 1 Difference in bit 5 IE4 25 0 Interrupt Event 4 A difference was discovered between the MIIGSK_RIFBR RXD4 bit and th...

Page 874: ...s Bit Reset Description Settings 0 23 0 Reserved IE7EN 24 0 Interrupt Event 7 Enable Enabled disables interrupt event 7 0 Interrupt 7 disabled 1 Interrupt 7 enabled IE6EN 25 0 Interrupt Event 6 Enable Enabled disables interrupt event 6 0 Interrupt 6 disabled 1 Interrupt 6 enabled IE5EN 25 0 Interrupt Event 5 Enable Enabled disables interrupt event 5 0 Interrupt 5 disabled 1 Interrupt 5 enabled IE4...

Page 875: ...llover condition via a carry interrupt output from the PE MSTAT Internal masking registers allow you to mask each counter rollover condition from causing an interrupt In addition each individual counter value can be reset on read access or all counters can be simultaneously reset by asserting an external module input pin TR64 is one of the RMON MIB counters it counts the 64 byte frames TR64 Transm...

Page 876: ...127 10 31 0 Transmit and Receive 65 to 127 Byte Frame Counter Increments for each good or bad frame transmitted and received that is 65 to 127 bytes long inclusive excluding preamble and SFD but including FCS bytes TR255 Transmit and Receive 128 to 255 Byte Frame Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TR255 Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 ...

Page 877: ...ibility TR511 10 31 0 Transmit and Receive 256 to 511 Byte Frame Counter Increments for each good or bad frame transmitted and received that is 256 to 511 bytes long inclusive excluding preamble and SFD but including FCS bytes TR1K Transmit and Receive 512 to 1023 Byte Frame Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TR1K Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 2...

Page 878: ...10 31 0 Transmit and Receive 1024 to 1518 Byte Frame Counter Increments for each good or bad frame transmitted and received that is 1024 to 1518 bytes long inclusive excluding preamble and SFD but including FCS bytes TRMGV Transmit and Receive 1519 to 1522 Byte VLAN Frame Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TRMGV Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 ...

Page 879: ...rite to zero for future compatibility RBYT 1 31 0 Receive Byte Counter The statistics counter increments by the byte count of frames received including those in bad packets excluding preamble and SFD but including FCS bytes RPKT Receive Packet Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RPKT Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ...

Page 880: ...for future compatibility RFCS 16 31 0 Receive FCS Error Counter Increments for each frame received that has an integral 64 to 1518 length and contains a frame check sequence error RMCA Receive Multicast Packet Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RMCA Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RMCA Type R W Reset 0 0 0 0 0 0 0 ...

Page 881: ...Reserved Write to zero for future compatibility RBCA 10 31 0 Receive Broadcast Packet Counter Increments for each valid broadcast frame of lengths 64 to 1518 non VLAN or 1522 VLAN excluding multicast frames Does not include range length errors RXCF Receive Control Frame Packet Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23...

Page 882: ...Reset Description 0 15 0 Reserved Write to zero for future compatibility RXPF 16 31 0 Receive Pause Frame Packet Counter Increments each time a valid pause MAC control frame is received RXUO Receive Unknown OPCode Packet Counter Bit 0 R1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RXUO Type R W Reset 0 0 0 0 0 0...

Page 883: ...or future compatibility RALN 16 31 0 Receive Alignment Error Counter Increments for each received frame from 64 to 1518 non VLAN or 1522 VLAN that contains an invalid FCS and is not an integral number of bytes RFLR Receive Frame Length Error Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RFLR Type R...

Page 884: ...unter Increments each time a valid carrier is present and at least one invalid data symbol is detected RCSE Receive Carrier Sense Error Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RCSE Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 99 RCSE Bit Descriptions Bits Reset Description 0 15 0 R...

Page 885: ...future compatibility RUND 16 31 0 Receive Undersize Packet Counter Increments each time a frame is received that is less than 64 bytes long and contains a valid FCS and is otherwise well formed This count does not include range length errors ROVR Receive Oversize Packet Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 ...

Page 886: ...set Description 0 15 0 Reserved Write to zero for future compatibility RFRG 16 31 0 Receive Fragments Counter Increments for each frame received that is less than 64 bytes long and contains an invalid FCS This includes integral and non integral lengths RJBR Receive Jabber Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 2...

Page 887: ...bility RDRP 16 31 0 Receive Dropped Packets Counter Increments for frames received that are streamed to the system but are later dropped due to lack of system resources TBYT Transmit Byte Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TBYT Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TBYT Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Tabl...

Page 888: ...ompatibility TPKT 10 31 0 Transmit Packet Counter Increments for each transmitted packet including bad packets excessively deferred packets excessive collision packets late collision packets and all unicast broadcast and multicast packets TMCA Transmit Multicast Packet Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TMCA Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 2...

Page 889: ...A Bit Descriptions Bits Reset Description 0 9 0 Reserved Write to zero for future compatibility TBCA 10 31 0 Transmit Broadcast Packet Counter Increments for each broadcast frame transmitted excluding multicast frames TXPF Transmit Pause Control Frame Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 T...

Page 890: ... Reset Description 0 19 0 Reserved Write to zero for future compatibility TDFR 20 31 0 Transmit Deferral Packet Counter Increments for each frame that is deferred on its first transmission attempt This count does not include frames involved in collisions TEDF Transmit Excessive Deferral Packet Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 ...

Page 891: ...ription 0 19 0 Reserved Write to zero for future compatibility TSCL 20 31 0 Transmit Single Collision Packet Counter Increments for each frame that experienced exactly one collision during transmission TMCL Transmit Multiple Collision Packet Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TMCL Type R...

Page 892: ...ons Bits Reset Description 0 19 0 Reserved Write to zero for future compatibility TLCL 20 31 0 Transmit Late Collision Packet Counter Increments for each transmit frame that experienced a late collision during a transmission attempt TXCL Transmit Excessive Collision Packet Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 ...

Page 893: ...0 31 0 Transmit Total Collision Counter Increments by the number of collisions experienced during the transmission of a frame as defined as the simultaneous presence of signals on the DO and RD circuits that is transmitting and receiving at the same time Note This count does not include collisions that result in an excessive collision condition TJBR Transmit Jabber Frame Counter Bit 0 1 2 3 4 5 6 ...

Page 894: ... 118 TFCS Bit Descriptions Bits Reset Description 0 19 0 Reserved Write to zero for future compatibility TFCS 20 31 0 Transmit FCS Error Counter Increments for every transmit packet with a valid size but an incorrect FCS value TXCF Transmit Control Frame Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3...

Page 895: ... 0 0 0 Table 25 120 TOVR Bit Descriptions Bits Reset Description 0 19 0 Reserved Write to zero for future compatibility TOVR 20 31 0 Transmit Oversize Frame Counter Increments for each oversized transmitted frame with a correct FCS value TUND Transmit Undersize Frame Counter Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 ...

Page 896: ...1 0 Transmit Fragment Counter Increments for every frame less than 64 bytes long and with an incorrect FCS value CAR1 Carry Register One Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C164 C1127 C1255 C1511 C11K C1MAX C1MGV C1RBY Type R W R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 C1RPK C1RFC C1RMC C1RBC C1RXC C1RXP C1RXU C1RAL C1RFL C1RCD C1RCS C1RU...

Page 897: ...unter Carry C1RFL 24 0 Carry Register 1 RFLR Counter Carry C1RCD 25 0 Carry Register 1 RCDE Counter Carry C1RCS 26 0 Carry Register 1 RCSE Counter Carry C1RUN 27 0 Carry Register 1 RUND Counter Carry C1ROV 28 0 Carry Register 1 ROVR Counter Carry C1RFR 29 0 Carry Register 1 RFRG Counter Carry C1RJB 30 0 Carry Register 1 RJBR Counter Carry C1RDR 31 0 Carry Register 1 RDRP Counter Carry CAR2 Carry R...

Page 898: ... C2TFG 17 0 Carry Register 2 TFRG Counter Carry C2TBY 18 0 Carry Register 2 TBYT Counter Carry C2TPK 19 0 Carry Register 2 TPKT Counter Carry C2TMC 20 0 Carry Register 2 TMCA Counter Carry C2TBC 21 0 Carry Register 2 TBCA Counter Carry C2TPF 22 0 Carry Register 2 TXPF Counter Carry C2TDF 23 0 Carry Register 2 TDFR Counter Carry C2TED 24 0 Carry Register 2 TEDF Counter Carry C2TSC 25 0 Carry Regist...

Page 899: ...t Descriptions Bits Reset Description M164 0 1 Mask Register 1 TR64 Counter Carry Mask M1127 1 1 Mask Register 1 TR127 Counter Carry Mask M1255 2 1 Mask Register 1 TR255 Counter Carry Mask M1511 3 1 Mask Register 1 TR511 Counter Carry Mask M11k 4 1 Mask Register 1 TR1K Counter Carry Mask M1MAX 5 1 Mask Register 1 TRMAX Counter Carry Mask M1MGV 6 1 Mask Register 1 TRMGV Counter Carry Mask 7 14 0 Re...

Page 900: ... Mask Register 1 RJBR Counter Carry Mask M1RDR 31 1 Mask Register 1 RDRP Counter Carry Mask CAM2 Carry Register Two Mask Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 M2TJB M2TFC M2TXC M2TOV Type R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 M2TUN M2TFG M2TBY M2TPK M2TMC M2TBC M2TPF M2TDF M2TED M2TSC M2TMA M2TLC M2TXC M2TNC M2TPH M2TDP Type R W Reset 1...

Page 901: ... 1 Mask Register 2 TFRG Counter Carry Mask M2TBY 18 1 Mask Register 2 TBYT Counter Carry Mask M2TPK 19 1 Mask Register 2 TPKT Counter Carry Mask M2TMC 20 1 Mask Register 2 TMCA Counter Carry Mask M2TBC 21 1 Mask Register 2 TBCA Counter Carry Mask M2TPF 22 1 Mask Register 2 TXPF Counter Carry Mask M2TDF 23 1 Mask Register 2 TDFR Counter Carry Mask M2TED 24 1 Mask Register 2 TEDF Counter Carry Mask ...

Page 902: ...r the 8 bits of the CRC remainder is mapped to one of the 256 entries You can enable a hash entry by setting the appropriate bit A hash table hit occurs if the DA CRC result points to an enabled hash entry IADDR 0 7 Individual Address Registers 0 7 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IADDRn Type R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IAD...

Page 903: ...e last RxBD The pattern match feature is supported in both 8 byte and 32 byte RxBD mode In 8 byte mode however the limited size of the BD limits only the reporting of the results of the matching process not the pattern matching itself PMASKn is a set of user programmable registers bytes 0 1 2 3 to mask a pattern match associated with the PMDn registers Data is masked on a bit by bit basis thus all...

Page 904: ... W R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 25 130 PCNTRLn Bit Descriptions Bits Reset Description Settings 0 17 Reserved Write to zero for future compatibility MI 18 23 0 Matching Index Specifies the index in multiples of 4 bytes from the start of the receive frame from the DA field to FCS inclusive to perform the pattern matching For example MI as cleared corresponds to the first 4 bytes of...

Page 905: ... 0 Reserved Write to zero for future compatibility PMC 30 31 0 Pattern Match Control Controls the filtering of frames based on pattern matching 00 Entry disabled 01 Pattern Match The pattern is not the criterion used for accepting or rejecting a frame if a match occurs It is used only for filing data on a frame that is accepted based on a previous pattern one with a PMC 10 or on DA recognition 10 ...

Page 906: ...3 0 Reserved Write to zero for future compatibility RDSEN 24 0 Rx Data Snoop Enable Enables disables snooping of all receive frame data to memory 0 Disables snooping of all receive frame data to memory 1 Enables snooping of all receive frame data to memory RBDSEN 25 0 RxBD Snoop Enable Enables disables snooping of all RxBD memory accesses 0 Disables snooping of all receive BD memory accesses 1 Ena...

Page 907: ...5 132 DATTR Bit Descriptions Bits Reset Description Settings 0 23 0 Reserved Write to zero for future compatibility RDSEN 24 0 Rx Data Snoop Enable Enables disables snooping of all receive frame data to memory 0 Disables receive frame data to memory snooping 1 Enables receive frame data to memory snooping RBDSEN 25 0 RxBD Snoop Enable Enables disables snooping of all receive BD memory accesses 0 D...

Page 908: ... by the user 0 The next BD is in the consecutive location 1 The next BD is in the location defined in TBASE Offset 0 I 3 Interrupt Specifies whether an interrupt is generated after this buffer is processed This bit is written by the user 0 No interrupt is generated after this buffer is serviced 1 EVENT TXB or IEVENT TXF are set after this buffer is serviced These bits can cause an interrupt if the...

Page 909: ...updates RC after sending the buffer 0 The frame is sent correctly the first time x More than zero attempts were needed to send the transmit frame 0x00 UN 14 Underrun Indicates when a transmitter underrun condition is encountered When this bit is set the Ethernet controller terminates the transmission and updates UN 0 No underrun encountered data was retrieved from external memory in time to send a...

Page 910: ...nsertion with expansion Software programs the right TYPE LENGTH field in the BD to take into account any inserted data Offset 0x08 TX Data Buffer Pointer Offset 0x10 Offset 0x12 Reserved Offset 0x14 Offset 0x 16 TX Insert Buffer Pointer Offset 0x18 Offset 0x20 Reserved Offset 0x22 Reserved IE IT Offset 0x24 Insert Index Offset 0x26 Insert Length Offset 0x28 Reserved Offset 0x30 Reserved TxBD 32 By...

Page 911: ...r 0 The next BD is in the consecutive location 1 The next BD is in the location defined in TBASE 0x00 I 3 Interrupt Specifies whether an interrupt is generated after this buffer is processed This bit is written by the user 0 No interrupt is generated after this buffer is serviced 1 EVENT TXB or IEVENT TXF are set after this buffer is serviced These bits can cause an interrupt if they are enabled t...

Page 912: ...is field is 15 then 15 or more retries were needed The Ethernet controller updates RC after sending the buffer 0 The frame is sent correctly the first time x More than zero attempts were needed to send the transmit frame 0x00 UN 14 Underrun Indicates when a transmitter underrun condition is encountered When this bit is set the Ethernet controller terminates the transmission and updates UN 0 No und...

Page 913: ... is greater than the TxBD DL Transmission of frames continues so a partial insertion can occur within the frame 0 If TxBD IT 01 or 10 no insertion error 1 An error occurred during an attempt to insert data 0x22 IT 14 15 Insertion Type Defines the type of insertion to perform This field is written by the user 00 No insertion 01 Replacement 10 Expansion 11 Reserved 0x24 II Insert Index Contains the ...

Page 914: ... controller when cleared and by the user when set 0 The data buffer of this BD is filled with received data or data reception is aborted due to an error condition 1 The data buffer of this BD is empty or reception is currently in progress 0x00 RO1 1 Receive Software Ownership This field is reserved for use by software Hardware does not modify this read write bit nor does its value affect hardware ...

Page 915: ...id only if L is set 0 Normal operation 1 Frame length exceeds the maximum frame length 0x00 NO 11 Rx Non octet Aligned Frame A frame that contained a number of bits not divisible by eight was received This bit is written by the Ethernet controller and is valid only if L is set 0 Normal operation 1 Frame contains a number of bits not divisible by eight 0x00 SH 12 Short Frame The length of a frame i...

Page 916: ... buffer and must be 64 byte aligned The buffer must reside in memory external to the Ethernet controller This field is written by the user RxBD 32 Byte Receive Buffer Descriptor Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0x00 E RO1 W I L F 0 M BC MC LG NO SH CR OV TR Offset 0x02 Data Length Offset 0x04 Reserved Offset 0x06 Offset 0x08 RX Data Buffer Pointer Offset 0x10 Offset 0x12 Reserved O...

Page 917: ...ed This bit is written by the user If you want the interrupt to occur only if RXF0 occurs disable RXB0 IMASK RXBEN0 is cleared and enable RXF0 IMASK RXFEN0 is set 0 No interrupt is generated after this buffer is serviced 1 IEVENT RXBn or IEVENT RXFn are set after this buffer is serviced These bits can cause an interrupt if enabled IMASK RXBENn or IMASK RXFENn 0x00 L 4 Last in Frame Specifies wheth...

Page 918: ...ntroller and is valid only if L is set 0 Normal operation 1 CRC error or receive code group error 0x00 OV 14 Overrun A receive FIFO overrun occurred during frame reception If this bit is set the other status bits M LG NO SH CR and CL lose their normal meaning and are zero This bit is written by the Ethernet controller and is valid only if L is set 0 Normal operation 1 Receive FIFO overrun 0x00 TR ...

Page 919: ...rn match Offset 20 MM 9 Multiple Match Indicates that two or more patterns matched This bit is written by Ethernet controller It contains valid information only while PM is set 0 No more than one pattern matched 1 Two or more patterns matched Offset 20 ABPM 10 Accepted Base on Pattern Match The frame was accepted based on a pattern match This bit is written by the Ethernet controller 0 Frame was a...

Page 920: ...MSC8113 Reference Manual Rev 0 25 150 Freescale Semiconductor Ethernet Controller ...

Page 921: ...ramming sheets are based on the default QBus bank settings The DSI addressing is also fixed Local bus addressing depends on the base addresses selected by the ISBSEL bits in the Hard Reset Configuration Word HRCW which is loaded during a power on reset The memory map in Chapter 8 provides a detailed listing of the various possibilities and the programming sheets reference the specific page where t...

Page 922: ...em interrupt 24 5 VS16 Virtual System interrupt 16 6 VS8 Virtual System interrupt 8 7 VS0 Virtual System interrupt 0 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 UART UART Interrupt 13 TMCNT Time Counter 14 PIT Periodic Interrupt Timer 15 DMA DMA global interrupt 16 IRQ15 IRQ15 Signal 17 IRQ14 IRQ14 Signal 18 IRQ13 IRQ13 Signal 19 IRQ12 IRQ12 Signal 20 IRQ11 IRQ11 Signal 21 IRQ10 IRQ10 Signal ...

Page 923: ... 10 TDM1TSTE TDM1 Transmit Second Threshold Event 11 TDM1TFTE TDM1 Transmit First Threshold Event 12 TDM2RXER TDM2 Receive Error sum of TDM receive error detections 13 TDM2RSTE TDM2 Receive Second Threshold Event 14 TDM2RFTE TDM2 Receive First Threshold Event 15 TDM2TXER TDM2 Transmit Error sum of TDM transmit error detections 16 TDM2TSTE TDM2 Transmit Second Threshold Event 17 TDM2TFTE TDM2 Trans...

Page 924: ...Timer Block A Timer 3 Compare Flag 12 TIMER8A Timer Block A Timer 8 Compare Flag 13 TIMER9A Timer Block A Timer 9 Compare Flag 14 TIMER10A Timer Block A Timer 10 Compare Flag 15 TIMER11A Timer Block A Timer 11 Compare Flag 16 UART UART Tx Rx Interrupt global 17 PIT Periodic Interrupt Timer global 18 TMCNT Timer Counter global 19 IRQ1 IRQ1 signal global 20 VIRQ0 Virtual Interrupt Number 0 21 VIRQ1 ...

Page 925: ...Timer 7 Compare Flag 12 TIMER12A Timer Block A Timer 12 Compare Flag 13 TIMER13A Timer Block A Timer 13 Compare Flag 14 TIMER14A Timer Block A Timer 14 Compare Flag 15 TIMER15A Timer Block A Timer 15 Compare Flag 16 UART UART Tx Rx Interrupt global 17 PIT Periodic Interrupt Timer global 18 TMCNT Timer Counter global 19 IRQ1 IRQ1 signal global 20 VIRQ8 Virtual Interrupt Number 8 21 VIRQ9 Virtual In...

Page 926: ...mer Block B Timer 3 Compare Flag 12 TIMER8B Timer Block B Timer 8 Compare Flag 13 TIMER9B Timer Block B Timer 9 Compare Flag 14 TIMER10B Timer Block B Timer 10 Compare Flag 15 TIMER11B Timer Block B Timer 11 Compare Flag 16 UART UART Tx Rx Interrupt global 17 PIT Periodic Interrupt Timer global 18 TMCNT Timer Counter global 19 IRQ1 IRQ1 signal global 20 VIRQ16 Virtual Interrupt Number 16 21 VIRQ17...

Page 927: ...erved 0x940 0x26 IRQ6 LIC IRQOUTA0 Group A 0x980 0x27 IRQ7 LIC IRQOUTA1 Group A 0x9C0 0x28 IRQ8 LIC IRQOUTA2 Group A 0xA00 0x29 IRQ9 LIC IRQOUTA3 Group A 0xA40 0x2A IRQ10 Bus controller x y contention 0xA80 0x2B IRQ11 Bus controller level1 contention 0xAC0 0x2C IRQ12 Bus controller p x contention 0xB00 0x2D IRQ13 Bus controller nonaligned data error 0xB40 0x2E IRQ14 LIC IRQOUTB0 Group B 0xB80 0x2F...

Page 928: ...NMI parity error bus monitor 0xFC0 Table A 7 Guide to MSC8113 Programming Sheets Module Programming Sheet Type Page SC140 Core Status Register SR R W page A 16 Exception and Mode Register EMR R W page A 17 EQBS Configuration QBus Mask for Bank 0 QBUSMR0 R W page A 18 QBus Base for Bank 0 QBUSBR0 R W page A 18 QBus Mask for Bank 1 QBUSMR1 R W page A 18 QBus Base for Bank 1 QBUSBR1 R W page A 18 QBu...

Page 929: ... Status and Control Register L_TESCR1 R W page A 36 Timer Counter Status and Control Register TMCNTSC R W page A 37 Time Counter Register TMCNT R W page A 38 Time Counter Alarm Register TMCNTAL R W page A 38 Periodic Interrupt Status and Control Register PISCR R W page A 39 Periodic Interrupt Timer Count Register PITC R W page A 39 Memory Controller Base Registers BR 0 7 9 11 R W page A 40 Option ...

Page 930: ...y Register A ELIRA PIC Edge Level Triggered Interrupt Priority Register B ELIRB R W page A 56 PIC Edge Level Triggered Interrupt Priority Register C ELIRC PIC Edge Level Triggered Interrupt Priority Register D ELIRD R W page A 57 PIC Edge Level Triggered Interrupt Priority Register E ELIRE PIC Edge Level Triggered Interrupt Priority Register F ELIRF R W page A 58 Interrupt Pending Register A Inter...

Page 931: ... 0 3 TDBS R W page A 79 TDM 0 3 Receive Global Base Address TDM 0 3 RGBA R W page A 80 TDM 0 3 Transmit Global Base Address TDM 0 3 TGBA R W page A 80 TDM 0 3 Adaptation Control Registers TDM 0 3 ACR R W page A 81 TDM 0 3 Receive Control Registers TDM 0 3 RCR R W page A 82 TDM 0 3 Transmit Control Registers TDM 0 3 TCR R W page A 82 TDM 0 3 Receive Data Buffers First Threshold TDM 0 3 RDBFT R W pa...

Page 932: ...DR R W page A 99 Pin Data Register PDAT R W page A 99 Pin Data Direction Register PDIR R W page A 99 Pin Assignment Register PAR R W page A 100 Pin Special Options Register PSOR R W page A 100 Ethernet Controller Interrupt Event Register IEVENT R W page A 101 Interrupt Mask Register IMASK R W page A 102 Ethernet Control Register ECNTRL R W page A 103 Minimum Frame Length Register MINFLR R W page A...

Page 933: ...us Register RSTAT R W page A 118 RxBD Data Length Register RBDLEN R W page A 119 Current RxBD Pointer CRBPTR R W page A 119 Maximum Receive Buffer Length R0R1 Register MRBLR0R1 R W page A 120 Maximum Receive Buffer Length R2R3 Register MRBLR2R3 R W page A 120 RxBD Pointer 0 3 RBPTR 0 3 R W page A 121 Receive Descriptor Base Address 0 3 RBASE 0 3 R W page A 121 MAC Configuration 1 Register MACCFG1R...

Page 934: ...ame Counter TRMGV R W page A 138 Receive Byte Counter RBYT R W page A 138 Receive Packet Counter RPKT R W page A 139 Receive FCS Error Counter RFCS R W page A 139 Receive Multicast Packet Counter RMCA R W page A 140 Receive Broadcast Packet Counter RBCA R W page A 140 Receive Control Frame Packet Counter RXCF R W page A 141 Receive Pause Frame Packet Counter RXPF R W page A 141 Receive Unknown OPC...

Page 935: ...ol Frame Counter TXCF R W page A 154 Transmit Oversize Frame Counter TOVR R W page A 155 Transmit Undersize Frame Counter TUND R W page A 155 Transmit Fragment Counter TFRG R W page A 156 Carry Register One CAR1 R W page A 157 Carry Register Two CAR2 R W page A 158 Carry Register One Mask CAM1 R W page A 159 Carry Register Two Mask CAM2 R W page A 160 Individual Address Registers 0 7 IADDR 0 7 R W...

Page 936: ...arry from last addition or borrow from last subtraction 0 No carry borrow generated C Carry Bit 0 1 Compare or test instruction condition is true 0 Compare or test instruction condition is false T True Bit 1 1 Arithmetic saturation mode selected 0 Arithmetic saturation mode not selected SM Saturation Mode Bit 2 1 Two s complement rounding selected 0 Convergent rounding selected RM Rounding Mode Bi...

Page 937: ...Execution Set Bit 1 1 Overflow or arithmetic saturation occurred 0 No overflow or arithmetic saturation occurred DOVF Data ALU Overflow Bit 2 1 NMI disabled NMI service executing 0 NMI enabled no NMI service is executing NMID Non maskable Interrupt Disable Bit 3 GP 6 0 General Purpose Flags Bits 23 17 EE1 value 0 ISBSEL2 Hard Reset Configuration Word bit 15 ISBSEL1 Hard Reset Configuration Word bi...

Page 938: ...0FF02 0x00F0FF06 0x00F0FF0A Reset QBUSBR0 0x00F0 QBUSBR1 0x0100 QBUSR2 0x0000 Read Write EQBS Bank Base 0 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QBUSMR 1 2 QBus Mask Registers 0 2 Addresses 0x00F0FF04 0x00F0FF08 Reset QBUSMR1 0xFF00 Boot rewrites to 0XFF80 QBUSMR2 0xFFFF Read Write Bank Mask 0 15 Note QBUSMR0 is a read only register with a reset mask value of 0xFFFF QBUSBR 0 2 QBUSMR 1 2 ...

Page 939: ...11 12 13 14 15 ICABR Instruction Cacheable Area Base Register Address 0x00F0FF32 Reset 0x0080 Read Write Area Base 0 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 EN REV SIZE 1 Size is 64 KB 0 Size is not 64 KB SIZE Size Indication Bit 7 1 Cacheable area outside the area definition 0 Cacheable area inside the area definition REV Reverse Cacheable Area Bit 6 1 Area enabl...

Page 940: ...l Register Address 0x00F0FF82 Reset 0x13FF Read Write WD 9 0 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 PFOFF 000 1 SIZE 2 0 Block Size SIZE Block Size Bits 13 15 1 Pre fetch disabled 0 Pre fetch enabled PFOFF Pre fetch Off Bit 11 SIZE 001 2 010 4 011 111 reserved 0 0 0 WBOFF 0 0 Reserved Write to 0 for future compatibility 1 Write Buffer disabled 0 Write Buffer enabled W...

Page 941: ... 21 Contains the area base address for the data area Area Base 31 16 15 8 Area Base Address Bits 0 15 24 31 IMM Immediate Bits 17 18 Regular write through Write Buffer Write immediate Write immediate with no freeze Reserved do not use 00 01 10 11 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FLBACR0 FlyBy Address Control Register Reset 0x00000000 EQBS DBR ...

Page 942: ... TT 2 4 CS 5 7 is CS 5 7 0 TT0 Res is TT0 and TT 2 4 CS 5 7 is TT 2 4 TTPC Transfer Type Pin Configuration Bit 20 OUT BPS MODCK_H DLL END DIS TCPC CS5 PC MMR BBD ISBSEL OUT DPPC ISPS SCDIS 1 IRQ7 INT_OUT signal is INT_OUT 0 IRQ7 INT_OUT signal is IRQ7 INTOUT INT_OUT IRQ7 Selection Bit 2 1 60x compatible bus mode 0 Single MSC8113 bus mode EBM External 60x Compatible Bus Mode Bit 3 01 8 bit port 00 ...

Page 943: ...rnal hard reset event occurred EHRS External Hard Reset Status Bit 31 1 External soft reset occurred 0 No external soft reset event occurred ESRS External Soft Reset Status Bit 30 1 Bus monitor reset occurred 0 No bus monitor reset event occurred BMRS Bus Monitor Reset Status Bit 29 1 A software watchdog reset occurred 0 No software watchdog reset event occurred SWRS Software Watchdog Reset Status...

Page 944: ...abled 0 Strict 60x compatible system bus mode Extended transfer mode is disabled ETM Compatibility Mode Enable Bit 12 1 Extended transfer mode is enabled on the local bus 0 Extended transfer mode is disabled in the local bus LETM Local Bus Compatibility Mode Enable Bit 13 1 Even parity 0 Odd parity EPAR Even Parity Bit 14 1 0 The bus master connected to the arbitration lines is an NPQM 0 2 Non MSC...

Page 945: ...DBG asserted with TS if data bus is not busy DBGD Data Bus Grant Delay Bit 2 1 External arbitration 0 Internal arbitration EARB External Arbitration Bit 3 Note The reset value is determined by the EARB bit in the Hard Reset Configuration Word PRKM Parking Master Bits 4 7 Reserved DSI 0000 0011 0100 SC140 core interface Reserved 0101 0110 External master 1 External master 2 0111 1000 External maste...

Page 946: ... Priority Field 10 Priority Field 11 Priority Field 12 Priority Field 13 Priority Field 14 Priority Field 15 System Bus Master Indices See PPC_ACR Reserved DSI 0x0 0x3 0x4 SC140 core interface Reserved 0x5 0x6 External master 1 External master 2 0x7 0x8 External master 3 DMA priority 0 0x9 0xA DMA priority 1 0xB DMA priority 2 Reserved 0xC 0xD 0xF Note PPC_ALRH and PPC_ALRL assign arbitration prio...

Page 947: ...0 for future compatibility DBGD 1 DBG asserted 1 cycle after TS if data bus is not busy 0 DBG asserted with TS if data bus is not busy DBGD Data Bus Grant Delay Bit 2 PRKM Parking Master Bits 4 7 TDM high priority 0000 Reserved Reserved 0001 0010 0011 0100 DMA priority 0 0101 1001 1010 DMA priority 1 1011 DMA priority 2 Reserved 1100 1101 1111 0 DSI Host bridge TDM low priority LCL_ACR DSI Address...

Page 948: ...10 Priority Field 11 Priority Field 12 Priority Field 13 Priority Field 14 Priority Field 15 Note LCL_ALRH and LCL_ALRL assign arbitration priorities for sixteen potential local bus masters Priority 0 is the highest and Priority 15 is the lowest The local bus master index number defines each master uniquely Assign the priority for a local bus master by entering its index number in the appropriate ...

Page 949: ...n is INT_OUT 0 IRQ7 INT_OUT pin is IRQ7 INTOUT IRQ7 or INT_OUT Selection Bit 3 DP1 IRQ1 EXT_BG2 IRQ1 DP1 IRQ1 EXT_BG2 DP2 IRQ2 EXT_DBG2 IRQ2 DP2 RES EXT_DBG2 DP3 IRQ3 EXT_BR3 IRQ3 DP3 RES EXT_BR3 DP4 IRQ4 EXT_BG3 DREQ3 IRQ4 DP4 DREQ3 EXT_BG3 DP5 IRQ5 EXT_DBG3 DREQ4 IRQ5 DP5 DREQ4 EXT_DBG3 DP6 IRQ6 DACK3 IRQ6 DP6 DACK3 IRQ6 00 01 10 11 DPPC 0 1 Data Parity Pin Configuration Bits 4 5 Pin SIU RES DP0...

Page 950: ... 1 System Interface Unit SIUMCR 001 010 011 000 BM 0 2 Boot Mode Bits 7 9 1 CS5 BCTL1 is BCTL1 CS5PC Buffer Control 1 or CS5 Pin Configuration Bit 12 CS5 BCTL1 is CS5 0 01 BCTL0 W R BCTL1 OE 00 BCTL0 W R BCTL1 OE BCTLC 0 1 Buffer Control Configuration Bits 14 15 11 Reserved 10 BCTL0 WE BCTL1 RE 1 0 No masking on bus request lines MMR Mask Masters Requests Bit 16 All external bus requests masked bo...

Page 951: ...y SIU 0 Defines the base address of the internal memory space The ISBSEL ISB Internal Space Base Bits 0 14 Bits 0 15 Read Write ISB bits in the HRCW select one of the following initial addresses ISBSEL Value Internal Base Address PARTNUM MASKNUM mask number A read only field containing a code corresponding to the device PARTNUM Part Number Bits 16 23 part number 000 001 010 011 100 101 110 111 0xF...

Page 952: ...Contains the count value for the software watchdog timer SWTC Software Watchdog Timer Count Bits 0 15 1 Local bus monitor is enabled 0 Local bus monitor is disabled LBME Local Bus Monitor Enable Bit 25 1 Software watchdog timer is enabled 0 Software watchdog timer is disabled SWE Software Watchdog Enable Bit 29 1 Software watchdog timer clock is prescaled 0 Software watchdog timer is not prescaled...

Page 953: ...fter reset The register feeds a state machine that controls the watchdog timer Once the state machine is reset it enters State 0 waiting for 0x556C Receipt of any other value causes the state machine to remain in State 0 Writing 0x556C to the SWSR causes the state machine to go to State 1 where it waits for a write of 0xAA39 to the SWSR If any other value is written the state machine returns to St...

Page 954: ...burst write 00000 00001 00010 Reserved Single beat or burst read 00011 01001 01010 DMD Data Errors Disable Bit 17 Data errors on system bus enabled Data errors on system bus disabled 0 1 WP Write Protect Error Bit 5 No write protect error occurred Attempted write to a read only area error occurred 0 1 ECC1 Single ECC Error Bit 4 No single bit ECC error occurred TEA asserted due to single bit ECC e...

Page 955: ...al register transaction error Internal register transaction error occurred 0 1 0 0 0 0 0 0 PB Parity Error on Byte Each bit is a status bit for a byte lane on the system bus Bits 8 15 No error occurred on the byte lane Parity error detected on the byte lane 0 1 BNK Memory Controller Bank Each bit is a status bit for a memory controller external bank Bits 16 23 No error occurred on memory controlle...

Page 956: ... 000 001 TDM Reserved 010 011 0 0 0 0 0 0 TT WP BM Local Bus Monitor Time Out Bit 0 No local bus monitor time out TEA asserted due to local bus monitor time out 0 1 TT Transfer Type Bits 11 15 Reserved Single beat or burst write 00000 00001 00010 Reserved Single beat or burst read 00011 01001 01010 WP Write Protect Error Bit 5 No write protect error occurred Attempted write to a local bus read onl...

Page 957: ...t 9 1 The time counter generates an interrupt when ALR 0 No alarm interrupt ALE Alarm Interrupt Enable Bit 13 is set 1 The time counter is enabled 0 The time counter is disabled TCE Time Counter Enable Bit 15 1 The input clock to the time counter is 32 kHz 0 The input clock to the time counter is 4 MHz TCF Time Counter Frequency Bit 14 0 0 0 0 1 The time counter generates an interrupt when SEC 0 T...

Page 958: ... counter value TMCNT MD Reset 0x00000000 Read Write Time Counter Alarm Register ALARM Alarm Value Bits 0 31 An alarm interrupt is generated when ALARM TMCNT TMCNTAL Reset 0x00000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ALARM The ALARM resolution is 1 second TMCNT TMCNTAL DSI Address 0x1D0224 QBus System Bus Address ___________ See page 8 ...

Page 959: ...Hz PTF Periodic Interrupt Frequency Bit 14 1 PIT is enabled 0 PIT is disabled PTE Periodic Timer Enable Bit 15 Periodic Interrupt Timer Count Register PITC Periodic Interrupt Timing Count Bits 0 15 Contains the count for the periodic timer Setting PITC to 0xFFFF PITC Reset 0x00000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PITC selects the m...

Page 960: ...g 00 Data errors checking disabled DECC 0 1 Data Error Correction and Checking Bits 21 22 11 Read modify write parity checking ECC correction and checking 01 1 Only read access is allowed 0 Read and write accesses are allowed WP Write Protect Bit 23 0 Bank is invalid V Valid Bit Bit 31 1 Bank is valid 1 Data beats of accesses to the address space controlled 0 No data pipelining is done DR Data Pip...

Page 961: ... output a quarter of a clock after the address lines 11 CS is output half a clock after the address lines ACS Address to Chip Select Setup Bits 21 22 01 00 Reserved CS is output at the same time as the address lines 1 CS PWE is deasserted a quarter clock early 0 CS PWE is deasserted normally CSNT Chip Select Negation Time Bit 20 1111 15 clock cycles wait states 0000 0 clock cycle wait states SCY C...

Page 962: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Memory Controller OR 0 7 9 11 Reset 0 0 0 0 10 8 internal banks per device not valid for 128 Mb 11 Reserved BPD Banks Per Device Bits 17 18 01 00 4 internal banks per device 2 internal banks per device SDRAMs ROWST 0 3 Row Start Address Bit Bits 19 22 NUMR Number of Row Address Lines Bits 23 25 IBID Internal Bank Interleaving Within Same Device Disable Bit 27 SD...

Page 963: ...emory bank 0 BCTLx is asserted upon access to the memory bank BCTLD Data Buffer Control Disable Bit 19 10 Four idle clock cycles are inserted 11 Eight idle clock cycles are inserted EHTR Extended Hold Time on Read Accesses Bits 29 30 01 00 One idle clock cycle is inserted No additional cycles are inserted normal timing generated 1 Bank does not support burst accesses UPMx executes 0 Bank supports ...

Page 964: ...dress Multiplex Size Bits 5 7 External A 8 23 PPC Bus Address Pin AMx Signal Driven on External Pin 011 A 16 31 External A 5 20 PPC Bus Address Pin AMx Signal Driven on External Pin 001 A 16 31 A 7 22 100 A 17 31 A 5 19 010 A 16 31 A 6 21 101 A 18 31 A 5 18 00 1 cycle disable period DSx 0 1 Disable Timer Period Bits 8 9 10 3 cycle disable period 01 2 cycle disable period 11 4 cycle disable period ...

Page 965: ... 15 17 111 A 19 21 000 A 13 31 SDAM Address Multiplex Size Bits 5 7 External A 5 23 System Bus Address Pin SDAM Signal Driven on External Pin 011 A 16 31 External A 5 20 System Bus Address Pin SDAM Signal Driven on External Pin 001 A 14 31 A 5 22 100 A 17 31 A 5 19 010 A 15 31 A 5 21 101 A 18 31 A 5 18 000 A12 010 A10 100 A8 110 A6 SDA10 A10 Control Bits 11 13 PBI 0 001 A11 011 A9 101 A7 111 A5 PB...

Page 966: ...01 1 cycle 10 2 cycles 11 Reserved LDOTOPRE Last Data Out to Precharge Bits 24 25 0 SDRAM burst length is 4 BL Burst Length Bit 23 1 SDRAM burst length is 8 001 1 clock cycle ACTTORW Activate to Read Write Interval Bits 20 22 010 2 clock cycles 111 7 clock cycles 000 8 clock cycles 000 Reserved RFRC Refresh Recovery Bits 14 16 100 6 clock cycles 010 4 clock cycles 110 8 clock cycles 001 3 clock cy...

Page 967: ...array when a WRITE MDR MD Reset 0x00000000 Read Write or READ command is supplied to the UPM Memory Address Register A Memory Address Bits 0 31 Address generated under the control of the AMx bits in the UPM MAR Reset 0x00000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A MDR MAR DSI Address 0x1D0188 QBus System Bus Address ___________ See page...

Page 968: ...ture compatibility PURT UPM Refresh Timer Bits 0 7 Used to select the UPM refresh rate PURT Bus frequency required refresh rate MPTPR PTP 1 1 PSRT SDRAM Refresh Timer Bits 0 7 PTP Timer Prescaler Bits 0 7 Used to divide the bus clock to determine the refresh period base value prescaler clock frequency bus frequency PTP 1 Used to select the UPM refresh rate PSRT Bus frequency required refresh rate ...

Page 969: ...S0 VS 31 24 Virtual Source Reserved Reserved Reserved Reserved VS31 VS30 VS29 VS28 Reserved Reserved Reserved Reserved VS27 VS26 VS25 VS24 Interrupt Status Bits 0 7 Reserved VS 23 16 Virtual Source VS Interrupt 7 VS Interrupt 6 VS Interrupt 5 VS Interrupt 4 VS23 VS22 VS21 VS20 VS Interrupt 3 VS Interrupt 2 VS Interrupt 1 VS Interrupt 0 VS19 VS18 VS17 VS16 Interrupt Status Bits 8 15 Used for Core 2...

Page 970: ...24 EL25 EL26 EL27 EL28 EL29 EL30 EL 4 7 Edge Level EL4 EL5 EL6 EL7 VS Interrupts 0 VS Interrupts 8 VS Interrupts 16 VS Interrupts 24 Bits 0 7 EL 12 15 Edge Level UART Interrupt TMCNT Interrupt PIT Interrupt DMA Interrupt EL12 EL13 EL14 EL15 Bits 12 15 EL 16 23 Edge Level IRQ15 IRQ14 IRQ13 IRQ12 EL16 EL17 EL18 EL19 IRQ11 IRQ10 IRQ9 IRQ8 EL20 EL21 EL22 EL23 Bits 16 23 EL 24 30 Edge Level IRQ7 IRQ6 I...

Page 971: ...errupt TMCNT Interrupt PIT Interrupt DMA Interrupt EN12 EN13 EN14 EN15 Bits 12 15 EN 16 23 Enable IRQ15 IRQ14 IRQ13 IRQ12 EN16 EN17 EN18 EN19 IRQ11 IRQ10 IRQ9 IRQ8 EN20 EN21 EN22 EN23 Bits 16 23 EN 24 30 Enable IRQ7 IRQ6 IRQ5 IRQ4 EN24 EN25 EN26 EN27 IRQ3 IRQ2 IRQ1 EN28 EN29 EN30 Bits 24 30 Note The EN bits configure the specified interrupts as external 0 0 0 0 0 0 0 0 0 EN 4 7 12 30 Enable Bits 4...

Page 972: ...pt 8 VS Interrupt 16 VS Interrupt 24 Bits 0 7 GIS 12 15 Edge Level UART Interrupt TMCNT Interrupt PIT Interrupt DMA Interrupt GIS12 GIS13 GIS14 GIS15 Bits 12 15 GIS 16 23 Edge Level IRQ15 IRQ14 IRQ13 IRQ12 GIS16 GIS17 GIS18 GIS19 IRQ11 IRQ10 IRQ9 IRQ8 GIS20 GIS21 GIS22 GIS23 Bits 16 23 GIS 24 30 Edge Level IRQ7 IRQ6 IRQ5 IRQ4 GIS24 GIS25 GIS26 GIS27 IRQ3 IRQ2 IRQ1 GIS28 GIS29 GIS30 Bits 24 30 Note...

Page 973: ...25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EM7 IMAP7 EM6 EM5 IMAP6 IMAP5 EM4 IMAP4 EM3 IMAP3 EM2 IMAP2 EM1 IMAP1 EM0 IMAP0 01 Single edge mode 00 Level mode 11 Reserved 10 Second edge detection mode EM 31 0 Edge Mode Selection for LIC Group A IRQs Bits 0 1 4 5 8 9 12 13 16 17 20 21 24 25 28 29 01 Route enabled interrupt through IRQOUTA1 into the PIC 00 Route enabled interrupt throu...

Page 974: ...13 14 15 EM7 IMAP7 EM6 EM5 IMAP6 IMAP5 EM4 IMAP4 EM3 IMAP3 EM2 IMAP2 EM1 IMAP1 EM0 IMAP0 01 Single edge mode 00 Level mode 11 Reserved 10 Second edge detection mode EM 31 0 Edge Mode Selection for LIC Group B IRQs Bits 0 1 4 5 8 9 12 13 16 17 20 21 24 25 28 29 01 Route enabled interrupt through IRQOUTB1 into the PIC 00 Route enabled interrupt through IRQOUTB0 into the PIC 11 Route enabled interrup...

Page 975: ...S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 LICAISR LICBISR Note The S bits reflect the current interrupt status for the specified interrupts Write a one to the bit to clear it Writing a zero has no effect 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LIC Group A B Interrupt Error Status Register ES 31 0 Error Status Bits 0 31 No second edge interr...

Page 976: ... triggered mode PED 7 6 5 4 Trigger Mode for IRQ Input xx Bits 0 4 8 12 PIL70 PED7 PED5 PIL50 PIL51 PIL52 PED4 PIL40 PIL41 PIL42 Interrupt Scheme ELIRA PIC Edge Level Triggered Interrupt Priority Register A Address 0x00F09C00 Reset 0 Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIL22 PIL21 PIL20 PED2 PIL32 PIL31 001 IPL0 lowest priority 000 Interrupts disabled 011 IPL2 IPL3 010 IPL1 101 IPL5 1...

Page 977: ... mode PED 15 14 13 12 Trigger Mode for IRQ Input xx Bits 0 4 8 12 PIL150 PED15 PED13 PIL130 PIL131 PIL132 PED12 PIL120 PIL121 PIL122 Interrupt Scheme ELIRC PIC Edge Level Triggered Interrupt Priority Register C Address 0x00F01C10 Reset 0 Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIL102 PIL101 PIL100 PED10 PIL112 PIL111 001 IPL0 lowest priority 000 Interrupts disabled 011 IPL2 IPL3 010 IPL1 ...

Page 978: ...iggered mode PED 23 22 21 20 Trigger Mode for IRQ Input xx Bits 0 4 8 12 PIL230 PED23 PED21 PIL210 PIL211 PIL212 PED20 PIL200 PIL201 PIL202 Interrupt Scheme ELIRE PIC Edge Level Triggered Interrupt Priority Register E Address 0x00F01C20 Reset 0x4000 Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIL182 PIL181 PIL180 PED18 PIL192 PIL191 001 IPL0 lowest priority 000 Interrupts disabled 011 IPL2 IP...

Page 979: ...P10 IP9 IP8 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 Level Triggered Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IPRB PIC Interrupt Pending Register B Address 0x00F09C38 Reset 0x00 Read Write 1 Interrupt request acknowledged by SC140 core 0 No interrupt request pending Edge Triggered Mode 1 Interrupt request pending 0 No interrupt request pending IP Interrupt Pending Status Bits 0 15 IP31 IP30 IP29 IP28 IP2...

Page 980: ...ck Mode Bit 14 1 Debug mode 0 Normal mode DM Debug Mode Bit 12 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility Instruction Cache Command Register Reset 0x0000 Write Only ICCMR C 3 0 DA 5 0 0000 C Command Bits 0 3 0001 Flush cache 1000 1001 All others Flush cache between boundaries Initialize state registers Clear line defined by DA bits Reserv...

Page 981: ...D BD BD BD PTR1 PTR2 PTR3 PTR4 PTR5 0 RQ NUM0 RQ RQ RQ RQ NUM1 NUM2 NUM3 NUM4 0 0 PRIO1 PRIO2 PRIO3 The channel will ignore level request to EXP 1 bus cycles after the EXP 0 2 Expiration Timer Bits 5 7 assertion of DRACK or DACK signal as defined by DRACK bit 1 DREQ is level triggered 0 DREQ is edge triggered DRS DREQ Sensitivity Mode Bit 8 1 DREQ is active low or falling edge triggered according ...

Page 982: ...n timer starts counting 0 Channel does not use DRACK Expiration timer starts DRACK DRACK Protocol Bit 16 counting after DACK assertion after DRACK assertion 1 Flyby mode Single access transaction 0 Dual access transaction FLY Flyby Transaction Bit 17 1 Channel is frozen 0 Channel operates normally FRZ Freezes Channel Bit 24 00000 Reserved RQNUM 0 4 Requestor Number Bits 19 23 00010 00011 00001 Res...

Page 983: ... 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility I 0 15 Interrupt from DMA Channel Bits 0 15 No interrupt Channel requires interrupt servicing 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I0 I1 I2 I3 I4 I5 I6 I7 DSTR DMA Status Register Reset 0 Read Write I8 I9 I10 I11 I12 I13 I14 I15 Note The I bits reflect the current interrupt status for the respective DMA ...

Page 984: ...126 127 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 BD_ADDR BD_SIZE Buffer Size Bits 32 63 Contains the size of the buffer remaining for transfer BD_SIZE 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 BD_ATTR Buffer Attributes and Temporary Data Bits 64 95 See the BD_ATTR programming sheets BD_ATTR BD_BSIZE Buffer Size Bits 96 127 Co...

Page 985: ...2 NBD3 NBD4 NBD5 0 0 0 0 TSZ0 TSZ1 TSZ2 FLS TC GBL 1 Cyclic address BD_ADDR is restored to original value 0 Sequential address BD_ADDR is incremented CYC Cyclic Address Bit 65 1 Do not increment address after request is serviced 0 Increment address after request is serviced NO_INC Increments Address Bit 68 See Sheet 2 Direct Memory Access BD_ATTR 10 11 Arbitrate for bus mastership with request 101...

Page 986: ... transaction 0 Non global transaction GBL Global Transaction Bit 95 When size reaches zero and CONT is set the next request will call NBD 0 5 Next Buffer Bits 74 79 the buffer pointed to by NBD 1 TC 0 2 value is 111 0 TC 0 2 value is 110 TC Transfer Code Bit 93 1 Read transaction 0 Write transaction RD Read Channel Bit 91 001 Max transfer size is 8 bits TSZ 0 2 Transfer Size Bits 86 88 011 000 010...

Page 987: ...et The user must enable a DMA channel interrupt request CAUTION Enabling a channel in DIMR and DEMR results in undefined system behavior Therefore for each channel enable the interrupt in the DIMR or the DEMR but not both 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility M 0 15 Internal Interrupt Mask Bits 0 15 LIC in...

Page 988: ...ss in PDMTEA Channel in PDMTER 0 No system bus DMA transfer error SDN0 DMA Channel System Bus Error Bit 0 1 Local bus error Error address in LDMTEA Channel in LDMTER 0 No local bus DMA transfer error SDN1 DMA Channel Local Bus Error Bit 1 Reserved Write to 0 for future compatibility 0 0 0 Note Write a one to the bit to clear it Writing a zero has no effect DTEAR DSI Address 0x1D0788 QBus System Bu...

Page 989: ...s from the HDST signals Data structure is from the LEDS field 0 1 HTA driven for 1 1 5 internal bus clock cycles HTA driven for 1 5 2 5 internal bus clock cycles 10 11 DSRFA HTADT RPE SNGLM Single Strobe Mode Bit 3 Dual strobe mode Single strobe mode 0 1 SLDWA Sliding Window Active Bit 0 Sliding window is not active Sliding window is active 0 1 BRSTP Burst Signal Polarity Bit 1 Burst signal is act...

Page 990: ...0 0 0 0 0 0 0 0 0 0 0 0 Value Ignored by DSI BA in BR9 and BR11 respectively 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility AM Address Mask Bits 0 16 Must be set to the same value as the AM field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSI Internal Address Mask Registers 9 and 11 Reset 0 Read Write AM in OR9 in GPCM mode or ...

Page 991: ... 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSI Error Register Reset 0 Read Write OVF DER 0 0 0 0 0 0 0 0 0 0 0 0 at PORESET deassertion from CHIP_ID 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSIDIS DSISTP DSI Stop Bit 0 DSI cannot enter Stop mode DSI can enter Stop mode 0 1 DSIDIS...

Page 992: ...lity 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Stop Control Register Reset 0x00000000 Read Write UART_ SCR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIC_STC GIC Stop Bit 29 Normal GIC operation GIC Stop Mode 0 1 DSI_ GIC_ DSI_STC DSI Stop Bit 30 Normal DSI operation DSI Stop Mode 0 1 UART_STC UART Stop Bit 31 Normal UART operation UART Stop Mode 0 1 STC STC STC SCR DSI Address 0x1BB000 Local Bus Address ___________ See pag...

Page 993: ...31 Read Write SMPVAL Semaphore Value Bits 24 31 If SMPVAL 0 the semaphore is free Any other SMPVAL value indicates that the semaphore is locked and the value is the lock code Each master device should have a unique lock code to indicate which device locked the semaphore If SMPVAL is not zero it is locked The master device that locked it must write a zero to SMPVAL to free the semaphore HSMPR 0 7 H...

Page 994: ...0001 0010 0011 Receive and transmit share frame clock and frame sync The TDM receives on data link and transmits one data link Receive and transmit share frame clock and frame sync The TDM receives two data links and transmits two data links valid only if CTS 1 Reserved Reserved 0100 0101 0110 0111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write CTAS Reserved Reserved...

Page 995: ...nc Edge Bit 30 RSYN sampled on RCLK rising edge RSYN sampled on RCLK falling edge 0 1 RRDO Receive Reversed Data Order Bit 31 First received bit stored as msb in memory First received bit stored as lsb in memory 0 1 RFTL RSTL RFTL Receive First Threshold Level Bit 16 Receive first threshold interrupt is pulse Receive first threshold interrupt is level 0 1 RSTL Receive Second Threshold Level Bit 17...

Page 996: ... Transmit first threshold interrupt is level 0 1 TSTL Receive Second Threshold Level Bit 17 Transmit second threshold interrupt is pulse Transmit second threshold interrupt is level 0 1 1 TFSE TDE or 1 5 TFSE TDE TCLKs 2 TFSE TDE or 2 5 TFSE TDE TCLKs 10 11 TSL Transmit Sync Level Bit 28 TSYN is active on logic 1 TSYN is active on logic 0 0 1 SOL SOE TSO TAO SOE Sync Out Edge Bit 21 TSYN output dr...

Page 997: ...0xE7 232 0x08 R 0x28 R 0x48 R 0x68 R 0x88 R 0xA8 R 0xC8 R 0xE8 R 0x09 10 0x29 42 0x49 74 0x69 106 0x89 138 0xA9 170 0xC9 202 0xE9 234 0x0A R 0x2A R 0x4A R 0x6A R 0x8A R 0xAA R 0xCA R 0xEA R 0x0B 12 0x2B 44 0x4B 76 0x6B 108 0x8B 140 0xAB 172 0xCB 204 0xEB 236 0x0C R 0x2C R 0x4C R 0x6C R 0x8C R 0xAC R 0xCC R 0xEC R 0x0D 14 0x2D 46 0x4D 78 0x6D 110 0x8D 142 0xAD 174 0xCD 206 0xED 238 0x0E R 0x2E R 0x...

Page 998: ...168 0xC7 200 0xE7 232 0x08 R 0x28 R 0x48 R 0x68 R 0x88 R 0xA8 R 0xC8 R 0xE8 R 0x09 10 0x29 42 0x49 74 0x69 106 0x89 138 0xA9 170 0xC9 202 0xE9 234 0x0A R 0x2A R 0x4A R 0x6A R 0x8A R 0xAA R 0xCA R 0xEA R 0x0B 12 0x2B 44 0x4B 76 0x6B 108 0x8B 140 0xAB 172 0xCB 204 0xEB 236 0x0C R 0x2C R 0x4C R 0x6C R 0x8C R 0xAC R 0xCC R 0xEC R 0x0D 14 0x2D 46 0x4D 78 0x6D 110 0x8D 142 0xAD 174 0xCD 206 0xED 238 0x0...

Page 999: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDM 0 3 Transmit Data Buffer Size Reserved Write 0 for future compatibility TDBS Transmit Data Buffer Size Bits 8 31 Value is transmit data buffers size in bytes minus 1 Because the TDM 0 3 TDBS TDBS 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write buffer size is 8 byte aligned bits 29 31 must be set to 111 1 1 1 Note Bits 29 31 are 0s after reset For correct operati...

Page 1000: ...00 Read Write 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write 0 for future compatibility TGBA Transmit Global Base Address Bits 16 31 Value forms the 16 msbs for the transmit data buffers global base TGBA 0 0 0 0 0 0 0 0 address The actual address for each buffer is TCDBA TBGA 16 0 0 0 0 0 0 0 0 TDM 0 3 RGBA TDM 0 3 TGBA TDM_____...

Page 1001: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write 0 0 0 LTS Learn Transmit Sync Bit 31 Adaptation machine learns the receive sync Adaptation machine learns the transmit sync 0 1 TDM_____________ enter number n ACR QBus IPBus Address 0x 01F83FB0 16384 n ______________ Local Bus Address ___________ See page 8 28 DSI Address 0x183FB0 16384 n ______________ AME Adaptation Machine Enable Bi...

Page 1002: ... 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDM 0 3 Transmit Control Registers Reserved Write 0 for future compatibility 0 0 TDM 0 3 TCR TEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write 0 0 0 TEN Transmit Enable Bit 31 Transmitter is disabled Transmitter is enabled 0 1 0 0 TDM 0 3 RCR TDM 0 3 TCR TDM_____________ enter number n RCR QBus IPBus Address 0x01F83FA8 16384 n ____...

Page 1003: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDM 0 3 Transmit Data Buffer First Threshold Reserved Write 0 for future compatibility TDBFT Transmit Data Buffer First Threshold Bits 8 31 Value is transmit data buffer first threshold location Because the TDM 0 3 TDBFT TDBFT 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write register value has a granularity of 8 bytes bits 29 31 must be 000 0 0 0 Note Bits 29 31 are 0s...

Page 1004: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDM 0 3 Transmit Data Buffer Second Threshold Reserved Write 0 for future compatibility TDBST Transmit Data Buffer Second Threshold Bits 8 31 Value is transmit data buffer second threshold location Because the TDM 0 3 TDBST TDBST 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write register value has a granularity of 8 bytes bits 29 31 must be 000 0 0 0 Note Bits 29 31 a...

Page 1005: ...nel Parameter Registers 0 255 Reserved Write 0 for future compatibility TCDBA Transmit Channel Data Buffer Base Address Determines transmit data buffer base address offset from the TGBA TDM 0 3 TCPR 0 255 TCDBA 0 0 0 0 0 Reset Unknown Read Write The TCDBA must be 16 byte aligned so bits 28 31 must be 0000 0 0 0 Note Bits 28 31 are unknown after reset For correct operation you must write 0s to thes...

Page 1006: ... 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDM 0 3 Transmit Interrupt Enable Registers Reserved Write 0 for future compatibility 0 0 TDM 0 3 TIER TSTEE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write TFTEE 0 TFTEE Transmit First Threshold Event Enable Bit 30 Transmit first threshold interrupt disabled Transmit first threshold interrupt enabled 0 1 TSTEE Transmit Second Thresh...

Page 1007: ...30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDM 0 3 Transmit Event Registers Reserved Write 0 for future compatibility 0 0 TDM 0 3 TER TSTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write TFTE 0 TFTE Transmit First Threshold Event Bit 30 No transmit first threshold event occurred Transmit first threshold event occurred 0 1 TSTE Transmit Second Threshold Event Bit 31 N...

Page 1008: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write 0 0 0 AMS Adaptation Machine Status Bit 31 No sync arrived and TDM 0 3 ASDR was not updated Sync arrived and TDM 0 3 ASDR was updated 0 1 TDM_____________ enter number n ACR QBus IPBus Address 0x01F83F30 16384 n ______________ Local Bus Address ___________ See page 8 28 DSI Address 0x 183F30 16384 n ______________ TDM 0 3 ASR 0 Note...

Page 1009: ... modes Note When read these are R 7 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCI Data Direction Register Reserved Write 0 for future compatibility SCIDDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x00000000 Read Write DDRTX 0 0 T8 R8 T 7 0 0 T8 Transmit Bit 8 Bit 17 Write only ninth bit when the SCI is in 9 bit data mode R8 Receive Bit 8 Bit 16 Read...

Page 1010: ...n enabled 0 1 ILT Idle Line Type Bit 21 Idle character bit count begins after start bit Idle character bit count begins after stop bit 0 1 Reserved Write a 0 to all reserved bits for future compatibility Serial Communication Interface SCI TIE PT TCIE PE M Data Format Mode Bit 19 1 start bit 8 data bits 1 stop bit 1 start bit 9 data bits 1 stop bit 0 1 LOOPS Loop Select Bit 16 Normal operation enab...

Page 1011: ...er A0 output signal polarity unchanged TIMER0 Timer A0 output signal polarity inverted 0 1 Reserved Write a 0 to all reserved bits for future compatibility Timers POL4 TOG4 TOG4 TIMER1 Pulse Toggle Bit 25 TIMER1 output toggles TIMER1 output is asserted for one clock 0 1 DIR4 TIMER1 Pin Direction Bit 26 TIMER1 is input TIMER1 is output 0 1 INTP Interrupt Pulse Level Bit 28 Timer A interrupts assert...

Page 1012: ... output signal polarity unchanged TIMER2 Timer A0 output signal polarity inverted 0 1 Reserved Write a 0 to all reserved bits for future compatibility Timers POL4 TOG4 TOG4 TIMER3 Pulse Toggle Bit 25 TIMER3 output toggles TIMER3 output is asserted for one clock 0 1 INTP Interrupt Pulse Level Bit 28 Timer B interrupts asserted for one clock Timer B interrupts are level type 0 1 POL4 TIMER3 Polarity...

Page 1013: ... IE7 TIERB Timer Interrupt Enable Register B Reset 0x000000000 Read Write IE8 IE9 IE10 IE11 IE12 IE13 IE14 IE15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility IE 0 15 Timer A Interrupt Enables Bits 16 31 Timer An interrupt disabled Timer An interrupt enabled 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IE0 IE1 IE2 IE3 IE4 I...

Page 1014: ...LK Timer receives its clock from TDM1RCLK 0000 0001 0010 0011 Timer receives its clock from TDM0TCLK Timer receives its clock from TDM1TCLK Timer receives its clock from the internal BUSES_CLOCK Reserved 0100 0101 0110 0111 Timer receives its clock from the output of timer A8 Timer receives its clock from the output of timer A9 Timer receives its clock from the output of timer A10 Timer receives i...

Page 1015: ...K Timer receives its clock from TDM3RCLK 0000 0001 0010 0011 Timer receives its clock from TDM2TCLK Timer receives its clock from TDM3TCLK Timer receives its clock from the internal BUSES_CLOCK Reserved 0100 0101 0110 0111 Timer receives its clock from the output of timer B8 Timer receives its clock from the output of timer B9 Timer receives its clock from the output of timer B10 Timer receives it...

Page 1016: ...unter value COMPVAL Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPVAL Compare Value Bits 16 31 Contains the value to compare to the counter value COMPVAL TCMPA 0 15 TCMPB 0 15 TCMPA_____________ enter number n QBus IPBus Address 0x01FBF080 8 n ______...

Page 1017: ... 0 0 0 0 0 0 0 0 0 Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TE TE Timer Enable Bit 31 Timer disabled Timer enabled 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRA 0 15 TCRB 0 15 TCRA_____________ enter number n QBus IPBus Address 0x01FBF100 8 n _____________...

Page 1018: ... CF5 CF6 CF7 TERB Timer Event Register B Reset 0 Read Write CF8 CF9 CF10 CF11 CF12 CF13 CF14 CF15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility CF 0 15 Timer A Compare Flags Bits 16 31 Timer An TCMPAn COMPVAL Timer An TCMPAn COMPVAL 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF0 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CF10 C...

Page 1019: ...15 D 31 0 Data Bits 0 31 Pin value is 0 Pin value is 1 0 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 PDIRPin Data Direction Register Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DR 31 0 Direction Bits 0 31 Pin is an input Pin is an output 0 1 DR0 DR1 DR2...

Page 1020: ...2 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 PSORPin Special Options Register Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SO 31 0 Data Bits 0 31 Dedicated peripheral function 1 Dedicated peripheral function 2 0 1 SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17 SO18 SO19 SO20 SO21 SO22 SO23 SO24...

Page 1021: ...ceful stop complete interrupt 0 1 Reserved Write a 0 to all reserved bits for future compatibility Ethernet Controller RXF0 GRSC RXF1 EBERR Ethernet Bus Error Bit 3 No bus error System bus error 0 1 RXC Receive Control Interrupt Bit 1 No control frame Control frame received 0 1 XFUN Transmit FIFO Underrun Bit 15 No underrun Transmit FIFO underrun 0 1 CRL Collision Retry Limit Bit 14 No excessive t...

Page 1022: ...t Enable Bit 7 Disabled Enabled 0 1 GTSCEN Graceful Tx Stop Complete Int En Bit 6 Disabled Enabled 0 1 Reserved Write a 0 to all reserved bits for future compatibility Ethernet Controller RXENF0 GRSCEN RXFEN1 EBERREN Ethernet Bus Error Enable Bit 3 Disabled Enabled 0 1 RXCEN Receive Control Interrupt Enable Bit 1 Disabled Enabled 0 1 XFUNEN Transmit FIFO Underrun Int Enable Bit 15 Disabled Enabled...

Page 1023: ...me Length Bits 25 31 Specifies the smallest packet to place into a receive buffer specified by RxBD MINFLR ECNTRL MINFLR QBus IPBus Address 0x01FB8020 Local Bus Address ___________ See page 8 36 DSI Address 0x1B8020 QBus IPBus Address 0x01FB8024 Local Bus Address ___________ See page 8 36 DSI Address 0x1B8024 0 0 0 0 0 0 0 0 0 0 0 0 AUTOZ STEN CLRCNT CLRCNT Clear All Statistics Counters Bit 17 MST...

Page 1024: ... pause frame if TCTRL TFCP 1 GRS PTV DMACTRL QBus IPBus Address 0x01FB8028 Local Bus Address ___________ See page 8 36 DSI Address 0x1B8028 QBus IPBus Address 0x01FB802C Local Bus Address ___________ See page 8 36 DSI Address 0x1B802C GRS Graceful Receive Stop Bit 27 Stop receiving after current frame Resume receiving frames 0 1 GTS Graceful Transmit Stop Bit 28 Resume transmitting frames Stop tra...

Page 1025: ... DOOS Disable Out of Sequence BD Bit 7 Buffer enabled Buffer disabled 0 1 PCNT Polling Count Bits 4 5 512 clocks 257 clocks 00 01 0 0 0 0 0 0 0 0 0 DOOS DMAMR QBus IPBus Address 0x01FB8038 Local Bus Address ___________ See page 8 36 DSI Address 0x1B8038 0 0 0 0 0 0 PCNT APR BDPR 128 clocks 64 clocks 10 11 APR Alarm Mode Priority Bits 12 13 Low priority Mid priority 00 01 Mid priority High priority...

Page 1026: ...8 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRXSTATR FRXCTRLR QBus IPBus Address 0x01FB8048 Local Bus Address ___________ See page 8 36 DSI Address 0x1B8048 QBus IPBus Address 0x01FB804C Local Bus Address ___________ See page 8 36 DSI Address 0x1B804C 0 0 0 0 0 0 0 0 0 0 0 EMPTY Rx FIFO Empty Bit 30 Rx FIFO not empty...

Page 1027: ... 25 31 Contains the value used to trigger the receive alarm function FRXALAR Reset 0x000000100 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRXSH FIFO Rx Alarm Shutoff Bits 23 31 Contains the value used to turn off the alarm state FRXSH FRXALAR FRXSHR QBus IPBus Address ...

Page 1028: ...c Bits 25 31 Contains the value used to trigger the panic function FRXPA Reset 0x000000100 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRXPS FIFO Rx Panic Shutoff Bits 23 31 Contains the value used to turn off the panic state FRXSH FRXPAR FRXPSR QBus IPBus Address 0x01F...

Page 1029: ...25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTXSTATR FTXTHR QBus IPBus Address 0x01FB8078 Local Bus Address ___________ See page 8 37 DSI Address 0x1B8078 QBus IPBus Address 0x01FB808C Local Bus Address ___________ See page 8 37 DSI Address 0x1B808C 0 0 0 0 0 0 0 0 0 0 0 0 EMPTY Tx FIFO Empty Bit 30 Tx FIFO...

Page 1030: ... 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTXS FIFO Tx Starve Bits 23 31 Contains the value used to trigger the starve function FRXSH FTXSPR FTXSR FTXSSR QBus IPBus Address 0x01FB8094 Local Bus Address ___________ See page 8 37 DSI Address 0x1B8094 QBus IPBus Address 0x01FB8098 Local Bus Address ___________ See page 8 37 DSI Address 0x1B8098 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTXSSR FIF...

Page 1031: ... to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCTRL TSTAT QBus IPBus Address 0x01FB8100 Local Bus Address ___________ See page 8 37 DSI Address 0x1B8100 QBus IPBus Address 0x01FB8104 Local Bus Address ___________ See page 8 37 DSI Address 0x1B8104 0 0 0 0 0 0 0 0 0 0 0 TFCP Tx Flow Control Pause Frame Bit 28 No pause Stop data frame Tx for specified time 0 1 0 0 0 0 0 0 0 0 0 TFCP R...

Page 1032: ...N TxBD Data Length Bits 16 31 Contains a value to define the length of the transmit or insert buffer TBDLEN Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility CTBPTR Current TxBD Pointer Bits 0 28 Contains the pointer to the current TxBD CTBPTR TBDLEN CTBPTR QBus IPBus Address 0x01FB810C Lo...

Page 1033: ...___ See page 8 37 DSI Address 0x1B8204 TBPTR TxBD Pointer Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility TBPTR TxBD Pointer Bits 0 28 Used by the DMA controller to point to the TxBD TBPTR QBus IPBus Address 0x01FB8184 Local Bus Address ___________ See page 8 37 DSI Address 0x1B8184 0 0 ...

Page 1034: ...1 because the OSTBD is always last in frame Reserved Write a 0 to all reserved bits for future compatibility Ethernet Controller W Wrap Bit 2 Next TxBD is consecutive Next TxBD is at user defined location 0 1 R Ready Bit 0 TxBD is not ready for transmission Prepared data buffer is ready being transmitted 0 1 UN Underrun Bit 14 No underrun Transmitter underrun detected 0 1 I Interrupt Bit 3 Do not ...

Page 1035: ...ee page 8 37 DSI Address 0x1B82B8 OSTBDP Out of Sequence Tx Data Buffer Pointer Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility OSTBDP Out of Sequence Tx Data Buffer Pointer Bits 0 31 Contains the address of the associated data buffer OSTBDP QBus IPBus Address 0x01FB82B4 Local Bus Addres...

Page 1036: ... 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility OS32IPTR Out of Sequence Tx Insert Buffer Pointer Bits 0 31 Contains the address of the buffer to contain the inserted data OS32IPTR QBus IPBus Address 0x01FB82C0 Local Bus Address ___________ See page 8 38 DSI Address 0x1B82C0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write t...

Page 1037: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility OS32ILEN Out of Sequence 32 Byte TxBD Insert Length Bits 0 31 Contains the address of the buffer to contain the inserted data OS32ILEN QBus IPBus Address 0x01FB82C8 Local Bus Address ___________ See page 8 38 DSI Address 0x1B82C8 OS32INX Out of Sequence 32 Byte TxBD Insert Index Bits 0 15 Contains the number of bytes ...

Page 1038: ...0 0 BCREJ PROM CRCLSEL BCREJ Broadcast Frame Reject Bit 27 No effect Reject frames with address 0xFFFFFFFFFFFF 0 1 PROM Promiscuous Mode Bit 28 No effect Accept all frames 0 1 RSF Receive Short Frame Mode Bit 29 No effect Rx frames shorter than MINFLR 0 1 FA Reject All Mode Bit 30 No effect No frames accepted for DA hit 0 1 0 0 0 0 0 0 0 0 0 RSF RA CRCLSEL CRC LSB Select Bit 20 Use CRC remainder 0...

Page 1039: ...h Bits 16 31 Contains a value to define the length of the receive buffer Writing a zero stops all receive channels RBDLEN Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility CTBPTR Current RxBD Pointer Bits 0 28 Contains the pointer to the current RxBD CRBPTR RBDLEN CRBPTR QBus IPBus Address...

Page 1040: ...erved Write to 0 for future compatibility 0 0 0 0 0 0 MRBLR2 MRBLR0R1 MRBLR2R3 QBus IPBus Address 0x01FB8340 Local Bus Address ___________ See page 8 38 DSI Address 0x1B8340 QBus IPBus Address 0x01FB8344 Local Bus Address ___________ See page 8 38 DSI Address 0x1B8344 0 0 0 0 0 0 0 0 0 0 0 0 MRBLR3 Maximum Rx Buffer Length Ring 3 Bits 0 9 Specifies the number of writes to buffer ring 3 MRBLR3 MRBL...

Page 1041: ...24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Receive Descriptor Base Address 0 3 Reserved Write 0 for future compatibility RBASEn Receive Descriptor Base Address n Bits 0 28 Value is the starting location for the RxBD memory map RBASE 0 3 RBASEn Reset 0x00000000 Read Write 0 0 0 TDM 0 3 RDBST TDM 0 3 TDBST QBus IPBus Address 0x01FB8384 8 n ______________ Local Bus Address ________...

Page 1042: ...YRXEN Synchronized Rx Enable Bit 28 Frame reception not enabled Frame reception enabled 0 1 RRXF RTXF RRXM RTXM RTXF Reset Tx Function Bit 15 Normal operation Reset the transmit function block 0 1 Reserved Write a 0 to all reserved bits for future compatibility Ethernet Controller MIILB RTXM Reset Tx MAC Bit 13 Normal operation Reset the PETMC transmit control block 0 1 SRESET Soft Reset Bit 0 Nor...

Page 1043: ...cifies the length of the preamble field in bytes PADCRC Padding CRC Bit 29 No padding or CRC MAC pads all Tx short frames and appends CRC 0 1 CRCEN CRC Enable Bit 30 Valid frame and valid CRC Frame and or CRC not valid 0 1 FDUP Full Duplex Bit 31 Half duplex mode Full duplex mode 0 1 LENC Length Check Bit 27 No length field checking MAC checks the frame length field 0 1 MACCFG2R DSI Address 0x1B85...

Page 1044: ...er MIFGE Minimum IFG Enforcement Bits 16 23 The minimum number of bits of the IFG to enforce between NBBIPG2 Non Back to Back Inter Packet Gap 2 Bits 9 15 Represents the non back to back inter packet gap size in bits NBBIPG1 Non Back to Back Inter Packet Gap 1 Bits 1 7 Defines the optional carrier sense window BPIPG Back to Back Interpacket Gap Bits 25 31 The IPG between back to back packets IPGIF...

Page 1045: ...ssively deferred packet Transmit an excessively deferred packet 0 1 Reserved Write a 0 to all reserved bits for future compatibility Ethernet Controller BPNB Back Pressure No Back off Bit 13 Tx MAC uses the binary exponential back off rule No backoff during a back pressure operation 0 1 ABEBT Alternate Binary Exponential Back off Truncation Bits 8 12 A value substituted for the Ethernet standard v...

Page 1046: ...ximum frame size for receive and transmit channels MF Reset 0x000000001 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility EXD Excess Deferral Bit 22 Set to indicate excessive deferral Read bit to clear EXD MAXFRMR IFSTATR QBus IPBus Address 0x01FB8510 Local Bus Address ___________ See page 8 39 DSI Address ...

Page 1047: ...A3 Station Address Octet 3 Bits 16 23 Defines the third octet of the station address SA2 Station Address Octet 2 Bits 8 15 Defines the second octet of the station address SA1 Station Address Octet 1 Bits 0 7 Defines the first octet of the station address SA4 Station Address Octet 4 Bits 24 31 Defines the fourth octet of the station address MACSTADDR1R DSI Address 0x1B8540 Local Bus Address _______...

Page 1048: ... 0x00000000 Read Write Ethernet Controller SA6 Station Address Octet6 Bits 8 15 Defines the second octet of the station address SA5 Station Address Octet 5 Bits 0 7 Defines the first octet of the station address MACSTADDR2R DSI Address 0x1B8544 Local Bus Address ___________ See page 8 39 QBus IPBus Address 0x01FB8544 SA6 SA5 Reserved Write a 0 to all reserved bits for future compatibility 0 0 0 0 ...

Page 1049: ...0 0 0 0 0 0 0 0 0 MIIMCFGR MIIMCOMR QBus IPBus Address 0x01FB8520 Local Bus Address ___________ See page 8 39 DSI Address 0x1B8520 QBus IPBus Address 0x01FB8524 Local Bus Address ___________ See page 8 39 DSI Address 0x1B8524 0 0 0 0 0 0 0 0 0 MGTCS Management Clock Select Bits 29 31 BUSES_CLOCK 4 BUSES_CLOCK 4 000 001 0 0 0 0 0 0 0 0 0 NOPRE No Preamble Bit 27 Preamble generated No preamble 0 1 R...

Page 1050: ... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIIMADDR MIIMCONR QBus IPBus Address 0x01FB8528 Local Bus Address ___________ See page 8 39 DSI Address 0x1B8528 QBus IPBus Address 0x01FB852C Local Bus Address ___________ See page 8 39 DSI Address 0x1B852C 0 0 0 0 0 0 RADDR Register Address Bits 27 31 Management cycle register addres...

Page 1051: ...0 0 0 0 0 0 MIIGSK_CFGR MIIGSK_GPR QBus IPBus Address 0x01FB9000 Local Bus Address ___________ See page 8 46 DSI Address 0x1B9000 QBus IPBus Address 0x01FB9004 Local Bus Address ___________ See page 8 46 DSI Address 0x1B9004 0 0 0 0 0 0 0 IFMODE Interface Mode Bits 30 31 MII mode RMII mode 00 01 0 0 0 0 0 0 0 0 0 EMODE Echo Mode Bit 28 Normal operation MII inputs looped to Tx outputs 0 1 FRCONT Fr...

Page 1052: ... 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIIGSK_ENR MIIGSK_SMII_SYNCDIR QBus IPBus Address 0x01FB9008 Local Bus Address ___________ See page 8 46 DSI Address 0x1B9008 QBus IPBus Address 0x01FB900C Local Bus Address ___________ See page 8 46 DSI Address 0x1B900C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN Enable Bit 31 Ethernet controller disabled Ethernet controller...

Page 1053: ...0 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIIGSK_TIFBR MIIGSK_ERIFBR QBus IPBus Address 0x01FB9010 Local Bus Address ___________ See page 8 46 DSI Address 0x1B9010 QBus IPBus Address 0x01FB9018 Local Bus Address ___________ See page 8 46 DSI Address 0x1B9018 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXD0 TXD 7 0 IFG Transmit Segme...

Page 1054: ...22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIIGSK_IEVENT MIIGSK_IMASK QBus IPBus Address 0x01FB901C Local Bus Address ___________ See page 8 46 DSI Address 0x1B901C QBus IPBus Address 0x01FB9020 Local Bus Address ___________ See page 8 47 DSI Address 0x1B9020 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IE0 IE...

Page 1055: ...ead Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TR64 TR127 QBus IPBus Address 0x01FB8680 Local Bus Address ___________ See page 8 40 DSI Address 0x1B8680 QBus IPBus Address 0x01FB8684 Local Bus Address ___________ See page 8 40 DSI Address 0x1B8684 0 0 TR64 Tx and Rx 64 Byte Frame Counter...

Page 1056: ...Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TR255 TR511 QBus IPBus Address 0x01FB8688 Local Bus Address ___________ See page 8 40 DSI Address 0x1B8688 QBus IPBus Address 0x01FB868C Local Bus Address ___________ See page 8 40 DSI Address 0x1B868C 0 0 TR255 Tx and Rx 128 to 255 Byte Frame C...

Page 1057: ...ite 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TR1K TRMAX QBus IPBus Address 0x01FB8690 Local Bus Address ___________ See page 8 40 DSI Address 0x1B8690 QBus IPBus Address 0x01FB8694 Local Bus Address ___________ See page 8 40 DSI Address 0x1B8694 0 0 TR1K Tx and Rx 512 to 1023 Byte Frame Coun...

Page 1058: ...0 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility TRMGV RBYT QBus IPBus Address 0x01FB8698 Local Bus Address ___________ See page 8 40 DSI Address 0x1B8698 QBus IPBus Address 0x01FB869C Local Bus Address ___________ See page 8 40 DSI Address 0x1B869C 0 0 TRMGV Tx and Rx 1519 to 1522 Byte VLAN Frame Counte...

Page 1059: ... 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility RPKT RFCS QBus IPBus Address 0x01FB86A0 Local Bus Address ___________ See page 8 40 DSI Address 0x1B86A0 QBus IPBus Address 0x01FB86A4 Local Bus Address ___________ See page 8 40 DSI Address 0x1B86A4 0 0 RPKT Receive Packet Counter Bits 10 31 The RMON MIB counter that counts the number of frame recei...

Page 1060: ...22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 RMCA RBCA QBus IPBus Address 0x01FB86A8 Local Bus Address ___________ See page 8 40 DSI Address 0x1B86A8 QBus IPBus Address 0x01FB86AC Local Bus Address ___________ See page 8 40 DSI Address 0x1B86AC 0 0 RMCA Rx Multicast Packet Counter Bits 10 31 The RMON MIB counter ...

Page 1061: ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 RXCF RXPF QBus IPBus Address 0x01FB86B0 Local Bus Address ___________ See page 8 40 DSI Address 0x1B86B0 QBus IPBus Address 0x01FB86B4 Local Bus Address ___________ See page 8 40 DSI Address 0x1B86B4 0 0 RXCF Rx Control Frame Packet Counter Bits 10 31 The ...

Page 1062: ...1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 RXUO RALN QBus IPBus Address 0x01FB86B8 Local Bus Address ___________ See page 8 40 DSI Address 0x1B86B8 QBus IPBus Address 0x01FB86BC Local Bus Address ___________ See page 8 40 DSI Address 0x1B86BC 0 0 RXUO Rx Unknown Opcode Packet Counter Bits 16 31 The RMON MIB counter that counts the number ...

Page 1063: ... 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 RFLR RCDE QBus IPBus Address 0x01FB86C0 Local Bus Address ___________ See page 8 40 DSI Address 0x1B86C0 QBus IPBus Address 0x01FB86C4 Local Bus Address ___________ See page 8 40 DSI Address 0x1B86C4 0 0 RFLR Rx Frame Length Error Counter Bits 16 31 The RMON MIB counter that counts the number of frames in whi...

Page 1064: ...6 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 RCSE RUND QBus IPBus Address 0x01FB86C8 Local Bus Address ___________ See page 8 40 DSI Address 0x1B86C8 QBus IPBus Address 0x01FB86CC Local Bus Address ___________ See page 8 41 DSI Address 0x1B86CC 0 0 RCSE Rx Carrier Sense Error Counter Bits 16 31 The RMON MIB counter that count...

Page 1065: ...7 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 ROVR RFRD QBus IPBus Address 0x01FB86D0 Local Bus Address ___________ See page 8 41 DSI Address 0x1B86D0 QBus IPBus Address 0x01FB86D4 Local Bus Address ___________ See page 8 41 DSI Address 0x1B86D4 0 0 ROVR Rx Oversize Packet Counter Bits 16 31 The RMON MIB counter that counts the n...

Page 1066: ... 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 RJBR RDRP QBus IPBus Address 0x01FB86D8 Local Bus Address ___________ See page 8 41 DSI Address 0x1B86D8 QBus IPBus Address 0x01FB86DC Local Bus Address ___________ See page 8 41 DSI Address 0x1B86DC 0 0 RJBR Rx Jabber Counter Bits 16 31 The RMON MIB counter that counts the number of oversiz...

Page 1067: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TBYT TPKT QBus IPBus Address 0x01FB86E0 Local Bus Address ___________ See page 8 41 DSI Address 0x1B86E0 QBus IPBus Address 0x01FB86E4 Local Bus Address ___________ See page 8 41 DSI Address 0x1B86E4 0 0 TBYT Tx Byte Counter Bits 1 31 The RMON MIB counter t...

Page 1068: ...20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TMCA TBCA QBus IPBus Address 0x01FB86E8 Local Bus Address ___________ See page 8 41 DSI Address 0x1B86E8 QBus IPBus Address 0x01FB86EC Local Bus Address ___________ See page 8 41 DSI Address 0x1B86EC 0 0 TMCA Tx Multicast Packet Counter Bits 10 31 The RMON MIB co...

Page 1069: ...7 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TXPF TDFR QBus IPBus Address 0x01FB86F0 Local Bus Address ___________ See page 8 41 DSI Address 0x1B86F0 QBus IPBus Address 0x01FB86F4 Local Bus Address ___________ See page 8 41 DSI Address 0x1B86F4 0 0 TXPF Tx Pause Frame Packet Counter Bits 16 31 The RMON MIB counter that counts th...

Page 1070: ... 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TEDF TSCL QBus IPBus Address 0x01FB86F8 Local Bus Address ___________ See page 8 41 DSI Address 0x1B86F8 QBus IPBus Address 0x01FB86FC Local Bus Address ___________ See page 8 41 DSI Address 0x1B86FC 0 0 TEDF Tx Excessive Deferral Packet Counter Bits 20 31 The RMON MIB counter that counts th...

Page 1071: ... 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TMCL TLCL QBus IPBus Address 0x01FB8700 Local Bus Address ___________ See page 8 41 DSI Address 0x1B8700 QBus IPBus Address 0x01FB8704 Local Bus Address ___________ See page 8 41 DSI Address 0x1B8704 0 0 TMCL Tx Multiple Collision Packet Counter Bits 20 31 The RMON MIB counter that cou...

Page 1072: ... 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TXCL TNCL QBus IPBus Address 0x01FB8708 Local Bus Address ___________ See page 8 41 DSI Address 0x1B8708 QBus IPBus Address 0x01FB870C Local Bus Address ___________ See page 8 41 DSI Address 0x1B870C 0 0 TXCL Tx Excessive Collision Packet Counter Bits 20 31 The RMON MIB counter that count...

Page 1073: ... 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TDRP TJBR QBus IPBus Address 0x01FB8718 Local Bus Address ___________ See page 8 41 DSI Address 0x1B8718 0 TJBR Tx Jabber Frame Counter Bits 20 31 The RMON MIB counter that counts the total number of oversized transmitted frames with an incorrect FCS value TJBR 0 0 0 0 0 0 0 0 0 0 ...

Page 1074: ...5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TFCS TXCF QBus IPBus Address 0x01FB871C Local Bus Address ___________ See page 8 41 DSI Address 0x1B871C QBus IPBus Address 0x01FB8720 Local Bus Address ___________ See page 8 41 DSI Address 0x1B8720 0 0 TFCS Tx FCS Error Counter Bits 20 31 The RMON MIB counter that counts the number of transmit packet with ...

Page 1075: ...6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TOVR TUND QBus IPBus Address 0x01FB8724 Local Bus Address ___________ See page 8 41 DSI Address 0x1B8724 QBus IPBus Address 0x01FB8728 Local Bus Address ___________ See page 8 41 DSI Address 0x1B8728 0 0 TOVR Tx Oversize Frame Counter Bits 20 31 The RMON MIB counter that counts the number of oversized transmit...

Page 1076: ...25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 0 0 0 0 TFRG QBus IPBus Address 0x01FB872C Local Bus Address ___________ See page 8 42 DSI Address 0x1B872C 0 TFRG Tx Fragment Counter Bits 20 31 The RMON MIB counter that counts the total number of frames less than 64 bytes with an incorrect FCS value TFRG 0 0 0 0 0 0 0 0 0 0 ...

Page 1077: ... IPBus Address 0x01FB8730 C1RDR C1RJB C1RUN C1ROV C1RFR C1RCS C1RCD C1RAL C1RFL C1RXU C1RXP C1RMC C1RBC C1RXC C1RFC C1RPK C1MAX C1MGV C1RBY C1RBC CAR1 RBCA Carry Bit 19 No carry Carry 0 1 C1RXC CAR1 RXCF Carry Bit 20 No carry Carry 0 1 C1RXP CAR1 RXPF Carry Bit 21 No carry Carry 0 1 C1RMC CAR1 RMCA Carry Bit 18 No carry Carry 0 1 C1RBY CAR1 RBYT Carry Bit 15 No carry Carry 0 1 C1RPK CAR1 RPKT Carr...

Page 1078: ...TBC C2TBY C2TPK C2TMC C2TFG C2TUN C2TFC C2CTF C2TOV C2TPK CAR2 TPKT Carry Bit 19 No carry Carry 0 1 C2TMC CAR2 TMCA Carry Bit 20 No carry Carry 0 1 C2TBC CAR2 TBCA Carry Bit 21 No carry Carry 0 1 C2TBY CAR2 TBYT Carry Bit 18 No carry Carry 0 1 C2TOV CAR2 TOVR Carry Bit 15 No carry Carry 0 1 C2TUN CAR2 TUND Carry Bit 16 No carry Carry 0 1 C2TFG CAR2 TFRG Carry Bit 17 No carry Carry 0 1 C2TPF CAR2 T...

Page 1079: ...UN M1ROV M1RFR M1RCS M1RCD M1RAL M1RFL M1RXU M1RXP M1RMC M1RBC M1RXC M1RFC M1RPK M1MAX M1MGV M1RBY M1RBC CAR1 RBCA Carry Mask Bit 19 Not masked Masked 0 1 M1RXC CAR1 RXCF Carry Mask Bit 20 Not masked Masked 0 1 M1RXP CAR1 RXPF Carry Mask Bit 21 Not masked Masked 0 1 M1RMC CAR1 RMCA Carry Mask Bit 18 Not masked Masked 0 1 M1RBY CAR1 RBYT Carry Mask Bit 15 Not masked Masked 0 1 M1RPK CAR1 RPKT Carry...

Page 1080: ...OV M2TPK CAR2 TPKT Carry Mask Bit 19 Not masked Masked 0 1 M2TMC CAR2 TMCA Carry Mask Bit 20 Not masked Masked 0 1 M2TBC CAR2 TBCA Carry Mask Bit 21 Not masked Masked 0 1 M2TBY CAR2 TBYT Carry Mask Bit 18 Not masked Masked 0 1 M2TOV CAR2 TOVR Carry Mask Bit 15 Not masked Masked 0 1 M2TUN CAR2 TUND Carry Mask Bit 16 Not masked Masked 0 1 M2TFG CAR2 TFRG Carry Mask Bit 17 Not masked Masked 0 1 M2TPF...

Page 1081: ...gister IADDR Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility GADDR Group Address Bits 0 31 Contains the value used to generate a pointer to the group address hash table GADDR IADDR 0 7 GADDR 0 7 IADDR_____________ enter number n QBus IPBus Address 0x01FB8800 4 n ______________ Local Bus ...

Page 1082: ... PMD Reset 0x000000000 Read Write 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility PMASK Pattern Mask Data Bits 0 31 Contains the 32 bit mask used for pattern matching PMASK PMD 0 15 PMASK 0 15 PMD_____________ enter number n QBus IPBus Address 0x01FB8900 32 n ______________ Local Bus Address ___________ See page 8 4...

Page 1083: ... match 00 01 CP Concatenated Pattern Bit 25 No pattern concatenation Concatenate following pattern to current one 0 1 0 0 0 0 0 MI PCNTRL 0 15 PCNTRL_____________ enter number n QBus IPBus Address 0x01FB8910 32 n ______________ Local Bus Address ___________ See page 8 42 DSI Address 0x1B8910 32 n ______________ Ethernet Controller PMC Pattern match accept Pattern match reject 10 11 MI Matching Ind...

Page 1084: ...ler QC Queue 2 Queue 3 10 11 RDSEN Rx Data Snoop Enable Bit 24 Disables snooping of all rx frame data Enables snooping of all rx frame data 0 1 0 0 0 0 0 PMF Pattern Match File Bit 22 Use DATTR QC to file matched frame Use PATTRB QC to file matched frame 0 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Write to 0 for future compatibility 0 0 0 0 0 ...

Page 1085: ...r also performs compare or test operations and arithmetic and logical shifts The offset values added in this adder are pre shifted by 1 2 or 3 according to the access width In reverse carry mode the carry propagates in the opposite direction A second full adder called a modulo adder adds the summed result of the first full adder to a modulo value M or minus M where M is stored in the selected modi...

Page 1086: ...write separately but it signals the memory system that it is attempting an atomic operation If the operation fails status is kept so that MSC8113 can try again Ax Address bus signals A 0 31 for the external system bus BADDRx Burst address signal BADDR 27 31 These five burst address pins are outputs of the SIU memory controller They connect directly to burstable memory devices bandwidth A measure o...

Page 1087: ...ng clearing changing or testing a destination according to an immediate operand All bit manipulation instructions typically execute in two cycles and work on 16 bit data This data can be a memory location or a portion high or low of a register Only a single bit manipulation instruction is allowed in any single execution set since only one execution unit exists for these instructions BMx Boot mode ...

Page 1088: ...r message BUFCMD Command buffers bufferdescriptor BD Each DMA channel uses the specifications in its associated buffer descriptors to define operation of the channel burst A multiple beat data transfer in the MSC8113 whose total size is equal to 32 bytes or 4 data beats at 8 bytes per beat CAM Content addressable memory CCITT Consultative Committee on International Telegraphy and Telephony CHIP_ID...

Page 1089: ... MSC8113 to maintain data bus tenure DBG Data bus grant signal The MSC8113 asserts this pin as an output to grant data bus ownership to an external bus master The external arbiter asserts this pin as an input to grant data bus ownership to the MSC8113 DBRx Data area Registers 0 3 DCHCRx DMA Channel 0 15 Configuration Registers DCIR DSP chip ID register DCPRAM DMA Channel Parameters RAM DCR DSI Con...

Page 1090: ...ntroller enables hot swap between channels by time multiplexed channels with no cost in clock cycles Sixteen priority levels support synchronous and asynchronous transfers on the bus and give a varying bus bandwidth per channel The DMA controller can service multiple requestors A requestor can be any one of four external peripherals or sixteen internal requests generated by the DMA FIFO itself See...

Page 1091: ...external peripheral to request DMA service from the specified channel DSI Direct Slave Interface DSI64 DSI size select 32 64 bits signal DSISYNC Indicates the DSI mode of operation as Synchronous or Asynchronous Mode DSP Digital signal processor DSR DSI Status Register DSTR DMA Status Register DSWBAR DSI Sliding Window Base Address Register DTEAR DMA Transfer Error Address Status Register Dx Data ...

Page 1092: ...nt Selector Mask Debug Mode Register ESP Exception stack pointer ETB End of block ETX End of text character EVM Evaluation module EXT_BGx External bus grant signals EXT_BG 2 3 Used to grant bus mastership to the requesting bus master EXT_BRx External bus request signal EXT_BR 2 3 Used by an external master to request bus mastership EXT_DBGn External data bus grant signal EXT_DBG 2 3 Used to grant ...

Page 1093: ... the MSC8113 flyby transactions can occur only between external peripherals and external memories located on the 60x compatible system bus Flyby operations do not require access to the DMA FIFO See also DMA FU Fetch unit full duplex Transmission in two directions simultaneously that is simultaneous two way communications Such communications occur on four wire circuits In contrast half duplex commu...

Page 1094: ...se Registers 0 1 GUI Graphical user interface HAx DSI host address line signal HA 11 29 half word For the 16 bit SC140 core a half word is 8 bits For the 60x compatible bus a half word is 16 bits HBCS Host Broadcast Chip Select DSI chip select for broadcast mode Enables more than one DSI to share the same host chip select pin for broadcast write accesses HBRST Host Burst The host asserts this pin ...

Page 1095: ...signals HWBE 4 7 HWBSx DSI write byte strobe signals HWBS 0 7 Hz Hertz ICache Instruction Cache ICACR Instruction Cacheable Area Control Register ICBR Instruction Cacheable Area Base Register ICCMR ICache Command Register ICCR ICache Control Register ID Identification Register IDE Integrated development environment IEEE Institute of Electrical and Electronics Engineers IFUR Instruction FU Configur...

Page 1096: ...orresponding to the highest priority unmasked pending interrupt ITU International Telecommunication Union IU Integer unit JTAG Joint Test Action Group JTAGID JTAG Identification ID Register KB Kilobyte Kb Kilobit Kbps Kilobits per second KHz Kilohertz lane A sub grouping of signals within a bus An 8 bit section of the address or data bus may be referred to as a byte lane for that bus L_TESCR1 Loca...

Page 1097: ...ICBICRn LIC Group B Interrupt Configuration Registers 0 3 LICBIER LIC Group B Interrupt Enable Register LICBIESR LIC Group B Interrupt Error Status Register LICBISR LIC Group B Interrupt Status Register little endian For little endian scalars the least significant byte LSB is stored at the lowest or starting address This is called little endian because the little end of the scalar comes first in m...

Page 1098: ...t can be enabled or disabled through software master The device that owns the address or data bus the device that initiates or requests the transaction Mb Megabit MB Megabyte MBMR Machine B Mode Register MBS Maximum burst size MCMR Machine C Mode Register MCP Machine check interrupt signal MCTL Modifier Control Register MDR Memory Data Register memory controller A unit whose main function is to co...

Page 1099: ...caler Register MPU Microprocessor unit MQBus Memory bus for the QBus connecting the SC140 cores to the M2 shared memory and Boot ROM msb Most significant bit MSB Most significant byte Multi Master Bus Mode The multi master bus mode can include one or more potential bus masters external to the MSC8113 The other bus masters can for example be ASIC DMAs high end PowerQUICC IIs or other MSC8113 device...

Page 1100: ... operation and combination of operands to the central processing unit CPU ORx Option Registers 0 7 9 11 The definitions depend on the mode used SDRAM GPCM or UPM PAG SC140 core program address generator PAR Pin Assignment Register parameter RAM The CPM maintains a section of RAM called the parameter RAM which contains many parameters for the operation of the FCCs SCCs SMCs SPI and I2 C channels Th...

Page 1101: ...PIC not only handles incoming interrupts from internal and external devices but also generates interrupts to other devices This capability enables the MSC8113 to be used as a companion chip complementing an external CPU such as a 60x compatible processor For example the MSC8113 might be used to provide protocol handling services sending an interrupt to notify the central processor each time it fin...

Page 1102: ...ster bus masters 0 7 PPC_ALRL Bus Arbitration Level Register bus masters 8 15 PS Port size PSDA10 Bus SDRAM A10 signal PSDAMUX Bus SDRAM address multiplexer signal PSDCAS Bus SDRAM column address strobe PSDDQMx Bus SDRAM DQM signals PSDDQM 0 7 PSDMR Bus SDRAM Mode Register PSDRAS Bus SDRAM row address strobe signal PSDVAL Data valid signal Indicates that a valid data beat is on the data bus It mus...

Page 1103: ...peration RCLK Receive clock RDBS Receive data buffer size requestor An external peripheral or an internal request generated by the DMA FIFO A peripheral interfaces with the DMA by placing a request for service The request can be external or internal depending on its origin reset A means to bring a device and its components to a known state by setting the registers and control bits to predetermined...

Page 1104: ...ite of clear The term set can also more generally describe the updating of a bit or bit field SIMM Signed immediate value Single Master Bus Mode This mode uses the MSC8113 memory controller as the only 60x compatible bus master to connect external devices to the bus In single master bus mode the MSC8113 uses the address bus as a memory address bus Slaves cannot use the 60x compatible system bus si...

Page 1105: ...the QBus connecting the SC140 cores to the system bus local bus and IPBus SR Status Register SRAM Static random access memory Contrast with dynamic random access memory DRAM The dynamic nature of the circuits for DRAM require data to be written back after being read hence the difference between the access time and the cycle time and also the need to refresh SRAMs use more circuits per bit to preve...

Page 1106: ...nsfers eight words TCn Transfer code signals TC 0 2 TCFRAn Timer Configuration Registers A TCFRBn Timer Configuration Registers B TCK Test clock signal for the TAP TCMPAx Timer Compare Registers A 0 15 TCMPBx Timer Compare Registers B 0 15 TCNRAx Timer Count Register A 0 15 TCNRBx Timer Count Register B 0 15 TCRAx Timer Control Registers A 0 15 TCRBx Timer Control Registers B 0 15 TDI Test data in...

Page 1107: ...ceive Interface Registers TDMxRNB TDM 0 3 Receive Number of Buffers TDMxRSR TDM 0 3 Receive Status Registers TDMxRSYN TDM 0 3 receive sync signals TDM0RSYN TDM3RSYN TDMxTCLK TDM 0 3 transmit clocks TDM0TCLK TDM3TCLK TDMxTCPR_n TDM 0 3 Transmit Channel Parameter Register n TDMxTCR TDM 0 3 Transmit Control Registers TDMxTDAT TDM 0 3 transmit data signals TDM0TDAT TDM3TDAT TDMxTDBDR TDM 0 3 Transmit ...

Page 1108: ...Event Register B TESCRx System Bus Transfer Error Status and Control Register 1 2 TGCRx Timer General Configuration Registers A and B TIERx Timer Interrupt Enable Registers A and B TIMERx Timer signals TIMER 0 3 TMCLK Timer clock signal TMCNT Time Counter Register TMCNTAL Time Counter Alarm Register TMCNTSC Time Counter Status and Control Register TMS Test mode select signal for the TAP transactio...

Page 1109: ...refresh timers and generation of programmable control signals for row address and column address strobes to allow for a glueless interface to DRAMs burstable SRAMs and almost any other kind of peripheral The UPM can generate different timing patterns for the control signals that govern a memory device These patterns define how the external control signals behave during a read write burst read or b...

Page 1110: ...fferent speeds so that they seem to be operating at the same speed WARA Write after read atomic bus operation WB Write buffer WBCR Write Back Control Register WBFR Write Back Flush Register word The MSC8113 DSP core is a 16 bit processor so a word in the core portion of the MSC8113 is 16 bits For the SIU portion of the MSC8113 device a word equals 32 bits XDBA Internal SC140 core memory data bus 1...

Page 1111: ...R equ 3c02 IFUR_ADDR equ 00f0ff60 WBCR_ADDR equ 00f0ff82 BASE_QBUS_8 ELIRA equ 1c00 ELIRD equ 1c18 ELIRF equ 1c28 IPRB equ 1c38 IPRB_ADDR equ 00f09c38 LICAICR1 equ 2c08 LICAICR2 equ 2c10 LICAICR3 equ 2c18 LICBICR0 equ 2c40 LICBICR1 equ 2c48 LICBICR2 equ 2c50 LICAISR equ 2c28 LICBISR equ 2c68 LICBIER equ 2c60 EONCE EE_CTRL equ effe18 SIU Registers according to IMMR ISB r6 10000 SIUMCR equ 0 PPC_ACR...

Page 1112: ... 1028 ETH MACCFG2 equ 3afc DMA_MR equ 3fc8 MIIMCFG equ 3ae0 BASE_IP_8 TDM3 Receive Transmit General Interface Register TDM3GIR equ 3ff8 TDMX Receive Transmit Interface Registers TDM3RIR equ 3ff0 TDM3TIR equ 3fe8 TDM3 Receive Transmit Frame Parametera according to the adaption procedure TDM3RFP equ 3fe0 TDM3TFP equ 3fd8 TDM3 Recieve Transmit Data Buffer size TDM3RDBS equ 3fd0 TDM3TDBS equ 3fc8 TDM3...

Page 1113: ...ister TDM3RSR equ 3f28 TDM3TSR equ 3f20 LOGIC STATE defines by state2equ script LOGIC_STATE_1 equ 7972 LOGIC_STATE_1_T equ 797A LOGIC_STATE_2_1 equ 7992 LOGIC_STATE_2_1_T equ 799E LOGIC_STATE_2_2 equ 79A8 LOGIC_STATE_2_2_T equ 79B4 LOGIC_STATE_2_3 equ 79BE LOGIC_STATE_2_3_T equ 79CA LOGIC_STATE_3 equ 79D4 LOGIC_STATE_3_T equ 79EC LOGIC_STATE_4 equ 79FA LOGIC_STATE_4_T equ 7A0A LOGIC_STATE_5 equ 7A...

Page 1114: ...x0200000 2M ISBSEL r6 for holding the IMMR ISB r7 BASE_QBUS_C equ 00f0c000 P 01077000 org p 0000 BASE_ROM_ADDRESS start P 01077000 31 move l BASE_EXEPTION_TABLE vba init vba 63 30 00 81 07 initilize EE1 pin to acknowledge debug P 01077006 20 move w fff7 d0 E0 9F F7 P 0107700A 00 move w d0 EE_CTRL E0 3E 18 80 EF initilize QBUS bank 1 mask register init r7 to BASE_QBUS and BASE_IP P 01077010 3F move...

Page 1115: ...81 FB P 01077048 3B move l BASE_IP r3 00 20 00 81 F8 initialize LIC TDM Interrupts to edge P 0107704E 30 move l 44044044 d0 48 20 44 84 04 P 01077054 00 move l d0 r4 LICAICR1 A4 8C 08 P 01077058 DC lsrr 4 d0 04404404 d0 24 P 0107705A 00 move l d0 r4 LICAICR2 A4 8C 10 P 0107705E 30 move l 40440440 d0 08 24 40 80 44 P 01077064 00 move l d0 r4 LICAICR3 A4 8C 18 initialize LIC TIMERS Interrupts to edg...

Page 1116: ...r F P 0107708A C0 move w 0008 d0 88 P 0107708C 00 move w d0 r4 ELIRF 04 9C 28 P 01077090 89 bra Fmain_cont_2 49 i2c_txrx_byte P 01077092 6F clr d6 10 P 01077094 24 move w 80 d4 00 80 80 byte_loop P 01077098 23 bsr i2c_txrx_bit 18 80 6C P 0107709C 92 ift rts C2 9F 71 P 010770A0 76 asr d4 d4 44 P 010770A2 6F asl d6 d6 5E P 010770A4 66 tsteq d4 69 P 010770A6 85 bf byte_loop F3 P 010770A8 0A bmchg 1 d...

Page 1117: ...P 010770DE 74 tfr d2 d1 D2 P 010770E0 85 bf loop_sample F1 P 010770E2 9F rts 71 i2c_assert_stop P 010770E4 6E clr d4 10 P 010770E6 6F clr d6 10 P 010770E8 6F clr d7 90 P 010770EA 23 bsr i2c_txrx_bit 18 80 1A P 010770EE 92 ift rts C2 9F 71 P 010770F2 34 move w d8 r9 A0 A0 00 40 11 P 010770F8 88 bra wait_sda_high C5 overflow exeption offset 0x100 P 01077100 org p 0100 BASE_EXEPTION_TABLE overflow_ex...

Page 1118: ... move w SCL_SDA_01 d1 C3 21 40 80 00 P 01077126 34 move w d1 r9 80 A0 00 41 11 P 0107712C 34 tfr d15 d0 00 A8 00 74 57 lperiod_loop_2 P 01077132 64 deceq d0 6D P 01077134 85 bf lperiod_loop_2 FF P 01077136 09 or SCL_SDA_10 d1 l 81 A0 00 P 0107713A C8 move l d1 r0 41 P 0107713C 34 move w d1 r9 80 A0 00 41 11 wait_scl_high P 01077142 83 bsr i2c_sample_gpio 83 P 01077144 35 and SCL_SDA_11 d2 d3 DB 80...

Page 1119: ...716A 71 cmpeq d3 d2 63 P 0107716C 90 nop C0 P 0107716E 92 ift rts C2 9F 71 P 01077172 34 cmpeq d8 d2 00 A8 00 71 60 P 01077178 90 nop C0 P 0107717A 94 ift bmset 1 d6 l C2 09 06 A0 01 P 01077180 64 deceq d0 6D P 01077182 85 bf hperiod_loop D9 P 01077184 0C bmtstc 1 d7 l 07 A0 01 P 01077188 90 nop C0 P 0107718A 92 iff rts C3 9F 71 P 0107718E 0C bmtstc 1 d6 l 06 A0 01 P 01077192 C8 move l r0 d1 49 P ...

Page 1120: ... 64 deceq d0 6D P 010771B8 85 bf start_loop F7 start_rts P 010771BA 9F rts 71 wait_sda_high P 010771BC 83 bsr i2c_sample_gpio 09 P 010771BE 0C bmtstc SCL_SDA_01 d2 l 42 A0 00 P 010771C2 81 bt wait_sda_high FB P 010771C4 20 move w BUF_TIME d0 00 80 42 stop_loop P 010771C8 2B bsr i2c_sample_gpio FF 9E FD P 010771CC 0C bmtstc SCL_SDA_01 d2 l 42 A0 00 P 010771D0 80 bt stop_rts 07 P 010771D2 64 deceq d...

Page 1121: ...ift moveu w f0f0 d1 l C2 19 E1 B0 F0 P 010771F8 D2 cmpeq w 2 d5 A2 P 010771FA 90 nop C0 P 010771FC 94 ift moveu w ff00 d1 l C2 19 E1 BF 00 P 01077202 D2 cmpeq w 3 d5 A3 P 01077204 90 nop C0 P 01077206 94 ift moveu w fff0 d1 l C2 19 E1 BF F0 P 0107720C D2 cmpeq w 6 d5 A6 P 0107720E 90 nop C0 P 01077210 94 ift moveu w 0f00 d1 l C2 19 01 AF 00 P 01077216 D2 cmpeq w 7 d5 A7 P 01077218 90 nop C0 P 0107...

Page 1122: ... 00 P 0107723C C2 move w 0020 d2 2M gap A0 P 0107723E 68 imac d2 d5 d1 d1 d5 l d2 l d1 89 P 01077240 D8 aslw d1 d1 d1 16 91 P 01077242 CD move l d1 r5 keep base address of bank 11 in r5 41 P 01077244 D2 cmpeq w 0 d4 20 P 01077246 80 bt Fmain_core0 CD wait_virq P 01077248 20 move w 0500 d0 00 85 00 P 0107724C 00 move l d0 r4 ELIRD 84 9C 18 P 01077250 30 move l 00200000 d0 00 20 00 80 20 P 01077256 ...

Page 1123: ...7282 90 nop C0 P 01077284 00 move l d0 r4 LICBISR A4 8C 68 P 01077288 6C clr d0 10 P 0107728A 00 move l d0 r4 ELIRD 84 9C 18 P 0107728E 00 move l d0 r4 LICBIER A4 8C 60 P 01077292 35 move l 00e40000 sr 03 20 00 80 E4 P 01077298 90 nop C0 P 0107729A D2 cmpeq w 0 d4 20 P 0107729C 80 bt wake_core123_soft_reset 4D P 0107729E 88 bra boot_jmp0 65 wake_core123 P 010772A0 36 bmtstc 0010 d11 h 20 A0 00 0C ...

Page 1124: ...0772C8 19 moveu w f003 d0 l E0 B0 03 P 010772CC 00 move w d0 r0 ICCR 20 9C 00 P 010772D0 90 nop C0 P 010772D2 90 nop C0 Flush ICACHE P 010772D4 02 move w d2 r0 ICCMR 20 9C 02 P 010772D8 90 nop C0 P 010772DA 90 nop C0 P 010772DC 41 move l d1 r6 96 P 010772DE 08 bmclr 2 d0 l 00 A0 02 Unlock ICACHE P 010772E2 00 move w d0 r0 ICCR 20 9C 00 P 010772E6 90 nop C0 wake_core123_soft_reset P 010772E8 20 mov...

Page 1125: ...ze GIC VIRQ Interrupts to edge P 01077312 30 move l 0f000000 d0 00 20 00 8F 00 P 01077318 B0 move l d0 r2 GICR 56 initialize ETH P 0107731A 20 move w 7100 d0 60 91 00 P 0107731E 00 move l d0 r2 MACCFG2 C2 85 04 P 01077322 30 move l 004d0000 d0 00 20 00 80 4D P 01077328 00 move l d0 r2 DMA_MR C2 80 38 P 0107732C C0 move w 3 d0 83 P 0107732E 00 move l d0 r2 MIIMCFG C2 85 20 initialize TDM RIR TDM TI...

Page 1126: ...3 9F E8 P 01077354 2B adda 4000 r3 r3 4B 80 00 P 01077358 00 move w d0 r3 TDM3RIR 23 9F F0 P 0107735C 00 move w d0 r3 TDM3TIR 23 9F E8 initialize SIU P 01077360 10 move w r6 PPC_ACR d0 06 80 28 P 01077364 7C asrr 8 d0 68 P 01077366 08 bmclr 000f d0 l 00 A0 0F P 0107736A 09 bmset 0005 d0 l 00 A0 05 P 0107736E 00 move b d0 r6 PPC_ACR 16 80 28 P 01077372 30 move l da54789e d0 78 38 9E 9A 54 P 0107737...

Page 1127: ... RSR d0 86 8C 90 P 010773A4 0C bmtstc 0001 d0 l 00 A0 01 P 010773A8 81 bt wake_core123_soft_reset 41 SIU MEMC INIT P 010773AA 01 move l d1 r2 DIBAR11 A2 80 20 P 010773AE 09 bmset 00c1 d1 l 01 A0 C1 P 010773B2 37 move l ffe00000 d7 18 20 00 BF E0 P 010773B8 07 move l d7 r2 DIAMR11 A2 80 38 P 010773BC 07 move l d7 r6 OR11 SET OR11 l2 l1c0 l1c1 l1c2 l1c3 86 81 5C P 010773C0 01 move l d1 r6 BR11 SET B...

Page 1128: ...3E4 01 move l d1 r6 BR10 SET BR10 gpcm local bus 0x021e0000 0x021effff 64K 86 81 50 P 010773E8 08 bmclr 0003 d7 h fffc0008 d7 17 A0 03 P 010773EC 08 bmclr 0008 d7 l fffc0000 d7 07 A0 08 P 010773F0 07 move l d7 r2 DIAMR9 A2 80 28 P 010773F4 09 bmset 0008 d7 l fffc0008 d7 SETA 1 PSDVAL is generated after external logic asserts GTA 07 A0 08 P 010773F8 21 move w 0218 d1 base address for ip 0x02180000 ...

Page 1129: ... 7B add 5 d7 00030045 d7 C5 P 0107742A 07 move l d7 r6 MDR 86 81 88 P 0107742E 19 move w 0 r5 0D A0 00 P 01077432 37 move l 90051248 d7 read burst 10 32 48 90 05 P 01077438 07 move l d7 r6 MCMR 86 81 78 P 0107743C 37 move l 00030c48 d7 00 2C 48 80 03 P 01077442 07 move l d7 r6 MDR 86 81 88 P 01077446 19 move w 0 r5 0D A0 00 P 0107744A 7B add 4 d7 00030c4c d7 C4 P 0107744C 07 move l d7 r6 MDR 86 81...

Page 1130: ...r5 0D A0 00 P 01077474 37 move l 90051258 d7 write single beat 10 32 58 90 05 P 0107747A 07 move l d7 r6 MCMR 86 81 78 P 0107747E 27 move w 0040 d7 00 80 40 P 01077482 07 move l d7 r6 MDR 86 81 88 P 01077486 19 move w 0 r5 0D A0 00 P 0107748A 7B add 5 d7 0045 d7 C5 P 0107748C 07 move l d7 r6 MDR 86 81 88 P 01077490 19 move w 0 r5 0D A0 00 P 01077494 37 move l 90051260 d7 write burst 10 32 60 90 05...

Page 1131: ...0774BC 27 move w 0044 d7 00 80 44 P 010774C0 07 move l d7 r6 MDR 86 81 88 P 010774C4 19 move w 0 r5 0D A0 00 P 010774C8 67 inc d7 0045 d7 EF P 010774CA 07 move l d7 r6 MDR 86 81 88 P 010774CE 19 move w 0 r5 0D A0 00 P 010774D2 37 move l 9005127c d7 exception 10 32 7C 90 05 P 010774D8 07 move l d7 r6 MCMR 86 81 78 P 010774DC 37 move l ff000001 d7 18 20 01 BF 00 P 010774E2 07 move l d7 r6 MDR 86 81 ...

Page 1132: ... 01077508 09 bmset 1 d1 l Valid bit set 01 A0 01 P 0107750C 01 move l d1 r6 BR10 86 81 50 P 01077510 D1 cmpeq w 0 d3 A0 P 01077512 80 bt external_memory 0B P 01077514 D1 cmpeq w 1 d3 A1 P 01077516 2D bt wait_virq FF 9D 33 P 0107751A 9E debug 70 external_memory P 0107751C 6C clr d0 10 P 0107751E 00 move w d0 IFUR_ADDR E0 3F 60 80 F0 P 01077524 90 nop C0 r3 d5 d5 ISB P 01077526 CB move l d5 r3 45 P ...

Page 1133: ...2c P 0107753E 34 clr d9 00 A0 04 6C 90 P 01077544 34 clr d11 00 A0 04 6D 90 P 0107754A 38 move l d9 VIRTUAL_REG_ADDR 20 A0 00 01 62 2F 20 81 07 P 01077554 10 move l r2 DCIR d0 A2 80 40 P 01077558 36 extractu 4 28 d0 d9 00 A0 04 30 C9 81 1C P 01077560 51 move l r6 d1 96 P 01077562 01 move l d1 SIUMCR_IMAGE_ADDR 62 2F 30 81 07 P 01077568 0E bmtset 0200 d1 l 01 A2 00 P 0107756C 80 bt ecc_cont 27 Lock...

Page 1134: ... l 00 A0 02 Unlock ICACHE P 0107758C 00 move w d0 r7 ICCR 27 9C 00 P 01077590 90 nop C0 ecc_cont P 01077592 D1 cmpeq w 4 d3 A4 P 01077594 25 bt from_i2c 18 87 E0 from_tdm_uart P 01077598 6F clr d7 90 P 0107759A 2C move w LOGIC_STATE_1 r4 60 99 72 P 0107759E 38 move l CRC_TABLE_ADDR r10 20 A0 00 3A 60 3C 74 81 07 P 010775A8 08 bmclr 0200 r5 h 1D A2 00 P 010775AC 36 move w 7abf d15 20 A0 00 27 60 9A...

Page 1135: ...4 7F E8 P 010775D0 34 move w r10 r0 d0 80 A0 00 A0 90 P 010775D6 34 eor d0 d15 00 A0 04 DF 90 P 010775DC 36 ift eor a001 d15 l 22 A0 00 0A A7 A0 01 P 010775E4 36 and 0ffff d15 d15 00 A8 04 3F FF 9F FF P 010775EC 36 move l 55660000 d6 08 20 00 95 66 P 010775F2 36 insert 4 8 d9 d6 00 A8 00 32 EE 81 08 P 010775FA 38 move l CALC_CRC_ADDR r15 20 A0 00 3F 60 3B 4E 81 07 P 01077604 38 move l NEXT_BYTE_AD...

Page 1136: ..._RESET TDM3RIR RFTL pulse RSTL pulse RFSD 01 One cycle delay P 0107762A C0 move w 0010 d0 90 P 0107762C 00 move w d0 r3 TDM3RIR 2 23 9F F2 TDM3TIR TFTL pulse TSTL pulse TSO 0 sync input TAO 0 Not drive data on inactive channel P 01077630 78 add 4 d0 0014 d0 44 P 01077632 00 move w d0 r3 TDM3TIR 2 23 9F EA TDM3RFP and TDM3TFP by adaption procedure TDM3TDBS 0x017 P 01077636 78 add 3 d0 0017 d0 43 P ...

Page 1137: ... F8 P 0107765E 01 move l TDM3TER_ADDR d1 E6 3F 38 81 F8 P 01077664 00 move l d0 TDM3RER_ADDR E2 3F 40 81 F8 P 0107766A 01 move l d1 TDM3TER_ADDR E2 3F 38 81 F8 P 01077670 C0 move w 0001 d0 81 P 01077672 00 move l d0 r3 TDM3ACR A3 9F B0 P 01077676 39 move l BASE_IP_8 r1 C0 20 00 81 F8 ams_sub P 0107767C 6C clr d1 90 P 0107767E C2 move w 11 d2 91 loop_ams P 01077680 10 move l r3 TDM3ASR d0 A3 9F 30 ...

Page 1138: ... 84 bf asdr_match_16 0F P 010776A4 34 move l 0001010d d4 00 21 0D 80 01 P 010776AA 04 move l d4 r1 TDM3RFP A1 9F E0 P 010776AE 88 bra check_ams_tx 4B asdr_match_16 P 010776B0 D0 cmpeq w f d1 AF P 010776B2 84 bf asdr_match_192 19 P 010776B4 0D bmtsts bff8 r1 l A9 BF F8 P 010776B8 34 move l 0001011d d4 00 21 1D 80 01 P 010776BE 94 ift bmclr 0001 d4 l C2 08 04 A0 01 P 010776C4 04 move l d4 r1 TDM3RFP...

Page 1139: ...E1 P 010776EE D8 aslw d1 d1 91 P 010776F0 09 bmset 011c d1 l 01 A1 1C P 010776F4 01 move l d1 r1 TDM3RFP A1 9F E0 check_ams_tx P 010776F8 10 move l r3 TDM3ACR d0 A3 9F B0 P 010776FC 0D bmtsts 0002 d0 l 00 A0 02 P 01077700 80 bt activ_chan 0D P 01077702 C0 move w 0003 d0 83 P 01077704 00 move l d0 r3 TDM3ACR A3 9F B0 P 01077708 E9 suba 8 r1 68 P 0107770A 8F bra ams_sub 73 activ_chan P 0107770C 6C c...

Page 1140: ...1077734 85 bf init_rcpr F5 init_tcpr P 01077736 34 deceqa r14 80 A0 00 EE F6 P 0107773C 34 tfra r14 r0 20 A0 00 E8 EE P 01077742 E8 asl2a r0 FE P 01077744 E8 adda r3 r0 1B P 01077746 00 move l d0 r0 TDM3TCPR_BASE A0 88 00 P 0107774A 85 bf init_tcpr ED TDM3RCPR_0 P 0107774C 32 move l 80006e00 d2 70 2E 00 80 00 P 01077752 02 move l d2 r3 TDM3RCPR_0 83 90 00 TDM3TCPR_CHIP_ID NEED to clear Transmit bu...

Page 1141: ...777E 28 adda TDM3LOCALMEM_BASE r0 r0 08 98 00 P 01077782 40 move l d0 r0 90 P 01077784 B0 move l d0 r0 4 41 P 01077786 28 adda 400 r0 r0 08 84 00 P 0107778A 40 move l d0 r0 90 P 0107778C B0 move l d0 r0 4 41 P 0107778E C0 move 2l d0 d1 r1 19 P 01077790 C0 move 2l d0 d1 r1 19 P 01077792 C0 move 2l d0 d1 r1 19 P 01077794 C0 move w 0001 d0 81 P 01077796 00 move l d0 r3 TDM3RCR A3 9F A8 P 0107779A 00 ...

Page 1142: ...ADDR r9 20 A0 00 09 E6 3F 60 81 F8 P 010777C6 08 move l TDM3RER_ADDR r0 E6 3F 40 81 F8 P 010777CC 0D bmtsts 0008 r0 l 08 A0 08 P 010777D0 2D bt ams_start FF 9E 83 tdm_next_byte_c P 010777D4 34 cmpeqa r9 r7 20 A0 00 EF A9 P 010777DA 81 btd tdm_loop_data D8 P 010777DC 34 tfra r14 r0 20 A0 00 E8 EE P 010777E2 E8 adda r7 r0 1F tdm_load_data P 010777E4 C5 move 2l r0 d4 d5 10 tdm_next_byte P 010777E6 38...

Page 1143: ... 08 A0 08 P 01077804 08 move l TDM3TDBDR_ADDR r0 E6 3F 58 81 F8 P 0107780A 2D bt ams_start FF 9E 49 P 0107780E 36 bmtstc 0002 d11 h 20 A0 00 0C 13 A0 02 P 01077816 84 bf tdm_check_tx_end 15 tdm_tx_loop P 01077818 34 cmpeqa r0 r11 80 A0 00 EB A8 P 0107781E 81 bt tdm_check_tx_ret 9F P 01077820 8F brad tdm_check_tx_ret 9C P 01077822 36 bmset 0002 d11 h 20 A0 00 09 13 A0 02 tdm_check_tx_end P 0107782A...

Page 1144: ...3 tdm_wait P 0107784A 08 move l TDM3TDBDR_ADDR r0 E6 3F 58 81 F8 P 01077850 90 nop C0 P 01077852 34 cmpeqa r0 r11 80 A0 00 EB A8 P 01077858 81 bt tdm_wait F3 tdm_wait_to_end P 0107785A 08 move l TDM3TDBDR_ADDR r0 E6 3F 58 81 F8 P 01077860 90 nop C0 P 01077862 34 cmpeqa r0 r11 80 A0 00 EB A8 P 01077868 85 bf tdm_wait_to_end F3 P 0107786A 20 move w 13ff d0 00 93 FF P 0107786E 00 move w d0 WBCR_ADDR ...

Page 1145: ...94 00 move l d0 r3 TDM3RGBA A3 9F C0 P 01077898 00 move l d0 r3 TDM3TGBA A3 9F B8 P 0107789C 00 move l d0 r3 TDM3RCPR_0 83 90 00 P 010778A0 00 move l d0 r0 TDM3TCPR_BASE A0 88 00 tdm_uart_i2c_finish P 010778A4 00 move l d0 r2 SCIBR 82 90 00 P 010778A8 00 move l d0 r2 SCICR 82 90 08 P 010778AC 00 move l d0 r2 PAR 82 82 18 P 010778B0 00 move l d0 r2 PSOR 82 82 20 P 010778B4 10 move l r6 BR10 d0 BR10...

Page 1146: ... move w 028b d1 00 82 8B P 010778E2 D1 cmpeq w 3 d3 A3 P 010778E4 80 bt non_fast_mode 05 P 010778E6 C1 move w 1 d1 81 non_fast_mode P 010778E8 01 move l d1 r2 SCIBR 82 90 00 P 010778EC C1 move w 0004 d1 84 P 010778EE 01 move l d1 r2 SCICR 82 90 08 uart_loop_data P 010778F2 36 bmtstc 0002 d11 h 20 A0 00 0C 13 A0 02 P 010778FA 84 bf uart_check_transmit_end 51 P 010778FC 36 bmtstc 0001 d11 h 20 A0 00...

Page 1147: ...0107791E 0D bmtsts c000 d0 l C0 A0 00 P 01077922 85 bf uart_check_tx_ret E5 P 01077924 36 extractu 8 18 d14 d5 00 A8 00 3C CD 82 18 P 0107792C 05 move l d5 r2 SCIDR 82 90 18 P 01077930 34 asll 8 d14 00 A0 04 7F 48 P 01077936 D2 cmpeq w 0003 d4 23 P 01077938 34 ift tfr d7 d14 02 A0 04 77 57 P 0107793E 66 deceq d4 6D P 01077940 85 bf uart_check_tx_ret C7 P 01077942 36 bmset 0002 d11 h 20 A0 00 09 13...

Page 1148: ...1 btd tdm_uart_i2c_finish 40 P 01077966 36 bmclr 0003 d11 h 20 A0 00 08 13 A0 03 P 0107796E 8F bra uart_check_tx_ret 99 P 01077970 9E debug 70 state_1 P 01077972 D0 cmpeq w 11 d1 B1 P 01077974 34 jf r12 80 A0 00 9C 67 state_1_t P 0107797A 36 bmclr 000f d11 l 20 A0 00 08 03 A0 0F P 01077982 34 clr d12 00 A0 04 6E 10 P 01077988 34 jmpd r15 80 A0 00 9F 60 P 0107798E 2C move w LOGIC_STATE_2_1 r4 60 99...

Page 1149: ... 09 P 010779AE 8F brad state_1 C4 P 010779B0 2C move w LOGIC_STATE_1 r4 60 99 72 state_2_2_t P 010779B4 34 jmpd r15 80 A0 00 9F 60 P 010779BA 2C move w LOGIC_STATE_2_3 r4 60 99 BE state_2_3 P 010779BE 34 cmpeq w 44 d1 11 80 44 P 010779C2 80 bt state_2_3_t 09 P 010779C4 8F brad state_1 AE P 010779C6 2C move w LOGIC_STATE_1 r4 60 99 72 state_2_3_t P 010779CA 34 jmpd r15 80 A0 00 9F 60 P 010779D0 2C ...

Page 1150: ... 010779EC 34 jmpd r15 80 A0 00 9F 60 P 010779F2 36 bmset 01 d11 l 20 A0 00 09 03 A0 01 state_4 P 010779FA 34 cmpeq d1 d10 00 A0 04 71 61 P 01077A00 84 bf state_4_t 0B P 01077A02 36 bmset 02 d11 l 20 A0 00 09 03 A0 02 state_4_t P 01077A0A 34 jmpd r15 80 A0 00 9F 60 P 01077A10 2C move w LOGIC_STATE_5 r4 60 9A 14 state_5 P 01077A14 0D bmtsts ff d1 l 01 A0 FF P 01077A18 34 jfd r15 80 A0 00 9F 66 P 010...

Page 1151: ... A0 00 9F 60 P 01077A3C 2C move w LOGIC_STATE_6_2 r4 60 9A 40 state_6_2 P 01077A40 36 insert 8 8 d1 d8 00 A0 04 32 E8 82 08 P 01077A48 34 jmpd r15 80 A0 00 9F 60 P 01077A4E 2C move w LOGIC_STATE_6_3 r4 60 9A 52 state_6_3 P 01077A52 36 insert 8 10 d1 d8 00 A0 04 32 E8 82 10 P 01077A5A 34 jmpd r15 80 A0 00 9F 60 P 01077A60 2C move w LOGIC_STATE_7_1 r4 60 9A 64 state_7_1 P 01077A64 75 tfr d1 d2 51 P ...

Page 1152: ...7A7A 2C move w LOGIC_STATE_7_3 r4 60 9A 7E state_7_3 P 01077A7E 32 insert 8 10 d1 d2 EA 82 10 P 01077A82 34 jmpd r15 80 A0 00 9F 60 P 01077A88 2C move w LOGIC_STATE_7_4 r4 60 9A 8C state_7_4 move w LOGIC_STATE_8_1 r4 insert 8 18 d1 d2 P 01077A8C 9A C0 32 EA 82 18 90 C0 2C 60 9A E8 addr_update asrw d2 d0 move l d1 r0 P 01077A98 94 C0 D8 1A C8 41 P 01077A9E 34 cmpeq w 01fc d0 10 81 FC move l 00083b7...

Page 1153: ...eq w 010e d0 move l r6 d1 P 01077AB8 96 C0 34 10 81 0E CE 49 asrr 11 d1 asrr 4 d0 P 01077AC0 3C F1 7C 64 P 01077AC4 94 ift insert f 11 d1 d2 C2 32 EA 83 D1 move l d2 r8 move l r0 d1 P 01077ACA 36 20 A0 00 C8 42 C8 49 P 01077AD2 34 ift jmp r15 82 A0 00 9F 61 P 01077AD8 D0 cmpeq w 10 d0 30 P 01077ADA 90 nop C0 P 01077ADC 34 jmpd r15 80 A0 00 9F 60 P 01077AE2 34 ift adda r5 r8 ...

Page 1154: ...AF4 32 insert 8 8 d1 d2 EA 82 08 P 01077AF8 34 cmpeq d2 d12 00 A0 04 72 62 P 01077AFE 34 jfd r12 80 A0 00 9C 66 P 01077B04 2C move w LOGIC_STATE_1 r4 60 99 72 P 01077B08 36 bmtsts 01 d11 l 20 A0 00 0D 03 A0 01 P 01077B10 34 clr d12 00 A0 04 6E 10 P 01077B16 94 ift move w LOGIC_STATE_9 r4 C2 2C 60 9B 3C P 01077B1C 94 iff move w LOGIC_STATE_9_C r4 C3 2C 60 9B 28 P 01077B22 34 jmp r12 80 A0 00 9C 61 ...

Page 1155: ...77B3C 34 deceq d8 00 A0 04 64 6D P 01077B42 34 move b d1 r8 80 A0 00 91 80 P 01077B48 94 ift move w LOGIC_STATE_10_1 r4 C2 2C 60 9B 98 calc_crc P 01077B4E 34 eor d12 d1 00 A8 00 DC 94 bmtsts 0080 d1 l move l d1 r0 P 01077B54 96 C0 C8 41 0D 01 A0 80 P 01077B5C 08 bmclr ff80 r0 l E8 BF 80 P 01077B60 34 asrr 8 d12 00 A0 04 7E 68 P 01077B66 34 move w r10 r0 d1 80 A0 00 A1 90 P 01077B6C 34 eor d1 d12 0...

Page 1156: ...ta FF 9D 6F P 01077B88 0D bmtsts 0007 r7 l 0F A0 07 P 01077B8C EF inca r7 41 P 01077B8E 2E bfd tdm_next_byte FF 9C 59 P 01077B92 08 bmclr ff00 r7 l EF BF 00 P 01077B96 8C bra tdm_next_byte_c 3F state_10_1 P 01077B98 75 tfr d1 d2 51 P 01077B9A 34 jmpd r12 80 A0 00 9C 60 P 01077BA0 2C move w LOGIC_STATE_10_2 r4 60 9B A4 state_10_2 P 01077BA4 36 bmtsts 1 d11 l 20 A0 00 0D 03 A0 01 P 01077BAC 34 jfd r...

Page 1157: ...BCA 84 bf rn_not_inc 09 P 01077BCC 34 inc d10 00 A0 04 65 6F rn_not_inc P 01077BD2 36 iff bmclr 8 d11 l 23 A0 00 08 03 A0 08 P 01077BDA 34 tfr d15 d2 00 A8 00 75 57 P 01077BE0 74 tfr d2 d0 52 P 01077BE2 34 eor d10 d0 00 A8 00 DC 12 P 01077BE8 0D bmtsts 0080 d0 l 00 A0 80 P 01077BEC 31 and 0007f d0 d0 18 80 7F P 01077BF0 C8 move l d0 r0 40 P 01077BF2 7D asrr 8 d2 68 P 01077BF4 34 move w r10 r0 d0 8...

Page 1158: ...0C 36 bmtsts 8 d11 l 20 A0 00 0D 03 A0 08 P 01077C14 36 insert 8 0 d10 d6 00 A8 00 34 EE 82 00 P 01077C1C 36 bmset 0001 d11 h 20 A0 00 09 13 A0 01 P 01077C24 36 ift bmset 10 d11 l 22 A0 00 09 03 A0 10 P 01077C2C D1 cmpeq w 2 d3 A2 P 01077C2E 84 bfd uart_send_ack 32 P 01077C30 39 move l 01076f00 r1 60 2F 00 81 07 P 01077C36 38 move l TDM3TDBDR_ADDR r11 20 A0 00 0B E6 3F 58 81 F8 P 01077C40 E9 adda ...

Page 1159: ... 80 A0 00 9C 60 P 01077C6E 34 tfr d6 d14 00 A0 04 77 56 CRC 16 table inital_crc 0x0000 crc crc 8 crc_table_16 crc BYTE_IN 0xff CRC_16_table size of 512 Bytes size of 256 Bytes with 0xa001 operation crc_table P 01077C74 dcw 0000 P 01077C76 dcw c0c1 P 01077C78 dcw c181 P 01077C7A dcw 0140 P 01077C7C dcw c301 P 01077C7E dcw 03c0 P 01077C80 dcw 0280 P 01077C82 dcw c241 P 01077C84 dcw c601 P 01077C86 d...

Page 1160: ...P 01077CDA dcw 1540 P 01077CDC dcw d701 P 01077CDE dcw 17c0 P 01077CE0 dcw 1680 P 01077CE2 dcw d641 P 01077CE4 dcw d201 P 01077CE6 dcw 12c0 P 01077CE8 dcw 1380 P 01077CEA dcw d341 P 01077CEC dcw 1100 P 01077CEE dcw d1c1 P 01077CF0 dcw d081 P 01077CF2 dcw 1040 P 01077CF4 dcw f001 P 01077CF6 dcw 30c0 P 01077CF8 dcw 3180 P 01077CFA dcw f141 P 01077CFC dcw 3300 P 01077CFE dcw f3c1 P 01077D00 dcw f281 ...

Page 1161: ...2c_txrx_bit d2 sda scl pin value i2c_sample_gpio i2c_assert_stop i2c_txrx_bit i2c_assert_start d3 sda scl pin value i2c_txrx_bit d4 bit position i2c_txrx_byte i2c_assert_stop i2c_txrx_bit d5 transmit byte i2c_txrx_bit i2c_read_SequantialData d6 receive byte i2c_txrx_byte i2c_txrx_bit i2c_read_SequantialData d7 control byte bit 0 tx 0 rx 1 i2c_txrx_byte i2c_assert_stop i2c_txrx_bit i2c_read_Sequant...

Page 1162: ...A0 00 27 00 81 00 i2c_start P 01077D98 6C clr d0 10 P 01077D9A 00 move w d0 r2 PAR 02 82 18 P 01077D9E 00 move w d0 r2 PSOR 02 82 20 P 01077DA2 34 tfr d8 d0 00 A8 00 74 50 P 01077DA8 34 move w d0 r9 80 A0 00 40 11 P 01077DAE 00 move w d0 r2 PDIR 02 82 10 P 01077DB2 00 move w d0 r2 PODR 02 82 00 P 01077DB6 23 bsr i2c_WaitFor_StartCond_BusFreeTime 18 82 1C P 01077DBA 34 clr d10 00 A0 04 6D 10 P 0107...

Page 1163: ...00 20 20 80 07 next_block P 01077DE6 34 move 2l r12 d14 d15 A0 A0 00 C7 14 P 01077DEC 34 tfra r3 r11 80 A0 00 EB EB P 01077DF2 EC tfra r1 r4 E9 P 01077DF4 34 move w c d12 20 A0 00 C4 8C P 01077DFA 88 bra i2c_cont_1 0B nmi 0 exeption offset 0xe00 P 01077E00 org p 0e00 BASE_EXEPTION_TABLE nmi0_exeption P 01077E00 9E debug 70 P 01077E02 9F rte 73 i2c_cont_1 P 01077E04 36 bmclr 0100 d11 h write data t...

Page 1164: ...20 A0 00 BA C9 P 01077E2A 34 iff cmpeq d0 d9 03 A0 04 70 E0 P 01077E30 BC move l r1 8 r4 CA P 01077E32 36 iff bmset 0100 d11 h 23 A0 00 09 13 A1 00 P 01077E3A 88 bra i2c_cont_2 0B nmi 1 exeption offset 0xe40 P 01077E40 org p 0e40 BASE_EXEPTION_TABLE nmi1_exeption P 01077E40 9E debug 70 P 01077E42 9F rte 73 i2c_cont_2 P 01077E44 23 bsr i2c_read_SequantialData 18 80 A4 P 01077E48 92 ift bra i2c_star...

Page 1165: ...xt_block_addr 3F P 01077E72 B0 move l r1 c d0 CB P 01077E74 64 zxt l d0 60 P 01077E76 34 not d10 d1 00 A8 00 D8 82 P 01077E7C 88 bra i2c_cont_3 09 nmi 2 exeption offset 0xe80 P 01077E80 org p 0e80 BASE_EXEPTION_TABLE nmi2_exeption P 01077E80 9E debug 70 P 01077E82 9F rte 73 i2c_cont_3 P 01077E84 36 insert 10 10 d1 d10 00 A0 04 32 EA 84 10 P 01077E8C 34 cmpeq d0 d10 00 A0 04 71 60 P 01077E92 80 bt ...

Page 1166: ...77EBC 21 bra i2c_cont_4 18 80 08 nmi 3 exeption offset 0xec0 P 01077EC0 org p 0ec0 BASE_EXEPTION_TABLE nmi3_exeption P 01077EC0 9E debug 70 P 01077EC2 9F rte 73 i2c_cont_4 P 01077EC4 34 cmpeqa r14 r10 A0 A0 00 EA AE P 01077ECA 80 bt i2c_finish 0B P 01077ECC 34 tfra r10 r3 20 A0 00 EB EA P 01077ED2 8F bra next_block 15 i2c_finish P 01077ED4 6C clr d0 10 P 01077ED6 34 move l d0 r9 80 A0 00 40 91 P 0...

Page 1167: ...rg p 0f00 BASE_EXEPTION_TABLE nmi4_exeption P 01077F00 9E debug 70 P 01077F02 9F rte 73 i2c_read_SequantialData_1 P 01077F04 6E clr d5 90 P 01077F06 CB move l r3 d0 48 P 01077F08 30 extractu 3 10 d0 d5 CD 80 D0 P 01077F0C 62 asl d5 d5 E2 P 01077F0E 09 bmset a0 d5 l 05 A0 A0 P 01077F12 CF move l d5 r7 45 P 01077F14 2B bsr i2c_txrx_byte FF 91 7F P 01077F18 92 ift rts C2 9F 71 P 01077F1C 6E clr d5 90...

Page 1168: ...ASE_EXEPTION_TABLE nmi5_exeption P 01077F40 9E debug 70 P 01077F42 9F rte 73 i2c_read_SequantialData_cont_2 P 01077F44 2B bsr i2c_assert_start FF 92 61 P 01077F48 CF move l r7 d5 4D P 01077F4A 09 bmset 1 d5 l 05 A0 01 P 01077F4E 2B bsr i2c_txrx_byte FF 91 45 P 01077F52 92 ift rts C2 9F 71 read_byte_loop P 01077F56 34 deceq d12 00 A0 04 66 6D P 01077F5C C7 move w 1 d7 81 P 01077F5E 94 ift bmset 2 d...

Page 1169: ...bug 70 P 01077F82 9F rte 73 i2c_mem_write P 01077F84 34 tfra r8 r4 20 A0 00 EC E8 P 01077F8A 36 bmtsts 0100 d11 h 20 A0 00 0D 13 A1 00 P 01077F92 EB inca r3 41 P 01077F94 92 iff move b d6 r4 C3 96 9C P 01077F98 EC inca r4 41 P 01077F9A 36 bmtstc 0001 d11 h 20 A0 00 0C 13 A0 01 P 01077FA2 90 nop C0 P 01077FA4 92 ift asll 8 d6 C2 7F 48 P 01077FA8 34 eor d6 d10 00 A0 04 DD 16 P 01077FAE 36 bmchg 0001...

Page 1170: ...9F rts 71 i2c_WaitFor_StartCond_BusFreeTime P 01077FD2 20 move w HALF_BUS_FREE_TIME d0 00 8C 85 busfree_loop P 01077FD6 2B bsr i2c_sample_gpio FF 90 EF P 01077FDA 0D bmtsts SCL_SDA_11 d2 l C2 A0 00 P 01077FDE 85 bf i2c_WaitFor_StartCond_BusFreeTime F5 P 01077FE0 64 deceq d0 6D P 01077FE2 85 bf busfree_loop F5 P 01077FE4 20 move w BUS_FREE_TIME d0 00 99 0B wait_loop P 01077FE8 2B bsr i2c_sample_gpi...

Page 1171: ...MSC8113 Reference Manual Rev 0 Freescale Semiconductor C 61 EF wait_rts P 01077FFC 9F rts 71 ...

Page 1172: ...MSC8113 Reference Manual Rev 0 C 62 Freescale Semiconductor MSC8113 Boot Code ...

Page 1173: ...sfer Attribute signals 13 2 Global GBL 13 7 Transfer Burst TBST 13 6 Transfer Code TC 0 2 13 6 Transfer Size TSIZ 0 3 13 7 Transfer Type TT 0 4 13 6 60x compatible address bus 1 21 60x compatible bus mode 13 14 60x compatible system bus 13 1 multi master bus mode B 15 8 bit data format UART 21 5 8 Byte Receive Buffer Descriptor RxBD 25 144 8 Byte Transmit Data Buffer Descriptor TxBD 25 137 9 bit d...

Page 1174: ...mode 14 17 asynchronous SRAM like interface 14 1 asynchronous write access using Dual Strobe mode 14 13 asynchronous write access using Single Strobe mode 14 15 Asynchronous Synchronous mode DSISYNC bit 14 35 atomic 9 14 atomic access 1 2 atomic bus operation 12 10 atomic operation 11 3 Atomic Operation ATOM bits 12 98 B BADDR 27 28 3 11 BADDR 27 31 12 12 BADDR30 3 11 Bank Base bits 9 19 bank inte...

Page 1175: ...nal memory 6 1 external memory device 6 3 host DSI 6 1 6 4 system bus 6 1 6 4 ISBSEL values 6 3 TDM 6 1 6 4 UART 6 1 6 13 boot chip select operation 12 44 Boot Mode BM 0 2 5 3 Boot Mode Indication BM bits 4 18 boot options 1 8 boot procedure 8 28 boot ROM 8 11 boot sequence 6 1 bootloader program definition B 3 bootstrap ROM 1 2 Boundary Scan Register BSR 18 2 18 17 BR 3 11 13 18 break characters ...

Page 1176: ...st division factor BUS DF 7 7 configuration 7 7 generation 7 2 timing 12 49 collisions 25 21 Command Buffer BUFCMD bit 12 107 Command Opcode OP bits 12 108 Commands Bits C 9 37 Common TDM Signals CTS bit 20 36 compare or test operations B 1 Compare Value COMPVAL bits 22 15 Compatibility Mode Enable ETM bit 4 11 configuration source CNFGS 5 2 Configuration Protection Logic block diagram 4 3 Continu...

Page 1177: ... DCR HTAAD 14 30 DCR HTADT 14 30 DCR LEDS 14 30 DCR RPE 14 30 DCR SLDWA 14 30 DCR SNGLM 14 30 DDR DSIDIS 14 35 DDR DSISTP 14 35 Debug mode 9 34 9 39 18 2 Debug Mode DM bit 9 36 DEBUG_REQUEST instruction 18 5 18 7 Dedicated Enable DD 31 0 bits 23 11 Default Attribute Register DATTR 25 136 DER OVF 14 36 Destination Address Field DA bits 9 37 destination address recognition 25 25 DIAMRx AM 14 33 DIBA...

Page 1178: ...Polarity DPL bit 16 36 DREQ Sensitivity Mode DRS bit 16 36 DSI 8 12 DSI 32 bit mode 14 4 DSI 64 Bit Data Bus DSI64 5 3 DSI 64 bit mode 14 5 DSI Access Mode Signal 14 13 DSI address map 8 61 DSI addressing modes 14 6 14 8 14 9 DSI Asynchronous mode 14 12 DSI Big Endian mdoe 14 10 DSI Chip ID Register DCIR 6 4 14 34 A 71 DSI configuration 14 27 DSI Control Register DCR 14 1 14 29 A 69 DSI data bus 1...

Page 1179: ...ram 9 6 error handling 25 41 ESP 2 5 Ethernet 25 1 Ethernet Control Register ECNTRL 25 57 Ethernet controller 25 5 Ethernet controller programming model 25 49 Ethernet initialization and reset 25 46 Ethernet signals 25 10 Even Parity EPAR bit 4 12 event counter 22 1 LICBIER 17 37 exception local bus contention with memory bus Xa Xb or P 9 7 misaligned data 9 6 X and P memory bus contention 9 7 Exc...

Page 1180: ...Flag FE bit 21 29 framing error UART 21 17 freeze core 9 8 Freezes Channel FRZ bit 16 37 full duplex multiple UART system 21 3 Full Duplex mode 25 21 full duplex port 21 1 G GBL 3 11 9 25 13 19 GCIER IRQx 17 28 GEIER DMA 17 27 GEIER IRQx 17 27 GEIER PIT 17 27 GEIER TMCNM 17 27 GEIER UART 17 27 General Interrupt Controller GIC 19 2 General Line 0 Control G0CLx bits 12 109 General Purpose Register G...

Page 1181: ...0 Host Control Register HCR 20 53 Host Interface HDI16 Host Control Register HCR 20 53 Host Transfer Acknowledge HTA 14 1 HRCW ISB 4 20 HRESET 3 4 HRW 14 11 HSMPRx SMPVAL 15 2 HTA Actively Driven HTAAD bit 14 30 HTA Drive Time HTADT bits 14 30 I ICABR area base 9 20 ICache non real time debugging 9 25 real time debugging 9 25 ICache attributes 9 28 ICache code position distribution 9 26 ICache com...

Page 1182: ... 9 20 A 19 Instruction Fetch Unit Configuration Register IF UR A 20 Instruction FU Configuration Register IFUR 9 20 INT_OUT 3 15 17 1 INT_OUT Drive Control INTODC bit 4 19 INT_OUT generation 17 6 Interface Status Register ISR 25 89 Internal Bank Interleaving within Same Device Disable IBID bit 12 100 internal memory controller 1 21 Internal Memory Map Register IMMR 4 20 A 31 internal memory system...

Page 1183: ... routing of MSC8101 interrupts 17 19 setting interrupt table base address in VBA reg ister 17 19 setting the interrupt base address in the VBA register 17 21 typical interrupt routine that uses a service rou tine 17 23 use of di and ei instructions to disable and en able interrupt requests 17 23 VBA register holds 20 MSB of the interrupt ta ble base address 17 21 Vector Address Bus VAB 17 18 Vecto...

Page 1184: ... 36 LIC Group B Interrupt Enable Register LICBIER 17 37 A 55 LIC Group B Interrupt Error Status Register LIC BIESR 17 39 LIC Group B Interrupt Status Register LICBISR 17 38 A 55 LIC Interrupt Sources 17 13 LIC Programming Model 17 29 LICAICR EMx 17 30 LICAICR0 IMAPx 17 30 LICAICR1 EMx 17 31 LICAICR1 IMAPx 17 31 LICAICR2 EMx 17 32 LICAICR2 IMAPx 17 32 LICAICR3 EMx 17 33 LICAIER Ex 17 37 LICBICR0 EM...

Page 1185: ...nagement interface 25 9 Map Selection of Interrupt Source 15 8 IMAPx bits 17 32 17 35 Map Selection of Interrupt Source 23 16 IMAPx bits 17 31 17 34 Map Selection of Interrupt Source 31 24 IMAPx bits 17 30 17 34 Map Selection of Interrupt Source 7 0 IMAPx bits 17 36 MAR A 12 111 Mask Masters Requests MMR bit 4 19 Mask Number MASKNUM bits 4 21 maskable interrupt sources 17 2 Maximum Frame Length Re...

Page 1186: ... configurations 12 14 timing examples 12 25 UPMs user programmable machines address control bits 12 59 address multiplexing 12 59 clock timing 12 49 data sample control 12 59 data valid 12 59 EDO interface example 12 74 exception requests 12 48 loop control 12 58 memory access requests 12 47 memory system interface example 12 63 programming the UPM 12 49 RAM array 12 50 RAM word 12 51 refresh time...

Page 1187: ...address space 8 1 8 11 MSC8101 multi master bus mode B 15 MSC8113 default memory map 8 3 MSC8113 dual bus architecture 12 2 MSC8113 interrupt system 17 1 multi master bus mode B 15 multiple master design support 1 21 multiple master designs 1 3 multiply accumulate MAC units 2 3 multi task support 9 32 munged little endian 1 3 Munged Little Endian mode PPCLE bit 14 35 MxMR AMx 12 108 MxMR BSEL 12 1...

Page 1188: ...ge hit checking 12 8 Page Mode Select PMSEL bit 12 100 Page Based Interleaving PBI bit 12 104 page mode SDRAM machine 1 3 page mode support and pipeline accesses 12 16 PAR DD 23 11 parallel arithmetic operations 2 3 B 5 Parallel Input Register PIREG 18 2 parity bit generation UART 21 10 parity byte select PBSE 12 11 Parity Byte Select Enable PBSE bit 4 18 Parity Enable Bit PE 21 26 parity error 12...

Page 1189: ...R 23 10 A 99 Pin Special Options Register PSOR 23 12 A 100 Pipeline Maximum Depth PLDP bit 4 11 pipeline mode one level 13 35 pipelining 12 11 PIT Interrupt PIT bit 17 26 17 27 PITC PITC 4 29 PITR PIT 4 29 PODR OD 23 10 POE 3 17 Polarity POL0 bit 22 10 Polarity POL4 bit 22 10 PORESET 3 3 3 16 5 2 25 46 PORESET 3 3 3 16 Port Data Direction Register PDIR 23 9 Port Data Direction Registers Direction ...

Page 1190: ...ecution order 9 11 QBus Mask Register 8 11 QBus Mask Register 0 8 11 QBus Mask Register 0 2 QBUSMR 0 2 9 19 QBus Mask Register 2 8 11 QBus Mask Registers 1 2 QBUSMR 1 2 A 18 QBus system 9 1 QBUSBR bank base 9 19 QBUSMR bank mask 9 19 quad word SC140 bit size i xxiii R RAM word 12 51 Read Channel RD bit 16 41 Read Loop Field RLFx bits 12 109 Read Prefetch Enable RPE bit 14 30 READ_PIREG instruction...

Page 1191: ... bit 20 65 Receive Sync Error Event Enable RSEEE bit 20 60 Receive Sync Level RSL bit 20 43 Receive Sync Synchronization Status RSSS bits 20 68 Receive T1 frame RT1 bit 20 48 Receive Undersize Packet Counter RUND 25 115 Receive Unified Buffer Mode RUBM bit 20 48 Receive Unknown OPCode Packet Counter TX UO 25 112 Received Bit 8 R8 21 30 Received Bits 7 0 R 7 0 21 30 Receiver Active Flag RAF bit 21 ...

Page 1192: ...Base MIB 25 105 RMON support 25 23 Row Start Address Bit ROWST bits 12 99 PDMTER 16 44 RSTCONF 3 3 rules for arbitration 13 18 run mode UART 21 22 RxBD Data Length Register RBDLEN 25 80 RxBD Pointer 0 3 RBPTRx 25 82 S SAMPLE PRELOAD instruction 18 5 18 6 SC140 core 1 2 SC140 core internal address space 8 1 8 8 SC140 DSP core 9 2 SC140 DSP core programming model 2 8 SC140 extended core 9 1 SC140 in...

Page 1193: ...0 Single MSC8113 bus mode 13 14 Single Wire mode UART 21 22 single wire UART connection 21 4 SIU interrupt 17 6 SIU Module Configuration Register SIUMCR 4 17 A 29 SIU programming model 4 10 SIU timers 4 4 SIUMCR BBD 4 17 SIUMCR BCTLC 4 19 SIUMCR BM 4 18 SIUMCR CLKOD 4 20 SIUMCR CS5PC 4 19 SIUMCR DPPC 4 18 SIUMCR ESE 4 17 SIUMCR INTODC 4 19 SIUMCR INTOUT 4 18 SIUMCR IRPC 4 18 SIUMCR MMR 4 19 SIUMCR...

Page 1194: ...ister PPC_ALRH i xxiv 4 14 System Bus Arbitration Level Register PPC_ALRL 4 15 System Bus Arbitration Level Register High PPC_ALRH A 26 System Bus Arbitration Level Register Low PPC_ALRL A 26 System Bus Assigned SDRAM Refresh Timer PSRT 12 111 System Bus Assigned UPM Refresh Timer PURT 12 111 A 48 System Bus Error Status and Control Registers TESCRx 12 112 system bus interface 4 1 system bus monit...

Page 1195: ...D MxRIER A 86 TDM 0 3 Receiver Interface Registers TDMxR IR A 75 TDM 0 3 Transmit Channel Parameter Registers 0 255 TDMxTCPR 0 255 A 85 TDM 0 3 Transmit Control Registers TDMxT CR A 82 TDM 0 3 Transmit Data Buffer First Threshold TDMxTDBFT A 83 TDM 0 3 Transmit Data Buffer Second Threshold TDMxTDBST A 84 A 121 TDM 0 3 Transmit Data Buffer Size TDMxT DBS A 79 TDM 0 3 Transmit Event Registers TDMxTE...

Page 1196: ...xRNB 20 64 TDMx Receive Status Register TDMxRSR 20 67 TDMx Transmit Channel Parameter Register 0 255 TDMxTCPR 0 255 20 59 TDMx Transmit Control Register TDMxTCR 20 54 TDMx Transmit Data Buffer Size TDMxTDBS 20 51 TDMx Transmit Data Buffers Displacement Reg ister TDMxTDBDR 20 63 TDMx Transmit Data Buffers First Threshold TD MxTDBFT 20 55 20 56 TDMx Transmit Data Buffers Second Threshold TDMxTDBST 2...

Page 1197: ...nal 18 3 TEA 3 15 13 37 13 40 TERA CF 22 18 TERB CF 22 19 TESCR1 BM 4 23 TESCR1 DMD 4 23 TESCR1 EXT 4 23 TESCR1 ISBE 4 23 TESCR1 TC 4 23 TESCR1 TT 4 23 TESCR1 WP 4 23 TESCR2 BNK 4 24 TESCR2 LCL 4 24 TESCR2 PB 4 24 TESCR2 REGS 4 24 TESR1 PAR 4 23 test access port TAP 18 1 TGCRA DIR0 22 9 TGCRA DIR4 22 9 TGCRA INTP 22 9 TGCRB INTP 22 10 TGCRB POL0 22 10 TGCRB POL4 22 10 TGCRB TOG0 22 10 TGCRB TOG4 2...

Page 1198: ...E 4 26 TMCNTSC TCF 4 26 TMS signal 18 3 18 4 restriction 18 17 toggle timer 22 1 transfer burst TBST 13 23 transfer burst signal TBST 13 23 Transfer Code TC bit 16 41 Transfer Code TC bits 4 23 4 25 transfer code TC 0 2 13 22 Transfer Code Pin Configuration TCPC bits 4 18 transfer size TSIZ 0 3 13 23 Transfer Size TSZ bits 16 41 transfer size signals TSIZ 0 3 13 23 Transfer Type TT bits 4 23 4 25 ...

Page 1199: ...Frame Counter TOVR 25 125 Transmit Packet Counter TPKT 25 118 Transmit Pause Control Frame Counter TXPF 25 119 Transmit Reversed Data Order TRDO bit 20 46 Transmit Second Threshold Event TSTE bit 20 67 Transmit Second Threshold Event Enabled TST EE bit 20 61 Transmit Second Threshold Level TSTL bit 20 45 Transmit Single Collision Packet Counter TSCL 25 121 Transmit Status Register TSTAT 25 70 Tran...

Page 1200: ...er requests 12 48 requests 12 46 signal negation 12 60 software requests 12 48 UPWAIT signal 12 60 wait mechanism 12 60 Upper Boundary Value UB bits 9 36 URXD 21 1 User Programmable Machines UPMs 12 1 12 45 user programmable machines UPMs 1 3 UTXD 21 1 V VALID 9 25 valid bit 9 28 Valid Bit V 12 98 Valid Bit Array Line Content VS bits 9 38 Valid Bit Array Status Register VBASR 9 38 VBASR VS 9 38 Ve...

Page 1201: ... SC140 bit size i xxiii Write Buffer WB 9 7 Write Buffer Control Register WBCR A 20 Write Loop Field WLFx bits 12 109 Write Protect WP bit 12 97 Write Protect Error WP bit 4 23 4 25 Write Recovery Time WRC bits 12 106 write after read WARA 12 10 X X and P contention 9 7 XDBA 2 3 XDBB 2 3 ...

Page 1202: ...MSC8113 Reference Manual Rev 0 Index 30 Freescale Semiconductor Index ...

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