NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 413 -
Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
5.16.3 Block Diagram
Figure 5.16-1 UART Block Diagram
TX_FIFO
The transmitter is buffered with a 64/16 byte FIFO to reduce the number of interrupts presented to the
CPU.
RX_FIFO
The receiver is buffered with a 64/16 byte FIFO (plus three error bits per byte) to reduce the number of
interrupts presented to the CPU.
TX shift Register
This block is the shifting the transmitting data out serially control block.
RX shift Register
This block is the shifting the receiving data in serially control block.
Baud Rate Generator
Divide the external clock by the divisor to get the desired baud rate clock. Refer to baud rate equation.
IrDA Encode
This block is IrDA encode control block.
IrDA Decode
This block is IrDA decode control block.
Control and Status Register
This field is register set including the FIFO control registers (UA_FCR), FIFO status registers
APB_BUS
UART / IrDA / LIN / RS-485 Device or Transceiver
UART_CLK
IrDA Decode
RX Shift Register
RX_FIFO
TX_FIFO
TX Shift Register
IrDA Encode
Baud Rate
Generator
Control and Status
Registers
Serial Data In
Serial Data Out
Baud Out
Baud Out
Status & Control
Status & Control
