Nuvoton NUC970 series, Technical Reference Manual

Page: 912 / 1251

NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 912 - Revision V1.30
NUC97
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SD Host DMA Transfer Starting Address Register (SDH_DMASA)
Register Offset R/W Description Reset Value
SDH_DMASA 0x408 R/W SD Host DMA Transfer Starting Address Register 0x0000_0000
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR ADDR/ORDER
Bits Description
[31:0]
ADDR
DMA Transfer Starting Address
This field indicates a 32-bit starting address of system memory (SRAM/SDRAM) for DMA to
retrieve or fill in data.
If DMA is not in normal mode, this field will be interpreted as a starting address of Physical
Address Descriptor (PAD) table.
[0]
ORDER
Determined to the PAD Table Fetching Is in Order or Out of Order
0 = PAD table is fetched in order.
1 = PAD table is fetched out of order.
Note: the bit 0 is valid in scatter-gather mode when SGEN (SDH_DMACTL[3]) = 1.
NOTE: Starting address of the SDRAM must be word aligned, for example, 0x0000_0000,
0x0000_0004, etc.
The diagram shown below describes the format of PAD table. Note that the total byte count of all Pads
must be equal to the byte count filled in FMI engine.
The EOT is the End of PAD Table. The EOT should be set to 1 in the last descriptor.
The byte count has to be the multiple of 4 bytes.
SDRAM Physical Base Address
Next Descriptor Physical Base Address
Byte Count
EOT
Reserved
Byte 0 Byte 1 Byte 2 Byte 3
Figure 5.26-1 PAD (Physical Address Descriptor) Table Format
The diagram shown below indicates how SDH feteched the PAD tables. SDH feteched next PAD