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NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 452 -
Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
UART n Line Control Register (UAn_LCR)
Register
Offset
R/W
Description
Reset Value
UAn_LCR
n=0,1,2,3,4,5,6,7
,8,9,10
U0x00C R/W
UART n Line Control Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
BCB
SPE
EPE
PBE
NSB
WLS
Bits
Description
[31:7]
Reserved
Reserved.
[6]
BCB
Break Control
0 = The serial data output (TX) is not forced to the Spacing State (logic 0).
1 = The serial data output (TX) is forced to the Spacing State (logic 0).
Note:
This bit acts only on TX and has no effect on the transmitter logic.
[5]
SPE
Stick Parity Enable Control
0 = Stick parity Disabled.
1 = If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0. If bit 3 is 1
and bit 4 is 0 then the parity bit is transmitted and checked as 1.
[4]
EPE
Even Parity Enable Control
0 = Odd number of logic 1’s is transmitted and checked in each word.
1 = Even number of logic 1’s is transmitted and checked in each word.
Note:
This bit is effective only when bit 3 (parity bit enable) is set.
[3]
PBE
Parity Bit Enable Control
0 = No parity bit.
1 = Parity bit is generated on each outgoing character and is checked on each incoming
data.
[2]
NSB
Number of
“STOP Bit”
0= One “ STOP bit” is generated in the transmitted data.
1= One and a half “ STOP bit” is generated in the transmitted data when 5-bit word length
is selected;.
Note:
Two “STOP bit” is generated when 6-, 7- and 8-bit word length is selected.
[1:0]
WLS
Word Length Selection
00 = 5-bit character length.