NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
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Revision V1.30
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translation. The MMU puts the translated physical addresses into the MMU Translation Lookaside
Buffer TLB.
The MMU TLB has two parts, the main TLB and the lockdown TLB. The main TLB is a two-way,
set-associative cache for page table information. It has 32 entries per way for a total of 64 entries.
The lockdown TLB is an eight-entry fully-associative cache that contains locked TLB entries.
Locking TLB entries can ensure that a memory access to a given region never incurs the penalty
of a page table walk.
The MMU features are:
Standard ARM architecture v4 and v5 MMU mapping sizes, domains, and access
protection scheme
Mapping sizes are 1MB (sections), 64KB (large pages), 4KB (small pages), and 1KB
(tiny pages)
Access permissions for large pages and small pages can be specified separately for
each quarter of the page (subpage permissions)
Hardware pag e table walks
Invalidate entire TLB using CP15 c8
Invalidate TLB entry selected by MVA, using CP15 c8
Lockdown of TLB entries using CP15 c10.
5.1.4 Caches and Write Buffer
The ARM926EJ-S processor includes an Instruction Cache (I-Cache), a Data Cache (D-Cache)
and a write buffer. The size of I-Cache and D-Cache in this chip is 16 KB, respectively.
The caches features are:
The caches are virtual index, virtual tag, addressed using the Modified Virtual Address
(MVA). This enables the avoidance of cache cleaning and/or invalidating on context
switch.
The caches are four-way set associative, with a cache line length of eight words per
line (32 bytes per line), and with two dirty bits in the D-Cache.
The D-Cache supports write-through and write-back (or copy back) cache operations,
selected by memory region using the C and B bits in the MMU translation tables.
Allocate on read-miss is supported. The caches perform critical-word first cache
refilling.
Pseudo-random or round-robin replacement selectable by the RR bit in CP15 c1.
Cache lockdown registers enable control over which cache ways are used for
allocation on a linefill, providing a mechanism for both lockdown and controlling cache
pollution.
The D-Cache stores the Physical Address (PA) tag corresponding to each D-Cache
entry in the tag RAM for use during cache line write-backs, in addition to the Virtual
Address tag stored in the tag RAM. This means that the MMU is not involved in D-
Cache write-back operations, removing the possibility of TLB misses related to the
write-back address.
The PLD data preload instruction does not cause data cache linefills. It is treated as a
NOP instruction.
