Nuvoton NUC970 series, Technical Reference Manual, Page: 232 / 1251

NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 232 - Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
SDRAM Mode Register (SDIC_MR)
The SDRAM mode registers is used to configure the Mode Register of SDRAM device. This Mode
Register value will be applied to both SDRAM 0 and SDRAM 1 devices.
Write this register, the SDRAM controller will generate a Load Mode Register (LMR) command to the
SDRAM device.
Register Offset R/W Description Reset Value
SDIC_MR S 0x018 R/W SDRAM Mode Register 0x0000_0032
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved Configure
7 6 5 4 3 2 1 0
Configure LATENCY BrstType BrstLength
Bits Description
[31:14]
Reserved
Reserved.
[13:7]
Configure
SDRAM Dependent Configuration
The value of this field is SDRAM type dependent. The definition of bits in this field is different
between SDR SDRAM, DDR SDRAM and DDR2 SDRAM. Please refer the SDRAM initial
sequence and related SDRAM specification to know what value should be configured in this field.