Nuvoton NUC970 series, Technical Reference Manual, Page: 181 / 1251

NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 181 - Revision V1.30
NUC97
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Clock Divider Control Register 9 (CLK_DIVCTL9)
Register Offset R/W Description Reset Value
CLK_DIVCTL9 0x044 R/W Clock Divider Control Register 9 0x0000_0000
31 30 29 28 27 26 25 24
CKO_N
23 22 21 20 19 18 17 16
Reserved CKO_S CKO_SDIV
15 14 13 12 11 10 9 8
SDH_N
7 6 5 4 3 2 1 0
Reserved SDH_S SDH_SDIV
Bits Description
[31:24] CKO_N
Reference Clock Out Divide
This field defines the clock divide number for clock divider to generate the reference clock output
The actual clock divide number is (CKO_N + 1). So,
CKO_CLK = CKO_SrcCLK / (CKO_N + 1).
[23:21]
Reserved
Reserved.
[20:19] CKO_S
Reference Clock Out Source Selection
This field selects which clock is used to be the source of reference clock output.
00 = CKO_SrcCLK is from XIN.
01 = Reserved.
10 = CKO_SrcCLK is from ACLKOut.
11 = CKO_SrcCLK is from UCLKOut.
[18:16] CKO_SDIV
Reference Clock Out Source Clock Divider
This field defines the source clock divide number for clock divider of APLL and UPLL output. This
field only takes effect while the CKO_S (CLK_DIVCTL9[20:19
]) is 2’b10 (APLL) or 2’b11 (UPLL).
If CKO_S (CLK_DIVCTL9[20:19
]) is 2’b10,
ACLKOut = APLLFout ÷ (CK 1).
If CKO_S (CLK_DIVCTL9[20:19
]) is 2’b11,
UCLKOut = UPLLFout ÷ (CK 1).
[15:8] SDH_N
SD Host Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for SD
host controller.
The actual clock divide number is (SDH_N + 1). So,
SDH_CLK = SDH_SrcCLK / (SDH_N + 1).
[7:5] Reserved Reserved.