NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
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Revision V1.30
NUC97
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CHNIC
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NUA
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collision filtering.
Time Stamping Engine for IEEE 1588
5.21.5.7
The EMAC supports a time stamping engine for IEEE Std. 1588. In this time stamping engine, a
64-bit counter implemented to generate the reference timing, the registers EMACn_TSSEC and
ETSLSR.
In frame transmission, if TSEN (EMACn_TSCTL[0]) and TTSEN of TXDES 0 (TXDMA Descriptor
Word 0) are both high, EMAC would store the 64-bit reference timing value to TXDES 1 (TXDMA
Descriptor Word 1) and TXDES 2 (TXDMA Descriptor Word 2) when frame transmission
completed.
In frame reception, if TSEN (EMACn_TSCTL[0]) is high, EMAC would store the 64-bit reference
timing value to RXDES 1 (RXDMA Descriptor Word 1) and RXDES 3 (RXDMA Descriptor Word 3)
when the frame reception finished.
The figure shown below describes how the 64-bit counter works to generate the reference timing.
The 64-bit counter formed by two 32-bit counters, the EMACn_TSSEC and EMACn_TSSUBSEC,
a
updated using the EMAC’s input reference clock, the HCLK. Two difference methods, controlled
by TSMODE (EMACn_TSCTL[3]), implemented to increase 32-bit EMACn_TSSUBSEC counter
by value configured in register EMACn_TSINC. When TSMODE (EMACn_TSCTL[3]) is low,
TSLSR counter increased in every clock. When TSMODE (EMACn_TSCTL[3]) is high, TSLSR
counter increased only when accumulator is overflow.
Time Stamp Addend Register
(EMAC_TSADDNED)
Accumulator
+
Overflow
0
1
TSMODE
(EMAC_TSCTL[2])
1'b1
Time Stamp Counter Sub Second
Register (EMAC_TSSUBSEC)
Increase
+
Time Stamp Increment Register
(EMAC_TSINC)
Increase
Time Stamp Counter Second Register
(EMAC_TSSEC)
32-bit
32-bit
+
1'b1
Figure 5.21-3 64-bit Reference Timing Counter
Magic Packet Parsing Engine
5.21.5.8
The EMAC supports a Magic packet parsing engine for recognizing Magic packet. The Magic
packet is a broadcast frame which payload includes 6 bytes of 0xFF, followed by 16 repetitions of
