NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 95 -
Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
Reset Source Active Status Register (SYS_RSTSTS)
Register
Offset
R/W
Description
Reset Value
SYS_RSTSTS
0x06C R/W
Reset Source Active Status Register
0x0000_00XX
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
KPIRSTS
WDTRSTS
CPURSTS
CHIPRSTS
LVRRSTS
PINRSTS
PORRSTS
Bits
Description
[31:7]
Reserved
Reserved.
[6]
KPIRSTS
Chip Reset by KPI Status
0 = No reset from KPI.
1 = The KPI had issued reset signal to reset the chip.
[5]
WDTRSTS
Chip Reset by Watchdog Timer Status
0 = No reset from watchdog timer.
1 = Watchdog timer had issued reset signal to reset the chip.
[4]
CPURSTS
CPU Reset by CPU_LVL (AHBIPRST[1]) or CPU_PLS (AHBIPRST[2]) Status
0 = No CPU reset from CPU_LVL (AHBIPRST[1]) or CPU_PLS (AHBIPRST[2]).
1 = CPU_LVL (AHBIPRST[1]) or CPU_PLS (AHBIPRST[2]) has been high to reset the
CPU.
[3]
CHIPRSTS
Chip Reset by CHIP (AHBIPRST[0]) Status
0 = No reset from CHIP (AHBIPRST[0]).
1 = CHIP (AHBIPRST[0]) has been high to reset CPU.
[2]
LVRRSTS
Chip Reset by LVRD Status
0 = No reset from LVRD.
1 = LVRD had issued reset signal to reset the chip.
[1]
PINRSTS
Chip Reset by NRESET Pin Status
0 = No reset from nRESET pin.
1 = nRESET pin had issued reset signal to reset the chip.
[0]
PORRSTS
Chip Reset by POR Status
0 = No reset from POR.
1 = POR had issued reset signal to reset the chip.